GB2403833A

GB2403833A - Resteering a failing speculation check instruction by sending a branch offset immediate value to the pipeline

Info

Publication number: GB2403833A
Application number: GB0423198A
Authority: GB
Inventors: James Douglas Gibson; Rohit Bhatia
Original assignee: Hewlett Packard Co
Current assignee: HP Inc
Priority date: 2000-02-16
Filing date: 2001-01-29
Publication date: 2005-01-12
Anticipated expiration: 2021-01-29
Also published as: GB0423198D0; GB2403833B

Abstract

A method for resteering a failing speculation check instruction is disclosed. A calculation is speculated, the validity of the calculation is checked using a CHK instruction, and if the calculation is invalid, a recovery target address is calculated. Calculating the recovery address comprises, sending a branch offset immediate value to the pipeline and sending a current instruction pointer (IP) corresponding to the CHK instruction to the pipeline. The recovery target address is then calculated, using an IP-relative branch adder to add the immediate value and the current IP value. The pipeline then branches to the recovery target address. The recovery target address may be sent to an instruction fetch unit that retrieves a target instruction and sends the instruction to the pipeline. The immediate value may be stored in a register of an integer data path and routed to a branch unit of the pipeline. The current IP may be routed from an exception handling unit (or XPN unit) to the branch unit. The immediate value, the current IP value and the recovery address may be tracked through the pipeline using a sequencer.

Description

1 Method and Apparatus for Resteering Failing Speculation Check

Instructions

2 Field

3 The technical field relates generally to digital computer systems. More particularly, 4 it relates to a method and an apparatus forprocessing branching instructions in a processor.

Background

6 Typical computer systems have a number of common components. These 7 components include a central processing unit (CPU), a bus, memory, and peripheral 8 devices. In high-speed computers, the CPU may be a superscalar, pipelined 9 microprocessor. A superscalar, pipelinedmicroprocessorcan include an instruction fetch unit and multiple pipelines. The instruction fetch unit fetches instructions and forwards them 1 to a pipeline. In the pipeline, the instructions flow through multiple pipeline stages, after 12 which the results of the instructions are committed to an architectural state (i.e., memory).

13 A pipelined microprocessor performs parallel processing in which instructions are 14 executed in an assembly-line fashion. Consecutive instructions are operated upon in sequence, but several instructions are initiated before a first instruction is complete. In this 16 manner, instructions step through each stage of aparticularpipeline, one instruction per 17 stage per pipeline at a time.

18 With respect to instructions processed by a pipeline, methods exist by which data 19 and control functions are speculated. These methods also include means by which the control- or data-speculative calculation is checked for success or failure using a speculation 21 check instruction, also referred to as "chk" instruction. The speculation check instruction 22 checks for a certain condition in the instruction stream. If that condition fails, then the 23 system branches to the target specified in the chk instruction. Existing methods, however, 24 do not efficientl yhandle mix-speculation. In existing methods, if the speculation fails, the system does not implement the branching behavior defined by the L\-64 architecture.

26 Instead, existing methods handle the failing speculation check instruction through software, 27 rather than using the hardware. These methods cause a fault and invoke a fault handler, 28 which emulates the branching behavior, rather than using hardware to resteer the instruction 29 stream. However, treating exceptions through the fault handler is inefficient.

1 What is needed is a method for implementing a resteer upon the oeeurrenee of a 2 failing speculation check instruction, rather than faulting to improve performance. In 3 particular, it is desirable to unpiement a resteer method that substantially uses preexisting 4 hardware k' further- increase eiticiency.

6 Summary

7 The present invention Is defined in the appendant Claims.

8 A netloti and an apparatus lor restcering tailing speculation check instructions in 9 the pipeline of a processor. A hrancl1 offset imnediatc value and an instruction pointer correspond to each speculation cheek instruction. i hese values are used to determine the I correct recovery target atidr-ess. A relative adder- adds the immediate value and the 12 instruction pointed value to arrive at the correct address. rlhis is done lay flushing tle 13 pipeline upon the occurrence <-if a failing speculation cheek instnetion. The pipeline flus 14 is extended to resteer the machine to the recovery target address. The finrnediate value and i 5 the instncton pointer arc titan routed through the existing data paths of the pipcliric, into 6 the relative adder, which calculates the rcccJver-y target address. sequencer tracks the 17 progression of these values through the pipclne and effects a branch at the desired time.

18 1hc system nary be optionally ununpiemcnted by setting it to fault upon the 19 occurrence of a tailing speculation check nstructior1 rather than hitiating a hrancl1 resteer.

If the fault is tngerccl, then a fault handler Is invoked and uses software to> emulate the 21 branch. Also, the systc-n nary be set to operate only it it is first detennincd that the hra2lcil 22 will actually arrive at its dcsthation. This is done by ensuring that certain Faults will not 23 prevent a branch.

Summary of Drawings

26 Figure I is a flow chart of the method of the system.

27 Figure 2 is a flow chart SilOWhig the rcstc-ering mcth:>d.

28 Figure 3 is a block diagram showing the computer system implementing the 29 method.

Iigure 4 is a block more detailed diagram Cal tlc computer- system of Figure 3. - 2

1 Detailed Descupffon 2 The system is a method and an apparatus for resteering a failing speculation check 3 instruction. By way of illustration only and not by way of limitation, the system is 4 explained in the context of the IA-64 architecture. One skilled in the art will recognize that the method can be implemented on any system that uses speculative instructions, performs 6 a speculation check, and has the ability to resteer the instruction execution based on the 7 speculation check.

8 The IA-64 architecture provides a speculation check instruction (chk) to determine 9 the validity of a control- or data-speculative calculation. If the chk instruction fails, a branch to IP + target25 is taken by the machine, hereafter referred to as a "check resteer." 11 The IA-64 architecture is described more fully in the IA-64 Application Instruction Set 12 Architecture Guide, Revision 1.0, copyright Intel Corporation / Hewlett-Packard Company 13 (1999). The branching behavior may be optionally unimplemented Previous methods have 14 not used the branching behavior of the IA-64 architecture and have provided no means for resteering the speculation check instructions through the existing hardware. Instead, 16 existing methods trigger a fault upon the detection of a mix- speculation and invoke a fault 17 handler, which is inefficient. The system implements the branching behavior available on 18 the IA-64 architecture and largely uses hardware that is already used in the processor.

19 Figure 1 shows a flow chart of the method of the system. In operation, a control- or data-speculative calculation speculates 100 the result of an operation. The speculated result 21 is then checked 1] 0 using a chk instruction. If the speculation was correct 120, then the 22 processor continues to process 130 pipelined instructions. If the speculation was incorrect, 23 then the L\-64 architecture performs a check resteer. The method then determines 150 24 whether check resteering has been implemented and enabled. If check resteering is not enabled, then a fault is triggered 200 and a fault handler is invoked. In prior methods, 26 check resteering was not implemented, so a fault was always triggered at this stage and the 27 fault handler invoked. The system implements the check resteering - 3 1 behavior so this is always "implemented." One embodiment also includes an "on/off 2 switch" allowing the user to selectively enable and disable the check resteer function.

3 If check resteering has been enabled 150, then the system determines 170 whether 4 certain architectural conditions aremettoallowcheckresteering. In one embodiment of the system, check resteering is not allowed unless four conditions are met. The LA-64 6 architecture defines values for certain status registers. In one embodiment it is desirable to 7 implement the check resteer upon the following conditions of four status register values.

8 These conditions are represented by the following four enable bits in the PSR register, 9 which must be set to the corresponding conditions to allow branching: PSR.ss = 0; PSR.tb = 0, PSR.ic = 1, and PSR.it = 1.

11 The PSR.ss refers to a single step trap enable. PSR.tb refers to a branch trap 12 enable. PSR.ic refers to an interruption collection enable. PSR.it refers to instruction 13 translation enable. That is, single step traps and branch traps are not enabled, but interrupt 14 collection and instruction translation are enabled. These bits are described more fully in the IA-64 ISA Guide. In normal operation of the LA-64 processor, these enable bits are set 16 to satisfy the implementation of the system. When operating in real mode, rather than, for 17 example, virtual address translation mode or debug mode, these control bits are set to allow 18 implementation of the check resteering.

19 These conditions are used to ensure that when a branch or a check resteer is taken architecturally it will arrive at the desired target. For example, in the case of a branch trap, 21 a branch trap handler is used. This would make resteering difficult, so instead, in one 22 embodiment the check resteering does not occur when a branch trap is taken. Instead, a 23 branch fault is taken 200, and the fault handler is invoked to handle a speculation fault by 24 emulating the failing speculation check instruction.

If the above conditions are met and branching is allowed, then the exception data 26 handler (also referred to as the "XPN unit" or "XPN block") 24 "flushes" 180 the core 27 pipeline 20. That is, it clears 180 all pending instructions in various stages of processing in 28 the pipeline20. The XPNunit24 also extends 180 this pipeline flush toimplement 190 the 29 instruction stream. That is, the XPN unit 24 prevents the fetch engine 22 from sending any further instructions to the core pipeline 20 until the failing speculation check instruction has 1 been resteered. In one embodiment, the XPN unit 24 extends the pipeline flush for at least 2 eight clock cycles. During this extended pipeline flush, the failing speculation check 3 instruction is resteered 190 to its recovery target address.

4 Figure 2 is a more detailed diagram of the resteer method. After the pipeline 20 has been flushed and during the following clock cycles, the XPN unit 24 sends 192 a 6 current instruction pointer (IP) 50 to the core pipeline 20. The XPN unit 24 also sends a 7 control signal 54 to an IIM register 30 in the integer data path (lDP) 28. This control signal 8 54 allows the IIM register 30 to hold an immediate value 60 from the failing speculation 9 check instruction. The immediate value 60 is an IP-relative, signed branch offset value.

The IDP 28 then sends the immediate value to the core pipeline 20 where the immediate 11 value is sign-extended to a 64-bit value. Within the core pipeline 20, the sign-extended 12 immediate value 60 and the current IP value 50 are added together 196 using an IP-relative 13 adder. The result of this relative add function becomes the recovery target address 58, 14 which is also referred to as the target IP 58. A sequencer 26 in the XPN unit 24 tracks the progression of the immediate value and the current IP through the core pipeline 20. At the 16 appropriate point in the core pipeline 20, the XPN unit 24 causes the failing speculation 17 check instruction to branch 198 to the recovery target address 58. This is done by sending 18 the target IP 58 back to the instruction fetch unit 22. The instruction fetch unit 22 then 19 restarts the program execution at the recovery target address. In one embodiment, the pipeline remains cleared and stalled until the instruction fetch unit 22 sends the instruction 21 from the recovery target address 58 to the core pipeline. When the instruction is sent, the 22 pipeline stall is released and the pipeline continues processing new instructions.

23 Figure 3 shows a simplified block diagram of a microprocessor 10 having a core 24 pipeline 20 and an instruction fetch unit 22 that sends instructions to the pipeline 20. The instructions are processed in multiple stages within the pipeline 20 and eventually output to 26 an architectural state, or memory. The processor 10 also has an XPN unit 24. At one 27 stage of the pipeline 20, erroneously speculated instructions are identified by the chk 28 instruction, and an indication of the mix-speculation 52 is given to the XPN unit 24.

29 The processor 10 also has a sequencer 26. In the embodiment shown in Figure 3, the sequencer 26 is part of the XPN unit 20. Upon the failure of a chk instruction, the 1 sequencer 26 flushes the pipeline 20 by canceling any pending instructions using a stall 2 control signal 56. The sequencer 26 also controls the fetch engine 22 and, in the case of a 3 mix-speculation, prevents the instruction fetch unit 22 from sending new instructions to the 4 pipeline 20 until the failing speculative instruction has been resteered, using the stall control signal 56. In one embodiment, this effectively extends the pipeline flush for at least 6 eight cycles while the instruction stream is resteered.

7 Upon the failure of a speculated instruction, the processor 10 resteers the 8 instruction to the correct address by causing the instruction to branch to a recovery target 9 address re-created from the relative sum of the current IP 50 and a sign-extended immediate value 60. The XPN unit 20 sends the current EP 50 to the branch unit 18 of the 11 core pipeline 20 on an exception resteer bus 330. The XPN unit 20 also sends an 12 immediate control signal 54 to an IIM register 30 on the IDP 28. This signal 54 causes the 13 IIM 30 to hold the immediate value 60 of the failing instruction. The immediate value 60 is 14 then sent along the IDP 28 to the branch unit 18 of the core pipeline 20.

Once in the core pipeline 20, the immediate value 60 and the current IP value 50 16 are processed though the pipeline stages like any other relative address function. The 17 immediate value 60 is sign-extended to become a 64-bit value. The sign- extended 18 immediate value 60 and the current IP value 50 are added together using a relative adder 19 410. The output of the adder 410 is the recovery target address 58, or target IP 58, of the failing speculation check instruction. As the current IP value 50 and the immediate value 21 60 progress through the core pipeline 20, the sequencer 26 keeps track of their position in 22 the pipeline 20. When they reach the proper point in the pipeline 20, the sequencer 26 23 causes the instruction stream to resteer to the recovery target address 58. This is performed 24 by sending the target IP 58 back to the instruction fetch unit 22 while the pipeline 20 is cleared and stalled. The instruction fetch unit 22 then sends the desired instruction to the 26 core pipeline 20, and the stall is released.

27 Figure 4 shows a partial hardware diagram of the data path of one embodiment. In 28 the embodiment shown in Figure 4, the method was implemented using existing hardware 29 so far as possible. One skilled in the art will recognize that Figure 4 is an abbreviated schematic of the data paths used in the system and the other paths and control systems are - 6 1not represented. Unassigned paths and inputs are paths and inputs used in the ordinary 2flow of instructions through the system and are not used in this branch resteer technique.

3Some paths and control functions used by the existing hardware are not shown.

4In a processor 10, an XPN unit 24 having control logic is used to detect a failing 5condition. Upon the detection of a failing condition, the XPN unit 24 issues a pipeline flush 6and also sends certain control information to the integer data path (IDP) 450 (and shown 7generally as blocks 370 through 440). The XPN unit 24 sends an immediate control signal 854 (not shown in Figure 4) that causes the IIM register 30 of the IDP 450 to store the 9immediate value 60 from the check instruction. The immediate value 60 is the signed 10extended branch offset that is used by the system in the event of a failing check.

11The value of the IIM register 30 is then sent through data-forwalding logic 380 and 12over to the branch unit 18 of the core pipeline 20. This value is then sent to amove-to 13branch (MTB) data detect register 390 and then to a multiplexer 400. The output of the 14multiplexor400 is fed into a relative adder41O, where it is added to the currentIPvalue 1550. At this point, the immediate value 60 has become a 64-bit sign- extended value.

16The XPN unit 24 uses a current instruction pointer (IP) 50 to track the relative 17addresses of instructions. Upon the detection of a failing speculation check instruction, the 18XPN unit 24 sends the current IP value 50 as data into the branch unit 18 of the core 19pipeline 20 on the exceptionresteerbus 330. In the core pipeline 20, the current IP value 2050 is sent through a register 340 before it passes through a multiplexer 350, another input 21of which is the normal data path. The output of the multiplexer 350 is fed into a bundle IP 22register (BndIpReg) 360, and then into the relative adder 410, where it is added to the 23sign-extended immediate value 60.

24In the embodiment shown, the output of the adder410 is then fed into an IP relative 25data execution register 420 and then into an IP relative data detect register 430. The 26output of that register then becomes one of the inputs of a multiplexer 440, the output of 27which leaves the core pipeline 20 and returns to the instruction fetch unit 22. Based on the 28output of the summation of the current IP value 50 and the signextended immediate value 2960, the instruction branches to the recovery target address 58. The branch occurs at a 1 designated point in the pipeline, and the sequencer 26 tracks the progress of these values 2 to ensure that the branch occurs at the designated point.

3 When the branch point is reached, the recovery target address 58, also referred 4 to as the target IP 58, is sent back to the instruction fetch unit 22. At this point, the pipeline 20 remains cleared and stalled by the stall control 56 of the sequencer 26. This prevents 6 new instructions from being sent by the instruction fetch unit 22 to the core pipeline 20.

7 When the instruction fetch unit 22 receives the target IP 58, the instruction fetch unit 22 8 delivers a new instruction to the core pipeline 20 based on the target IP 58. At this point, 9 the stall is released and the system continues to process new instructions.

One skilled in the art will recognize that the embodiment of the system shown in 11 Figure 4 resteers the failing speculation check instruction by reusing the processor's existing 12 data paths. A resteer could be performed without all of the hardware shown in Figure 4.

13 In the embodiment of Figure 4, however, the existing data paths of the processor include 14 this hardware. The embodiment shown leverages the existing hardware by allowing the immediate value 60 and current IP value 50 to travel through the same data paths normally 16 used to process instructions. By extending the pipeline flush, the system ensures that those 17 data paths will be available to resteer the instruction stream. Once the instruction stream 18 has been resteered, the stall is released.

19 Although the system has been described in detail with reference to certain embodiments thereof, variations are possible. For example, although the values of certain 21 data, sizes of the pipelines, particular logic elements, clock cycles, and other certain specific 22 information were given as examples, these examples were by way of illustration only, and 23 not by way of limitation. The system may be embodied in other specific forms without 24 departing from the essential spirit or attributes thereof. It is desired that the embodiments described herein be considered in all respects as illustrative, not restrictive, and that 26 reference be made to the appended claims for determining the scope of the invention.

Claims

Claims 1. A method for resteering a failing speculation check instruction

comprising: speculating a calculation; checking the validity of the speculated calculation using a chk instruction; and if the speculated calculation is invalid, calculating a recovery target address, wherein calculating the recovery target address further comprises: sending a branch offset immediate value to the pipeline; sending a current instruction pointer (IP) corresponding to the chk instruction to the pipeline; using an IP-relative branch adder to calculate the recovery target address by adding the immediate value and the current IP value branching to the recovery target address.
2. The method of claim 1, further comprising: sending the recovery target address to an instruction fetch unit that retrieves a target instruction corresponding to the recovery target address and sends the target instruction to the pipeline.
3. The method of claim 1 or claim 2, further comprising: storing the immediate value in a register of an integer data path; routing the immediate value to a branch unit of the pipeline; routing the current IP from an XPN unit to the branch unit; and routing the immediate value and the current IP to the IP-relative branch adder.
4. The method of claims I, 2 or 3, further comprising: tracking the progression of the immediate value, the current IP value, and the recovery target address through the pipeline using a sequencer; sending the recovery target address to the instruction fetch unit when the recovery target address reaches a predetermined point in the pipeline; fetching an instruction based on the recovery target address; and releasing a pipeline stall.
5. A method for resteering a failing speculation check instruction comprising: speculating a calculation; checking the validity of the speculated calculation using a chk instruction; and if the speculated calculation is invalid, calculating a recovery target address; determining whether a branch instruction would reach the recovery target address; and if the branch instruction would not reach the recovery target address, then faulting and invoking a fault handler to resteer the failing speculation check 1 0 instruction, otherwise branching to the recovery target address.
6. The method of claim 5, wherein the determining determines whether a branch instruction would reach the recovery target address by determining whether either a branch trap or a single step trap is taken.
7. The method of claims 5 or 6, further comprising: if the speculated calculation is invalid, clearing at least one pending instruction in a pipeline in which the failing instruction is being processed; preventing further instructions from entering the pipeline until the failing speculation check instruction has been resteered; and using at least one data path in the pipeline to calculate the recovery target address.
8. The method of claims 5, 6 or 7, further comprising: sending the recovery target address to an instruction fetch unit that retrieves a target instruction corresponding to the recovery target address and sends the target instruction to the pipeline.
9. The method of claim 5, wherein the method is implemented in an IA-64 architecture that operates in a real mode and in a virtual address translation mode, and wherein the step of determining comprises determining whether branching is enabled by checking status registers, and wherein the branching is only enabled when operating in the real mode.