GB2403081A

GB2403081A - Extending the performance of analogue to digital converters

Info

Publication number: GB2403081A
Application number: GB0314516A
Authority: GB
Inventors: Andrew Glascott-Jones
Original assignee: Individual
Current assignee: Individual
Priority date: 2003-06-21
Filing date: 2003-06-21
Publication date: 2004-12-22
Anticipated expiration: 2023-06-21
Also published as: GB0314516D0; GB2403081B

Abstract

An ADC with low sample rate and low analogue bandwidth is enabled to convert high speed signals with comparable accuracy to a high rate, high bandwidth converter. An input signal 1 is passed through a delay line with a plurality of taps connected, to an amplifier which sums the delayed signals together, hence slowing the signal. The resultant signal is then presented to an ADC 5 which converts to a digital representation. This is input to a digital processing unit 7 which performs the inverse function of the summed delay line to recreate the signal input to the delay line.

Description

Extending the Performance of ADCs

Background

This invention relates to high speed analogue signal acquisition, in particular to a circuit and method which can extend the performance of a low specification Analogue to Digital Converter (ADC).

To convert high speed signals requires specialized and expensive ADCs which have large analogue bandwidths and high sampling rates This invention enables an ADC with low sample rate and low analogue bandwidth, and hence lower cost, to convert high speed signals with comparable accuracy to a high rate, high bandwidth converter.

In conventional ADCs the input signal is sampled at a predetermined rate and compared against a reference voltage which can take the form of a resistor ladder ( a Flash type converter) or compared against delayed and subtracted versions of itself ( a pipeline converter).

Other methods include using a number of ADCs connected in parallel with a sequential triggering arrangement. Or the use of a very short pulse (of the order of Ips) to sample a repetitive signal (as in a sampling adaptor) Earlier patents for high speed sampling include: The FISO (US5200983), which uses a CCD delay line to sample the input signal.

A high speed analogue signal sampling system (US5521599) which uses a delay line with a delay lock system which enables greater precision in the timing of the samples.

A high speed sampling arrangement (US5257025), which uses a number of sampling circuits each at differing sample frequencies.

This patent proposes the uses of a tapped delay line to slow a signal in a precise and repeatable manner prior to conversion, followed by an inverse function performed by a digital processing unit.

Delay lines have been used in earlier patents to speed up slow video signals:- US5304854: Signal Transient Improvement Circuit;US3778543: Predictive-Retrospective Method of bandwidth improvement Shaping of pulses to improve conversion accuracy is used in Nuclear Physics (Trapeziodal shaping of pulses etc.) and also deconvolution of the sampled pulses is also performed.

(G.F.Knoll Radiation Detection and Measurement ISBN 047161761-X) Earlier patents require specialized techniques and processes and so are expensive, an object of this invention is to provide similar performance using common components without the need for expensive processes.

Summary of the Invention

According to the present invention there is provided an ADC preceded by signal processing elements which comprise of a delay line, with a plurality of taps from which signals are taken to amplifying and weighting elements which will provide the input to the ADC.

Hence fast signals input to the system are slowed prior to the ADC which means that the conversion will be performed with greater accuracy than if the fast signal was directly input to the ADC. 1.

The delay line method of slowing the signal is used in preference to a filter because this element of the circuit requires fine resolution which is best achieved using a delay line.

The digital output from the ADC output is input to a digital processing unit which reconstructs the input signal by performing the inverse algorithm to that of the input delay line and weighting system.

Description of the Drawings

Fig. I is a block diagram of the preferred embodiment of the high speed data acquisition system.

Fig. 2 shows a block diagram of the delay line and amplifier weighting Fig. 3 shows another embodiment of the device using a number of separate ADCs

Detailed Description of a Preferred Embodiment

Referring to Fig. 1., a preferred embodiment of a high speed data acquisition system according to the present invention includes a fixed delay element 3 preceded by a switch element 2, which connects the output of the delay element to the input. The delay element 3 is followed by a signal processing element which extends the ADCs' performance 5. This element is shown in more detail in fig. 2 and described in the next paragraph. This is followed by a digital processing element 6. The element 4, is a trigger control unit which adjusts the sampling time of the ADC 5 and also controls the operation of the switch The signal processing element shown in fig. 2 comprises of a plurality of delay elements 9 each preceded by a tap ofthe input to the element. Each tap is input to a summing amplifier 11, the relative weightings of each tap can be equal or different taps may be given different weightings in the sum. In the case where the taps are of equal weighting, as a signal travels down the delay line formed by each of the elements 9, a delayed version of the signal is presented to the summing amplifier and the output ofthe amplifier becomes a discrete integral of the signal as it appears in time along the delay line formed by elements 9. This integration will slow the signal down so that the ADC 5 will see a signal with much reduced slew rate than the input signal and will then be able to perform the conversion with greater accuracy.

This conversion will only provide information regarding the integral ofthe signal at that point in time and so another sample should be taken of the signal at a different time. This can be achieved for a repetitive sample by delaying the sample point from the trigger point, as is well known in the art. However for a transient signal this is not possible so the transient signal is captured in the delay element 3 shown in fig. I. and repeatedly presented to the signal processing element 5. The sample time of the ADC is adjusted by the trigger control unit 4 so that a number of samples of the integrated signal are taken and stored in memory elements within the digital processing unit 7.

The digital processing unit 7 is then able to perform the inverse function on the data samples it has received. In the case of a equal weighting on the tap elements fig. 2 -item 3 a differentiation is performed. Alternatively a known calibration pulse can be used to provide the time response of the system, the input signal would then be reconstructed by a convolution of the data samples and the calibrated system time response.

A further embodiment is shown in fig. 3 whereby a plurality of ADCs are used each sampling the input signal at incrementally delayed times so that the delay element 3 is not required.

Claims

Claims 1. A device for converting analogue electrical signals to a digital

representation comprising a method by which the input signal is delayed prior to conversion, a plurality of taps are taken from this delay path each of which are summed using analogue means and the respultant signal is presented to a standard Analogue to Digital Converter (ADC) which converts this signal to a digital representation, the data samples from the ADC are used by a digital processing machine to reconstruct the input signal prior to the delay line using an algorithm which is the inverse time response of the delay sub-system.
2. A device for converting high bandwidth signals in the analogue domain to the digital domain according to claim 1. in which a plurality of standard ADCs are used, the sample signal to each ADC is supplied at incrementally delayed times.