GB2401456A - Processor with delayed branch resolution - Google Patents

Processor with delayed branch resolution Download PDF

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Publication number
GB2401456A
GB2401456A GB0417085A GB0417085A GB2401456A GB 2401456 A GB2401456 A GB 2401456A GB 0417085 A GB0417085 A GB 0417085A GB 0417085 A GB0417085 A GB 0417085A GB 2401456 A GB2401456 A GB 2401456A
Authority
GB
United Kingdom
Prior art keywords
branch
instruction
processor
resteering
resolution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB0417085A
Other versions
GB2401456B (en
GB0417085D0 (en
Inventor
Sudarshan Kadambi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Publication of GB0417085D0 publication Critical patent/GB0417085D0/en
Publication of GB2401456A publication Critical patent/GB2401456A/en
Application granted granted Critical
Publication of GB2401456B publication Critical patent/GB2401456B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30058—Conditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address

Abstract

A processor (402) avoids or eliminates repetitive replay conditions and frequent instruction resteering through various techniques including resteering the fetch after the branch instruction retires, and delaying branch resolution. A processor (402) resolves conditional branches and avoids repetitive resteering by delaying branch resolution. The processor (402) has an instruction pipeline (916) with inserted delay in branch condition and replay control pathways. For example, an instruction sequence that includes a load instruction, followed by a subtract instruction then a conditional branch, delays branch resolution to allow time for analysis to determine whether the condition branch has resolved correctly. Eliminating incorrect branch resolutions prevents flushing of correctly predicted branches.

Description

GB 2401456 A continuation (74) Agent and/or Address for Service: W P
Thompson & Co Drury Lane, LONDON, WC2B 5SQ, United Kingdom
GB0417085A 2002-02-05 2003-02-04 Delaying a branch instruction allowing determination of correctness Expired - Fee Related GB2401456B (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US35546402P 2002-02-05 2002-02-05
US10/095,397 US7076640B2 (en) 2002-02-05 2002-03-11 Processor that eliminates mis-steering instruction fetch resulting from incorrect resolution of mis-speculated branch instructions
PCT/US2003/003187 WO2003067424A2 (en) 2002-02-05 2003-02-04 Processor with delayed branch resolution

Publications (3)

Publication Number Publication Date
GB0417085D0 GB0417085D0 (en) 2004-09-01
GB2401456A true GB2401456A (en) 2004-11-10
GB2401456B GB2401456B (en) 2006-07-26

Family

ID=27667890

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0417085A Expired - Fee Related GB2401456B (en) 2002-02-05 2003-02-04 Delaying a branch instruction allowing determination of correctness

Country Status (4)

Country Link
US (1) US7076640B2 (en)
AU (1) AU2003219704A1 (en)
GB (1) GB2401456B (en)
WO (1) WO2003067424A2 (en)

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US7653912B2 (en) * 2003-05-30 2010-01-26 Steven Frank Virtual processor methods and apparatus with unified event notification and consumer-producer memory operations
US7111153B2 (en) * 2003-09-30 2006-09-19 Intel Corporation Early data return indication mechanism
US7580914B2 (en) * 2003-12-24 2009-08-25 Intel Corporation Method and apparatus to improve execution of a stored program
US7254700B2 (en) * 2005-02-11 2007-08-07 International Business Machines Corporation Fencing off instruction buffer until re-circulation of rejected preceding and branch instructions to avoid mispredict flush
US7634644B2 (en) * 2006-03-13 2009-12-15 Sun Microsystems, Inc. Effective elimination of delay slot handling from a front section of a processor pipeline
US7647486B2 (en) 2006-05-02 2010-01-12 Atmel Corporation Method and system having instructions with different execution times in different modes, including a selected execution time different from default execution times in a first mode and a random execution time in a second mode
US7752350B2 (en) * 2007-02-23 2010-07-06 International Business Machines Corporation System and method for efficient implementation of software-managed cache
US7707398B2 (en) * 2007-11-13 2010-04-27 Applied Micro Circuits Corporation System and method for speculative global history prediction updating
US9342432B2 (en) 2011-04-04 2016-05-17 International Business Machines Corporation Hardware performance-monitoring facility usage after context swaps
US8868886B2 (en) 2011-04-04 2014-10-21 International Business Machines Corporation Task switch immunized performance monitoring
US20130055033A1 (en) 2011-08-22 2013-02-28 International Business Machines Corporation Hardware-assisted program trace collection with selectable call-signature capture
US9354886B2 (en) 2011-11-28 2016-05-31 Apple Inc. Maintaining the integrity of an execution return address stack
US9405545B2 (en) * 2011-12-30 2016-08-02 Intel Corporation Method and apparatus for cutting senior store latency using store prefetching
US9405544B2 (en) * 2013-05-14 2016-08-02 Apple Inc. Next fetch predictor return address stack
US9946549B2 (en) 2015-03-04 2018-04-17 Qualcomm Incorporated Register renaming in block-based instruction set architecture
US10296463B2 (en) 2016-01-07 2019-05-21 Samsung Electronics Co., Ltd. Instruction prefetcher dynamically controlled by readily available prefetcher accuracy
US10455045B2 (en) 2016-09-06 2019-10-22 Samsung Electronics Co., Ltd. Automatic data replica manager in distributed caching and data processing systems
US10467195B2 (en) 2016-09-06 2019-11-05 Samsung Electronics Co., Ltd. Adaptive caching replacement manager with dynamic updating granulates and partitions for shared flash-based storage system
US10747539B1 (en) 2016-11-14 2020-08-18 Apple Inc. Scan-on-fill next fetch target prediction
US10496647B2 (en) * 2017-04-18 2019-12-03 Microsoft Technology Licensing, Llc Delay detection in query processing
CN109101276B (en) * 2018-08-14 2020-05-05 阿里巴巴集团控股有限公司 Method for executing instruction in CPU
CN110007966A (en) * 2019-04-10 2019-07-12 龚伟峰 A method of it reducing memory and reads random ordering
US20220091852A1 (en) * 2020-09-22 2022-03-24 Intel Corporation Instruction Set Architecture and Microarchitecture for Early Pipeline Re-steering Using Load Address Prediction to Mitigate Branch Misprediction Penalties
US11928472B2 (en) 2020-09-26 2024-03-12 Intel Corporation Branch prefetch mechanisms for mitigating frontend branch resteers

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US5765037A (en) * 1985-10-31 1998-06-09 Biax Corporation System for executing instructions with delayed firing times
US6052775A (en) * 1997-06-25 2000-04-18 Sun Microsystems, Inc. Method for non-intrusive cache fills and handling of load misses
WO2002003200A2 (en) * 2000-06-30 2002-01-10 Intel Corporation Method and apparatus to replay transformed instructions

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US5765037A (en) * 1985-10-31 1998-06-09 Biax Corporation System for executing instructions with delayed firing times
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WO2002003200A2 (en) * 2000-06-30 2002-01-10 Intel Corporation Method and apparatus to replay transformed instructions

Also Published As

Publication number Publication date
WO2003067424A3 (en) 2004-02-26
US7076640B2 (en) 2006-07-11
AU2003219704A1 (en) 2003-09-02
US20030149865A1 (en) 2003-08-07
AU2003219704A8 (en) 2003-09-02
GB2401456B (en) 2006-07-26
WO2003067424A2 (en) 2003-08-14
GB0417085D0 (en) 2004-09-01

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20070204