GB2397694A

GB2397694A - Semiconductor device and method of manufacture

Info

Publication number: GB2397694A
Application number: GB0409387A
Authority: GB
Inventors: Nak-Jin Son; Ji-Young Kim
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2002-07-04
Filing date: 2003-07-03
Publication date: 2004-07-28
Anticipated expiration: 2023-07-03
Also published as: GB2397694B; GB0409386D0; GB2397693B; GB2397693A; GB0409387D0

Abstract

A semiconductor device prevents punch-through between the source and drain regions of a transistor and improves refresh operation of a memory cell. A trench (fig 6c: 208) is formed in the channel region between the source and drain regions in a semiconductor substrate, and a doped layer 210 for example epitaxial silicon fills up the trench. A gate insulation layer is formed over the doped layer and substrate, and a gate electrode is formed on the gate insulating layer. In alternative embodiments, a doped layer (fig 3: 112) is formed on the inner walls of a trench which is filled with semiconductor layer (114) and two gate electrodes (125) are formed so that the trench is between the gate electrodes, or two trenches are formed in the substrate, each filled with doped layers, and gate electrodes corresponding to each trench are formed upon a gate insulating layer (fig 7).

Description

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

BACKGROUND OF THE INVENTION

1. Field of the Invention

This disclosure relates to a semiconductor device and a method of manufacturing the same. More particularly, the disclosure relates to a semiconductor device capable of avoiding the "punchthrough" phenomenon between source and drain regions of a transistor, improving the refresh characteristics of a memory cell, and a method of manufacturing the same.

9. Description of the Related Art

FIG. 1 is a cross-sect!onal view of a conventional MOS transistor.

Refemng to FIG 1, the MOS transistor comprises a gate electrode 3 stacked on a semiconductor substrate 1 with a gate oxide layer 2 interposed between them, with source regions 4 and drain region 5 formed on the surface portions of the substrate 1 adjacent to either side of the gate electrode 3.

Carriers such as electrons or holes are supplied at the source region 4 and are removed at the drain region 5. The gate electrode 3 plays the role of forming a surface Inversion layer, he., a channel, extending between the source region 4 and the drain region 5 i When scahog Coven the MOS transistor as the integration level of semiconductor I devices increases, the reduction in the length of the gate electrode IS far more dramatic than the reduction of the operating voltage With the down scaling of the gate length, the influence of the source/drain upon the electric field or the potential in the channel region of the MOS transistor IS considerable. This Influence is known as the "short channel effect" and a lowering of the threshold voltage IS a typical result of this phenomenon. This IS because the channel region is greatly influenced by the depletion charge, the electric field, and the potential distnbuLon of the sourcefdran regions as well as the gate electrode In addition to a decreased threshold voltage, punchthnrough between the source and drain regions IS another severe problem accompanying the short channel effect In the hIOS transistor of FIG 1, the drain depletion layer 7 is widened in proportion to the Increase In the drain voltage, so that the dram depletion layer comes close to the source region 4 Thus, the dram depletion layer 7 and the source depletion layer 6 are completely corrected to each other when the length of the gate electrode 3 Is decreased. The electric field of the drain may eventually penetrate Into the source region 4 and thereby reduce the potential energy Lamer of the source junction. When this occurs, an Increased number of mayor camers in the source region 4 possess sufficient energy to overcome the Lamer Thus, a larger current flows from the source region 4 to the drain region 5. This effect is called the "punchthrough" phenomenon. When punchthrough occurs, the drain current Is not saturated but rapidly increases towards the sahrahon region In general MOS transistor technology, a threshold voltage (Via) adjustment is performed In order to secure the desired threshold voltage. The threshold adjustment is an Implant process. For example, a p-type 1mpunty such as boron (B) Is ion-mplanted in the NMOS transistor When the drain voltage is relatively small in the short- channel MOS transistor, the drain depletion layer Is not directly In contact with the source region. However, the surface of the substrate is depleted to some degree by the gate electrode, thereby varying the height of the potential Lamer near the source This is known as "surface punchthrough". The threshold adjustment process Increases the dopmg concentration of the interface between the substrate and the gate oxide layer, thereby suppressing surface punchthrough as well as adjusting the threshold voltage.

Accordingly, as down scaling of the gate length progresses, the threshold adjustment process Is performed at a high doping concentration to suppress the punchthrough Typtcal]y, the source and dram regions make contact with the heavily-doped threshold adjustment region because the impinges are applied to the entire surface of the substrate Thus, in the NMOS transistor, the e-type source and dram regions make contact with the p+ region (I e, threshold adjustment region) to apply the high electric field on the p-nunction, thereby mcreasng the junction leakage current In dynamic random access memory (DRAM) devices, In which a unit memory cell consists of one transistor and one capacitor cell, a "refresh" operation (I e, a data restoring operation for recharging the data charge) is necessary because the data charge of the capacitor decreases due to the leakage current over tense. Typically, the cell transistor is an NMOS transistor Therefore, the junction leakage current Increases due to the high electric field at the pen junction where the e-type source/dran retakes contact with the p region (I e, the threshold adjustment region) when a high dose threshold adjustment Implantation is performed. This results In the detenoraton of the refresh operation.

U. S Pat. No 5,963,811 discloses a method of forming a heavily doped antiI punchthrough region in the interface between the source and drain regions and the cell legion through an additional on-mplantation process after the threshold adjustment Is performed Methods of locally forming an ant-punchthrough region directly below the gate electrode are disclosed In U.S. Pat. Nos. 5,484,743, 5,489,543, and 6,985,061 However, In these methods, the ant-punchthrough region extends to the source and dram regions due to the profile of the lateral projection range (lop) caused by the on implantation Accordingly, a large electric field is applied to the region where the e-type source and drain regions and the p-type channel region make contact with each other, generating an increased unction leakage current and a deterioration of the refresh operation.

Furthermore, Japanese Patent Laid Open Publication No. 9-045904 discloses a method of forming a partition for preventing punchthrough below the channel region. The partition Is formed of an insulator or alternatively formed by filling the interior of the insulator with a conductor. In the case of using a partition composed of an Insulator, the current path of the depletion layer penetrates to the source side when the drain depletion layer meets the partition, thereby generating punchthrough. The method of forTnng the partition i by filling the intenor of the Insulator with a conductor can prevent this problem, but the required manufacturing process Is complicated.

According to a first aspect of the invention, there is provided a semiconductor device comprising a semiconductor substrate in which a trench is formed; a-doped layer formed at inner walls of the trench; a first semiconductor layer fillmg up the trench; a gate insulating layer formed on the first semiconductor layer and the substrate; two gate electrodes formed on the gate msulatng layer such that the trench is located between the gate electrodes; and first and second Impurity regions formed in the substrate on both sides of each of the two gate electrodes In another aspect, there Is provided a semiconductor device comprising a semiconductor substrate In which a trench is formed; a doped layer filling the trench, a gate Insulating layer formed on the doped layer and the substrate; a gate electrode formed on the gate msulatmg layer; and a source and a drain region formed In the substrate on respective sides of the gate electrode.

In another aspect, there is provided a semiconductor device comprising a serrucondtictor substrate In which two trenches are formed; a doped layer that fills the two trenches; a gate insulahng layer formed on the doped layer and the substrate; two gate electrodes corresponding to the two trenches formed on the gate insulating layer; a first impurity region formed m the substrate on a first side of each of the two gate electrodes, respectively; and a second impurity region formed In the substrate on a second side of each of the two gate electrodes, respectively.

The invention also relates to a method of manufacturing a semiconductor device comprising formmg a trench in an active region of a semiconductor substrate; forming a doped layer on an inner wall of the trench; filling the trench with a first semiconductor layer; forming a gate insulating layer on the first semiconductor layer and the substrate; forming two gate electrodes on the gate insulating layer such that the trench is located between the two gate electrodes; and forming a source and a drain region in the substrate on respective sides of each of the two gate electrodes.

In another aspect, there is provided a method of manufacturing a semiconductor device comprising forming a trench In a semiconductor substrate; filling the trench with a doped layer; formin g a gate insulating layer on the doped layer and the substrate; forming a gate electrode on the gate Insulating layer; and forming a source and a drain region in the substrate on both sides of the gate electrode.

The invention also relates to a method of manufacturing a semiconductor device comprising, forming two trenches in a semiconductor substrate; filling up each of the trenches with a doped layer, forming a gate insulating layer on the doped layer and the substrate; forming two gate electrodes on the gate Insulating layer corresponding to each of the trenches; and forrmng first and second impurity regions in the substrate on both sides of the two gate electrodes, respectively.

These devices aim to avoid ounch-through, while mprovmg the refresh operation Embodiments can Include all types of p- and e-type devices.

BRIEF DESCRIPTION OF THE DREGS

The above and other objects and advantages of the invention will become readily apparent by reference to the following detailed description when considered in conjunchon with the accompanying drawings wherein: FIG. 1 is a cross-sectional view of a conventional MOS transistor; FIG. 2 is a plane view showing a memory cell of a semiconductor device in : accordance with an embodiment of the invention FIG. 3 is a cross- sectional view of the memory cell of the semiconductor device, taken along the line A-A' of FIG 2.

FIGS 4A to 4F are cross-sectional views illustrating a method of manufacturing the memory cell of the semiconductor device as shown in FIG. 3.

FIG. 5 is a cross-sectional view pf a MOS transistor of a semiconductor device In accordance with another embodiment of the mventon.

FIGS. 6A to 6F are cross-sechonal views illustrating a method of manufacturing the - MOS transistor of the semiconductor device shown in FIG..

FIG 7 is a cross-sectional view of a memory cell of a semiconductor device In !, i-- . accordance with yet another embodiment of the invention FIGS. 8A to 8D are cross-sectional views illustrating a method of manufacturing the memory cell of the semiconductor device shown in FIG. 7.

DETAILED DESCRIPTION OF TtIE INVENTION

Hereinafter, embodiments of the invention will be described in detail with reference to the accompanying drawings. In the following drawings, the same numerals indicate the same elements.

FIG. 2 is a plane view showing a memory cell of a semiconductor device In accordance with an embodiment of the mvenhon. FIG. 3 is a cross-sectional view of the memory cell, taken along the line A-A' of the FIG 2 Referrmg to FIGS. and 3, a trench 110 Is formed in an active region 102 of a semiconductor substrate 100 divided n1to an isolation region 101 and the active region 102.

Preferably, the trench 110 Is fonned to have a width (w) wider than that of the active region 102. Although the isolation region 101 Is formed lo have a shallow trench isolation structure In the embodiment of FIG.3, the isolation region 101 may be formed to have a LOCOS-type structure without limiting the present invention.

A doped layer l l: for adjusting a threshold voltage and preventing punchthrough Is locally formed along the Inner wall of the trench 110. Preferably, the doped layer l 12 Is a

-

doped silicon epitaxal layer Alternately, the doped layer 112 may be formed via a delta- dopng process or an on-inplantation process.

A first semiconductor layer 114 is formed In the trench 110. Preferably, the first semiconductor layer 114 Is an undoped silicon epitaxal layer plananzed with the surface of the substrate 110.

A gate Insulating layer 118 Is formed on the first semiconductor layer 114 and the substrate 100 Preferably, the gate Insulating layer 118 Is formed on the hrst semiconductor layer 114 and the substrate with a second semiconductor layer 116 Interposed between them.

The second semiconductor layer 116 is a layer wherein a surface Inversion layer (he., - channel) is formed The second semiconductor layer 116 smooths the current flow between the source and drain regions of the semiconductor device. Preferably, the second semiconductor layer 116 is an undoped silicon epitaxial layer formed to have a thickness sufficient to prevent mpuntes In the doped layer 112 from penetrating the gate nsulahng layer 118.

TNVO gate electrodes 125 are fonned on the gate insulating layer 118 so that the trench Is located between the two gate electrodes 125. Preferably, each of the gate electrodes has a polycide structure consisting of an mpurity-doped polyslicon layer 120 and a metal secede 122 stacked thereon. Preferably, each of the gate electrodes 125 overlaps a portion of the trench 110 Gate cappmg layers 126 comprised of silicon nitride are formed on each of the gate electrodes 125. Gate spacers 132 comprised of silicon nitride are formed on the sidewalls of each of the gate electrodes 125.

A first impurity region (e.g., source regions) 128 and a second 1mpunty region (e.g. dram regions) 130 are formed In the substrate on both sides of each of the gate electrodes 195.

Between two gate electrodes 125 there Is formed one drain region 130. According to this embodiment, although the source region 198 and drain region 130 are formed In the surface portion of the second semiconductor layer 116 and the substrate 100 as shown in FIG 3, source region 198 and drain region 130 may be formed to have a depth shallower than the thickness of the second semiconductor layer 116 without hmtmg the scope of the Kenton.

:0 Furthermore, although not shown In FIG 3, a capacitor Is formed on the source region 198 and Is electrically connected to the source region 198 through a capacitor contact hole. A bit lme Is formed on the drain region 130 and is electrically connected to the drain region 130 through a bit One contact hole I) According to this embodiment, the heavily doped layer 1 12 on the Inner wall of the trench 110 is completely separated from source region 128 and drain region 130 of the transistor. Thus, the electric field of the P-N junction is weakened, reducing the junction leakage current and tmprovmg the refresh operation. Furthermore, punchthrough between the source region 128 and drain region 130 Is prevented due to the heavily doped layer 112.

FIGS 4A to 4F are cross-sectional views 11ustratmg a method of manufacturing the memory cell of the semiconductor device shown in FIG. 3 Referring to FIG 4A, through a thermal oxidation process, an oxide layer 104 with a thickness of about 6Q8O: Is formed on a semiconductor substrate 100. Upon the oxide - 10 layer 104 a nitride layer 106, such as Si3N4, is deposited to a thickness of about 150020004 by a low-pressure chemical vapor deposition (LPCVD) method. After coating the nitride layer 106 with a photoresist film, the film Is exposed and developed, forming a photoresist pattern 108 that defines where an active region of a memory cell will be located.

Referring to FIG. 4B, the nitride layer 106 and the oxide layer 104 are etched away using the photoresist pattern 108 as an etching mask.

- Successively, the exposed semiconductor substrate 100 is amsotropcally etched to a predetermined depth to fond a trench 110 in the active region of the memory cell. Preferably, the trench 110 has a width wider than that of the active region. Next, the photoresist pattern 108 is removed through ashng and stepping processes.

Referring to FIG. 4C, a heavily doped silicon layer 119 is formed on the Inner wall of trench 110. The doped silicon layer 112 Is grown by selective eptaxial growth usmg silicon atoms of the substrate 100 exposed In the trench 1 10 as seeds Alternately, as shown in FIG. 4D, the exposed firmer wail of the trench 1-10 Is doped with a p-type mpunty 111 by an ion-implantaton process or a delta-dopng process, thereby forming the heavily doped layer 112 on the Inner wall of the trench 110. Preferably, In the delta-dopng process, a gas contamng boron (B) Is applied m a plasma state to dope the mner wall of the trench 1 10 with a heavily doped p+ type mpunty The heavily doped layer 1 12 formed on the inner wall of trench 110 adjusts the threshold voltage (Vt) of the transistor and prevents punchthrough between the source and dram regions. In the convenhona1 method, the Vt adjust region and the anti-punchthrouh region are formed ndivdual]y through the threshold adjustment implant step and the ant- punchthrough implant step In this embodrnent, both the threshold adjustment and ant- purchthrough mp]ant are simultaneously achieved due to the heavily doped layer 112 formed by any one of the eptaxal growth' on-mplanta:on, or del, a-dopng processes. Here, À1 when the heavily doped layer 117 Is formed via an epitaxial growth process, the threshold voltage Is adjusted by optimizing the film thickness and the doping concentration.

Referrmg to FIG 4E, after forrnng the heavily doped layer 112 on the ironer wall of the trench l lO as described above, a first semiconductor layer 114 is formed so as to fill up the trench 110. Preferably, the first semiconductor layer 114 Is an undoped silicon eptaxial layer. In this case the deposition conditions are optimized such that the silicon eptaxial layer is selectively grown only on the substrate lOO Accordingly, the first semiconductor layer 114 is grown In an irregular shape because no silicon eptaxal layer is grown on the mtride layer 106 or the oxide layer 104. Deposition conditions are set up such that the lowest height - = 1 0 of the first semiconductor layer 11 Is higher than the surface of the substrate 1 00 (see "h" in FIG. 4E).

Referring to FIG. 4F, the first semiconductor layer 1 14 Is removed down to the level of the oxide layer 104 (FIG. 4E) by a chemical-mechanical polishing (CMP) process. Here, - the CMP process may be carried out until the first semiconductor layer 114 Is plananzed with ,. . the surface of the substrate 100, or it may be stopped when the first semiconductor layer 114 - protrudes somewhat from the surface of the substrate 100.

Next, the nitride layer 106 of FIG. 4E Is removed by a wet etchmg process using a nltude etchant such as phosphoric acid Tl1en, the oxide layer 104 Is removed by a wet etchmg process usmg an oxide etchant such as LAL ÀThereafter, as shown in FIG. 3, an undoped silicon layer is grown on the first semiconductor layer 114 and the substrate 100 via an epitaxial growth process, thereby forming a second semiconductor layer 1 16 The second semiconductor layer 116 Is a layer wherein a surface inversion layer (i.e., channel) is formed The second semiconductor layer l 16 functions to smooth the current flow. Preferably, the second semiconductor layer 116 has a thickness sufficient to prevent Impurities In the doped layer 112 from penetrating to the gate Insulating layer 1 1 S Next, an Isolation process such as a shallow trench Isolation (STI) is performed on the substrate 100, fon::n1g an Isolation layer 101 Specifically, a pad oxide layer, a nitride layer and a first CVD oxide layer are sequentially stacked on the substrate 100 The first CVD oxide layer and the mtode layer are patterned by a photohthography process to form a mask layer pattern Next, using the mask layer pattern as an etching mask, the substrate l OO Is etched to a predeten1lmed depth to thereby form an Isolation trench A second CVD-oxde layer, e.g. high density plasma oxide (HAP oxide) layer, Is deposited to a thickness sufficient to fill the Isolation trench Then, the second CVD-oxde layer Is removed dozen to the surface of the mtnde layer through an etch-baci; process or a CMP process. At thus time, the first CVD layer of the mask layer pattern is removed as well. The nitride layer and the pad oxide layer are sequentially removed by wet etching, thereby forming the shallow trench isolator region lOl.

Next, a gate msulatng layer 118 comprised of oxide, an mpurity-doped polysilcon layer 120, a metal secede layer 122 and a gate capping layer 126 comprised of nitride are sequentially formed on the isolation region lOl and the second semiconductor layer 116.

Through a photolithography process, the gate capping layer 126, the n1etal secede layer 122 and the polyslicon layer 120 are patterned to form gate electrodes 125 having a polycde 1 0 structure.

Through the entire surface of the substrate 100 on which the gate electrodes 125 are formed, impurities of low concentration (e.g., n- type mpunhes) are On-implanted to form hghtly doped source/dram regions 128 and 130 An insulating layer such as nitride is deposited on the entire surface of the resultant structure and anisotropically etched away to form gate spacers 132 on the sidewalls of the gate electrodes 125. Next, through an ion - - implantation process, heavily doped source and drain regions (not shown) of the NMOS transistor are formed on the peripheral circuit area, with the exception of the memory cell area. In the NMOS transistor of the memory cell area, it is more important to prevent current loss than increase the current drivability as deterrnned by the drain saturation current (Idsat) - 20, In the NMOS transistor of the peripheral circuit area, the current dnvablity is very important because it affects the entire performance of the chip. Accordingly, in order to simultaneously satisfy both requirements, the NMOS transistor of the memory cell area has a single e- type source/dram junction to minimize the J unction damage, while the NMOS transistor of the peripheral circuit area has a source/drain Junction of a lightly doped drain (LDD) or a double diffused drain (000) structure.

In the above-descubed first embodiment, the isolation region 101 is formed after the second semiconductor layer l 16 (where the charnel region of the cell transistor is formed).

However, it is obvious that the steps of FIGS 4A to 4F may also be performed after the isolation region 101 is fonned, for instance, after a conventional semiconductor manufacturing process completes the mitral step of forming isolation region 101.

Furthermore, In the case where trench isolation is apphed, the isolation trench and the trench that prevents punchthrough may be fonned at the same time.

FIG. 5 is a cross-sectonal view of a MOS transistor of a semiconductor device In accordance with another embodiment of the present nvento:1.

Referring to FIG. 5, a trench 208 is formed to a predetermined depth in a region of a semiconductor substrate 900 where a channel region of a transistor will be formed. The trench 208 is filled with a heavily doped layer 210. Preferably, the heavily doped layer 210 is À - a doped silicon eptaxial layer It is preferable that the heavily doped layer 210 is planarized with the surface of the substrate 200. lithe heavily doped layer 210 adjusts the threshold voltage of the transistor and prevents punchthrough.

A gate n1sulatmg layer 212, a gate electrode 214, and a gate capping layer 216 are sequentially formed on the doped layer 210 and the substrate 900 Gate spacers 220 are formed on the sidewalls of the gate electrode 214 and the gate capping layer 216.

Lightly doped source region 218 and drain region 219 (i.e., ADD regions) are formed in the substrate on both sides of the gate electrode 214. Heavily doped source region 222 and drain region 223 are formed in the substrate on both sides of the gate spacers 220.

Preferably, the trench 208 is formed so that the dimension of the trench 20S in the length direction of the gate electrode 214 (along the axis perpendicular to the plane of FIG. 5) is less than the length of the gate electrode 214. In order to enhance the anti-punchthrough - effect, the trench 208 has a depth greater than that of the heavily doped source/dran regions 222 and 223.

According to this embodiment, the heavily doped layer 210 is formed vertically in the channel region of the transistor, and thus, Is completely separated from the heavily doped - 20; source region 272 and drain region 223, thereby reducing the junction leakage current and preventing purchthrough.

FIGS. 6A to 6F are cross-sectional views illustrating a method of manufacturing the MOS transistor of the semiconductor device shown m FIG S. Referring to FIG. 6A, after sequentially forming an oxide layer 202 and a mask layer on a semiconductor substrate 200, the mask layer is patterned usmg a photolithography process to form mask layer patten1s 204 for opening a portion of a channel region of a transistor Preferably, the mask layer includes a material having an etching selectivity with respect to the oxide layer, e g, a Etude.

Referring to FIG 6B, a material having a similar etching rate to that of the material of the mask layer (e.g., ntnde) Is deposited on the entire surface of the substrate 200 incluUmg the mask layer patterns 004 It is then ansotropically etched to form spacers 906 on the sidewalls of the mask layer patterns 204 Refemng to FIG. 6C, using the mask layer patterns 204 and the spacers 206 as an etching mask, the substrate 900 Is amsotropcally etched to a predeterrnned depth, forming a 1,' trench 208. Preferably, the trench 208 Is formed such that the dimension of the trench 208 In the length direction of a gate electrode 214 in FIG. 5 (along the axis perpendicular FIG. 5) is less than the length of the gate electrode Furthermore, the trench 208 has a greater depth than that of the source and dram regions. For example, In a MOS transistor where the length of the gate electrode Is less than 1 00nm, the trench 208 has a width of about 20 30nm and a depth of about 0.2 pan.

Refemng to FIG. 6D, a doped silicon layer is grown by a selective eptaxal growth process using silicon atoms of the substrate 200 that are exposed through the trench 208 as seeds, thereby fonnng a heavily doped layer 210 filling the trench 208. For example, If the - 10 trench 208 has a width of about 2030nm and a depth of about 0.2 m, the doped silicon epitaxal layer has a thickness of about 20000 l.

The heavily doped layer 210 adjusts the threshold voltage (Vt) of the transistor and prevents punchthrough between the source and drain regions. In the convenhona1 method, the Vt adjust region and the anti- punchthrough region are formed Individually through the Vt adjust implantation and the anti-punchthrough implantation. In the present embodiment, the two effects of Vt adjustment and punchthrough prevention are simultaneously achieved due to the heavily doped layer 210 formed by a selective eptaxal growth process. Here, the threshold voltage is adjusted by optimizing the thickness and the doping concentration of the doped layer 210.

:- 20 - , Next, the doped layer 210 protruding from the substrate 200 Is removed through a chemical mechanical polishing (CMP) process, resulting in FIG. 6E. Altemately, this process may be omitted.

Subsequently, the mask layer patterns 204, the spacers 206, and the oxide layer 202 are sequentially removed, resulting in FIG. 6F Thereafter, as shown In FIG. 5, a gate msulatmg layer 212 ncludmg oxide, a gate electrode 214 and a gate capptnc' layer 216 are sequentially formed on the doped layer 210 and the substrate 200 On the entire surface of the substrate 200 on which the gate electrode 214 is formed, mpunties at a low concentration (e g., n- type mpuntes) are on-rnplanted to form lightly doped source region 218 and drain region 219 (I e., LDD regions).

:0 An insulating layer such as oxide or nitride Is deposited on the entire surface of the resultant structure and amsotropically etched away to formgate spacers 220 on the sidewalls of the gate electrode 21 Next, through an on-mplantaton process, heavily doped source region 222 and drain region 22: are formed in the substrate 200 on both sides of the gate spacers 220, thereby completing the MOS transistor.

FIG. 7 is a cross-sectiorial view of a memory cell of a semiconductor device In accordance with yet another embodiment of the present invention.

Referring to FIG. 7, two trenches 302 are formed In an active region of a semiconductor substrate 300 that is divided Into an active region and an isolation region 301.

Each of the trenches 302 Is located In a channel region of a transistor and Is Donned so that the dimension of the trench In the length direction of a gate electrode Is less than the length of the gate electrode.

As illustrated in FIG. 7, the isolation region 301 Is formed to have a shallow trench --. 10 Isolation structure in this embodiment. However, the isolation region 301 may also be formed to have a LOCOS-type (LOCal Oxidation of Silicon) structure without limiting the scope of the present invention.

Each of the trenches 302 Is filled with a heavily doped layer 304. Preferably, the heavily doped layer 304 Is a doped silicon eptaxial layer A gate insulating layer 306 is formed on the doped layer 304 and the substrate 300.

Two gate electrodes 312 are formed on the gate insulating layer 306 corresponding to each of the trenches 304. Preferably, each of the gate electrodes 312 Is formed to have a polycde structure consisting of an impurity doped polysilicon layer 308 and a metal slide layer 310 stacked thereon.

, . - 20 -- . Ntnde gate capping layers 314 are formed on each of the gate electrodes 312. Etude gate spacers 320 are formed on the sidewalls of each of the gate electrodes 312.

A hrst mpunty region (e.g., source region) 316 and a second impurity region (e.g., drain region) 318 are formed in the substrate 300 on both sides of each of the gate electrodes 312 Here, one drain region 318 is formed between two gate electrodes 312.

Furthermore, although not shown, a capacitor may be formed on the source region 316 to make electuca] contact with the source region 316 through a capacitor contact hole. A bit hoe Is formed on the drain region 318 to be electrically connected to the drain region 31 through a bit One contact hole.

According to the present mventon, the heavily doped layer 304 filling the trench 302 is formed vertically in the channel region of the transistor and Is completely separated from the source region 316 and drain region 318. Hence, the electric field of the PN junction is weakened, decreasing the junction leakage current and Improving the refresh Furthermore, punchthl-oucTh between the source regions 316 and dram region 31 g Is prevented due to the heavily doped layer 304 1 1 FIGS 8A to 8D are crosssechonal views Illustrating a method of manufacnlring the memory cell of the semiconductor device shown In FIG. 7.

- Refemng to FIG. SA, a semiconductor substrate 300 is subjected to an isolation process, thereby forming Isolation regions 301 Preferably, the Isolator process is a shallow trench Isolation (STI) process Specifically, a pad oxide layer (not shown), a nitride layer - (not shown) and a first CVD oxide layer (not shown) are sequentially stacked on the substrate 300 The first CVD oxide layer and the nitride layer are patterned via a photohthography process to form a mask layer pattern Next, using the mask layer pattern as an etching mask, the substrate 300 Is etched to a predetermined depth to forth Isolation trenches. A second - - 1 O CVD-oxde layer (e g, a high density plasma (HDP) oxide), is deposited to a thickness sufficient to fill the isolation trenches. Then, the second CVD-oxide layer is removed down to the surface of the nitride layer through an etch-back process or a CMP process At this time, the first CVD layer of the mask layer pattern Is removed as well The nitride layer and the pad oxide layer are sequentially removed by wet etching to form the shallow trench -15 isolation regions 301.

Next, after sequentially forrnng an oxide layer 330 and a mask layer on a semiconductor substrate 300 and the isolation regions 301, the mask layer Is patterned via a photolithography process to form mask layer patterns 332 for opening a portion of a channel region of a cell transistor. Preferably, the mask layer is comprised of a material having an I- . 20 etching selectivity with respect to the oxide layer (e.g., a nitride).

Refemng to FIG. 8B, a material having a sirrnlar etching rate to that of the material constituting the mask layer (e.g., nitride), Is deposited on the entire surface of the substrate 300 including the mask layer patterns 332 Then, it Is anisotropcally etched to-forTn spacers 334 on the sidewalls of the mask layer patterns 332.

Next, using the mask layer patterns 332 and the spacers 334 as an etching mask, the substrate 30015 ansotropcally etched to a predetermined depth to form trenches 302 In the channel regions of each of the transistors Preferably, the trench 302 has a width narrower than the length of a gate electrode and a depth greater than that of the source/dran regions.

For example, in the MOS transistor wherem the length of the gate electrode Is less than 100nm, the trench 302 Is formed to have a width of about 2030nTn and a depth of about 0.2 Em.

Refemng to FIG. 8C, a doped silicon layer Is grown by a selective eptaxal growth process using silicon atoms of the substrate 300 exposed through the trenches 302 as seeds, thereby forrnng heavily doped layers 304 filling the trenches 302. For example, If the trench -; 302 has a width of about 2030nm and a depth of about 0.: Ilm, the doped silicon epitaxial layer is formed to have a thickness of about 2003005 Next, the doped layer 304 protruding from the substrate 300is removed through a chemical-mechanical polishing (CMP) process. Alternately, this process rrtay be orntted.

Next, the mast; layer patterns 332 and the spacers 334 are removed by wet etching process using a nitride etchant such as phosphoric acid, resulting In FIG. 8C After removing the oxide layer 330 by a wet etching process using an oxide etchant, an oxide gate insulating layer 306 Is formed on the doped layers 304 and the substrate 300 through a thermal oxidation process.

À 10- Thereafter, as shown in FIG 7, an mpurity-doped polyshcon layer 308, a metal slide layer 310 and a gate capping layer 314 composed of nitride are sequentially formed on the gate nsulahog layer 306. Through a photobthog.raphy process, the gate capping layer 3 14, the metal secede layer 310 and the polysilcon layer 308 are patterned to form gate electrodes 312 with a polycide structure.

Irnpuntes at a low concentration (e g., e-type impurities) are ionmplanted on the entire surface of the substrate 300 on which the gate electrodes 312 are formed, thereby forming lightly doped source regions 316 and drain region 318. Next, an insulating layer such as nitride is deposited on the entire surface of the resultant structure and anisotropically etched to form gate spacers 320 on the sdevalls of the gate electrode 3 l 2. Through an ion implantation process, heavily doped source and drain regions (not shown) of the NMOS transistor are formed in the peripheral circuit area but not in the memory cell area.

Accordmg to the embodiment as described above, the heavily doped layer Is locally formed on the inner wall of the trench located in an active region between two gate electrodes Altematvely, the trench contanmg the heavily doped layer Is formed directly below the channel region.

The heavily doped layer optimizes the doping concentration of the channel region to adjust the threshold voltage It also reduces the tendency of the deletion layer to widen m the channel region, thereby increasing the punchthrough voltage Furthermore, since the heavily doped layer Is locally foiled In the trench, the source regions and drain region are completely separated from the heavily doped layer, thereby weakening the electric field of the Injunction Accordingly, the source/dranunction capacitance Is reduced and the junction leakage current Is decreased, thereby Improving the refresh operation.

To reiterate, embodiments of the Invention provide a semiconductor device that prevents punchtlrough between the source and draw regions of a transistor while,mprovng the refresh operation of a memory cell Embodiments of the invention also provide a method of manufactunog such a semiconductor device.

Some embodiments of the invention Include a semiconductor substrate in which a trench is formed; a doped layer fonned at the inner walls of the trench; a first semiconductor layer filling up the trench, a gate Insulating layer formed on the hrst semiconductor layer and s the substrate; two gate electrodes formed on the gate insulating layer such that the trench Is located In between two gate electrodes, and first and second impurity regions formed In the substrate or: both sides of each of the gate electrodes.

According to preferred embodiments of the Invention, the doped layer includes a doped silicon eptaxial layer. Altematvely, the doped layer may be formed via a delta doping process or an ion-implantaton process.

Other embodiments of the invention Include a semiconductor substrate in which a trench is formed; a doped layer filling up the trench, a gate insulating layer formed on the doped layer and the substrate; a gate electrode formed on the gate nsulatmg layer; and source - 15 and drain regions formed In the substrate on both sides of the gate electrode.

- In a preferred embodiments, the trench is located in a channel region between the source region and the drain region. The doped layer includes a doped silicon eptaxlal layer.

Still other embodiments of the Invention include a semiconductor substrate In which two trenches are formed; doped layers filling up each of the trenches; a gate Insulating layer formed on the doped layers and the substrate; two gate electrodes formed on the gate insulating layer so as to correspond to each of the trenches; and first and second mpunty regions formed in the substrate on both sides of each of the gate electrodes Other embodiments of the mventon provide a method of manufacturing a semiconductor device that Include the processes of forrnng a trench a the semiconductor substrate, foxing a doped layer on the inner wall of the trench; filling the trench with a first semiconductor layer, forming a gate Insulating layer on the first semiconductor layer and the substrate, forrmng two gate electrodes on the gate Insulating layer such that the trench Is located m between two gate electrodes, and forming source/drain regions In the substrate on both sides of each of the gate electrodes.

Still another embodiment of the Invention provides a method of manufacturing a semiconductor device that Includes the processes of forming a trench In a serfuconductor substrate, filling the trench with a doped layer, forming a gate insulating layer on the doped layer and the substrate; forrnng a gate electrode on the gate Insulating layer, and forrnng source and drain regions In the substrate on both sides of the gate electrode j Yet another embodiment of the invention provides a method of manufacturing a semiconductor device that includes the processes of forming two trenches In a semiconductor substrate; filling each of the trenches with doped layers, forming a gate nsulatmg layer on - the doped layers and the substrate; forming No gate electrodes on the gate insulating layer so as to correspond to each of the trenches; and forming first and second impurity regions in the substrate on both sides of the gate electrode Accordmg to some embodiments of the the invention, the heavily doped layer is locally formed on the inner wall of the trench formed m an active region between two gate electrodes. Alternately, the trench filled with the heavily doped layer Is formed directly below the channel region. It Is preferred that the doped layer is formed by epitaxial growth so as to be locally formed directly below the channel region without lateral extension.

The heavily doped layer plays a role of optimizing the doping concentration of the channel region to adjust the threshold voltage. It also reduces the widening of the depletion layer in the channel region, thereby increasing the punchthrough voltage. Furthermore, since the heavily doped layer is locally formed In the trench, the source and drain regions are - completely separated from the heavily doped layer, thereby weakening the electric field of the P-N junction. Accordingly, the source-drain junction capacitance is reduced and the junction leakage current is decreased, improving the refresh operation. Embodiments of the mvenhon can be apphed to all types of NMOS devices and PMOS devices.

- 20 Although multiple embodiments of the invention have been described, it is understood that the invention should not be limited to only these described embodiments. Vanous changes and modificahons may be made by one of ordinary skill In the art, yet still fall within the scope of the invention -as hereinafter claimed I,

Claims

CLAIMS: l. A semiconductor device comprising: a semiconductor substrate in

which a trench is formed; a doped layer filling the trench; a gate insulating layer formed on the doped layer and the substrate; a gate electrode formed on the gate insulating layer; and a source and a drain region formed in the substrate on respective sides of the gate electrode.
2. The semiconductor device as claimed in claim 1, wherein the trench is formed in a channel region between the source region and the drain region.
3. The semiconductor device as claimed in claim 1, wherein the doped layer is planarized with the surface of the substrate.
4. The semiconductor device as claimed in claim 1, wherein the doped layer comprises a doped silicon epitaxial layer.
5. A method of manufacturing a semiconductor device comprising: fonnng a trench m a semiconductor substrate; filling the trench with a doped layer; forming a gate insulating layer on the doped layer and the substrate; forming a gate electrode on the gate insulating layer; and forming a source and a drain region in the substrate on both sides of the gate electrode.
6 The method as claimed m claim 5, wherein forming a trench comprises fonning a trench in a chapel region between the source region and the drain region.
7. The method as claimed in claim 5 or 6, wherein forming a trench compn ses: fomlmg a mask layer pattern on the semiconductor substrate; fanning spacers on the sidewalls of the mask layer pattern; and etching the substrate by using the mask layer pattern and the spacers as an etching mask.
8. The method as claimed in claim 7, further comprising removing the mask layer pattern and the spacers after filling the trench.
9. The method as claimed in claim 5, 6, 7 or 8, further comprising planarizng the doped layer with the surface of the substrate after filling the trench.
10. The method as claimed in claim 5, 6, 7, 8 or 9, wherein the doped layer comprises a doped silicon epitaxial layer.