GB2395824B - Object addressed memory hierarchy - Google Patents
Object addressed memory hierarchyInfo
- Publication number
- GB2395824B GB2395824B GB0403483A GB0403483A GB2395824B GB 2395824 B GB2395824 B GB 2395824B GB 0403483 A GB0403483 A GB 0403483A GB 0403483 A GB0403483 A GB 0403483A GB 2395824 B GB2395824 B GB 2395824B
- Authority
- GB
- United Kingdom
- Prior art keywords
- memory hierarchy
- addressed memory
- object addressed
- hierarchy
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
- G06F12/1063—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently virtually addressed
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/072,169 US6859868B2 (en) | 2002-02-07 | 2002-02-07 | Object addressed memory hierarchy |
GB0301150A GB2387939B (en) | 2002-02-07 | 2003-01-17 | Object addressed memory hierarchy |
Publications (3)
Publication Number | Publication Date |
---|---|
GB0403483D0 GB0403483D0 (en) | 2004-03-24 |
GB2395824A GB2395824A (en) | 2004-06-02 |
GB2395824B true GB2395824B (en) | 2004-08-25 |
Family
ID=32232406
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB0403483A Expired - Lifetime GB2395824B (en) | 2002-02-07 | 2003-01-17 | Object addressed memory hierarchy |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB2395824B (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4731740A (en) * | 1984-06-30 | 1988-03-15 | Kabushiki Kaisha Toshiba | Translation lookaside buffer control system in computer or virtual memory control scheme |
US5317704A (en) * | 1989-07-18 | 1994-05-31 | Hitachi, Ltd. | Storage relocating method and hierarchy storage system utilizing a cache memory |
-
2003
- 2003-01-17 GB GB0403483A patent/GB2395824B/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4731740A (en) * | 1984-06-30 | 1988-03-15 | Kabushiki Kaisha Toshiba | Translation lookaside buffer control system in computer or virtual memory control scheme |
US5317704A (en) * | 1989-07-18 | 1994-05-31 | Hitachi, Ltd. | Storage relocating method and hierarchy storage system utilizing a cache memory |
Also Published As
Publication number | Publication date |
---|---|
GB2395824A (en) | 2004-06-02 |
GB0403483D0 (en) | 2004-03-24 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PE20 | Patent expired after termination of 20 years |
Expiry date: 20230116 |