GB2395325B - System to reduce skew in clock signal distribution using balanced wire widths - Google Patents

System to reduce skew in clock signal distribution using balanced wire widths

Info

Publication number
GB2395325B
GB2395325B GB0403622A GB0403622A GB2395325B GB 2395325 B GB2395325 B GB 2395325B GB 0403622 A GB0403622 A GB 0403622A GB 0403622 A GB0403622 A GB 0403622A GB 2395325 B GB2395325 B GB 2395325B
Authority
GB
United Kingdom
Prior art keywords
clock signal
signal distribution
wire widths
reduce skew
balanced wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
GB0403622A
Other versions
GB0403622D0 (en
GB2395325A (en
Inventor
Gerard M Blair
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/507,508 external-priority patent/US6654712B1/en
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of GB0403622D0 publication Critical patent/GB0403622D0/en
Publication of GB2395325A publication Critical patent/GB2395325A/en
Application granted granted Critical
Publication of GB2395325B publication Critical patent/GB2395325B/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
GB0403622A 2000-02-18 2001-01-31 System to reduce skew in clock signal distribution using balanced wire widths Expired - Lifetime GB2395325B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/507,508 US6654712B1 (en) 2000-02-18 2000-02-18 Method to reduce skew in clock signal distribution using balanced wire widths
GB0102443A GB2365178B (en) 2000-02-18 2001-01-31 Method to reduce skew in clock signal distribution using balanced wire widths

Publications (3)

Publication Number Publication Date
GB0403622D0 GB0403622D0 (en) 2004-03-24
GB2395325A GB2395325A (en) 2004-05-19
GB2395325B true GB2395325B (en) 2004-07-28

Family

ID=32178855

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0403622A Expired - Lifetime GB2395325B (en) 2000-02-18 2001-01-31 System to reduce skew in clock signal distribution using balanced wire widths

Country Status (1)

Country Link
GB (1) GB2395325B (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0794590A (en) * 1993-09-22 1995-04-07 Toshiba Corp Automatic wiring method for integrated circuit
US5845233A (en) * 1997-07-30 1998-12-01 Lucent Technologies, Inc. Method and apparatus for calibrating static timing analyzer to path delay measurements
JP2000163460A (en) * 1998-11-30 2000-06-16 Matsushita Electric Ind Co Ltd Method for verifying reliability of semiconductor integrated circuit device and method for arrangement and wiring thereof
JP2001084282A (en) * 1999-09-13 2001-03-30 Matsushita Electric Ind Co Ltd Automatic arranging/wiring system

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0794590A (en) * 1993-09-22 1995-04-07 Toshiba Corp Automatic wiring method for integrated circuit
US5845233A (en) * 1997-07-30 1998-12-01 Lucent Technologies, Inc. Method and apparatus for calibrating static timing analyzer to path delay measurements
JP2000163460A (en) * 1998-11-30 2000-06-16 Matsushita Electric Ind Co Ltd Method for verifying reliability of semiconductor integrated circuit device and method for arrangement and wiring thereof
JP2001084282A (en) * 1999-09-13 2001-03-30 Matsushita Electric Ind Co Ltd Automatic arranging/wiring system

Also Published As

Publication number Publication date
GB0403622D0 (en) 2004-03-24
GB2395325A (en) 2004-05-19

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Legal Events

Date Code Title Description
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)

Free format text: REGISTERED BETWEEN 20110203 AND 20110209

PE20 Patent expired after termination of 20 years

Expiry date: 20210130