GB2394868A

GB2394868A - Efficient synchronisation channel encoding in UTRA TDD mode using codeword generator matrix

Info

Publication number: GB2394868A
Application number: GB0225497A
Authority: GB
Inventors: Alan Edward Jones; Paul Howard
Original assignee: IPWireless Inc
Current assignee: IPWireless Inc
Priority date: 2002-11-01
Filing date: 2002-11-01
Publication date: 2004-05-05
Anticipated expiration: 2022-11-01
Also published as: GB0225497D0; GB2394868B

Abstract

An encoder and method for efficient synchronisation channel encoding in UTRA TDD mode by: producing a codeword a , where a =dG + z modulo-2, where d represents a predetermined code group to be encoded, G represents a predetermined generator matrix, and z represents a function of the code group number and a row of the generator matrix; producing values sk=2 a 2k+1+ a 2k;k=0,1,2, and associated values b1,b2,b3; and producing a value SSSC associated with the code group, where SSSC=(b1c f (0),b2c f (1),b3c f (2)), c f represents a code within the code group, and b1,b2,b3 e (Ò1,Òj). This provides an efficient encoding architecture with reduced memory requirements for the synchronisation channel in UTRA TDD mode; and, in addition, by simple manipulation of the generation matrix, a higher chip rate signal may be signalled whilst still preserving the signalling information for the lower chip rate.

Description

ENCODER AND METHOD FOR EFFICIENT SYNCHRONISATION CHANNEL

ENCODING IN UTRA TDD MODE

5 Field of the Invention

This invention relates to wireless communication networks and particularly to UTRA (Universal Mobile Telephone System Terrestrial _adio Access) networks operating in 10 TDD (Time Division Duplex) mode.

Background of the Invention

15 In UTRA TDD mode the synchronization channel (SCM) has two functions. The primary function is to provide a signal that enables a 'UK' (user equipment, such as a wireless terminal) to search for and identify a 'Node B' (i.e., a wireless Base Station of a UMTS system). The 20 secondary function is to provide sufficient information to allow a UE to demodulate a P-CCPCH (Primary Common Control Physical CHannel) transmission and obtain the_ system information, sent on the BCH (Broadcast CHannel) transport channel which is carried by the P-CCPCH, needed 25 in order to be able to communicate with the network.

There are two cases of SCH and P-CCPCH allocation as follows: Case l) SCH and P-CCPCH allocated in timeslot #k, 30 where k=0 14

À À À

À À.. ..

:: À B:.e r À Case 2) SCH allocated in two timeslots: timeslot #k and timeslot #k+8, where k=06; P-CCPCH allocated in timeslot #k where timeslot #k is the kth timeslot. Due to this SCH 5 scheme, the position of P-CCPCH is known from the SCH.

The SCH consists of one real-valued primary synchronization code (PSC) and three complex secondary synchronization codes (SSCs), all of length 256 chips.

The PSC is common for all Node Bs, but the SSCs are Node 10 B specific. The PSC and SSC are transmitted simultaneously from a given Node B at a specific fixed time offset (tosser) from the start of time slot k. The time offset is included to prevent the possible capture effect that would otherwise occur as a consequence of all Node 15 Bs transmitting the common primary code at the same time.

Considering a network where multi-chip rates are supported, in an initial start-up condition, the UE will not be aware of the chip rate that is available. To cope 20 with this situation, it is known for the SCH to be always transmitted at a fixed chip rate (e.g., 3.84Mcps), and for the chip rate being used in the cell by the other transport channels to be signalled to the UEs by using the secondary synchronization code, SSC (by modulating 25 the secondary sequences).

Heretofore, this has been done by storing code group and frame position information defining the codes in tables in memory in the network and UK. However, the amount of 30 information needing to be stored in this way may be considerable.

À À À ::: À: :.'

- - A need therefore exists for efficient synchronization channel encoding in UTRA TDD mode wherein the abovementioned disadvantage(s) may be alleviated.

Statement of Invention

In accordance with a first aspect of the present 10 invention there is provided a method for efficient synchronization channel encoding in UTRA TDD mode as claimed in claim 1.

In accordance with a second aspect of the present 15 invention there is provided a method for efficient synchronization channel encoding in UTRA TDD mode as claimed in claim 6.

In accordance with a third aspect of the present 20 invention there is provided an encoder for efficient synchronization channel encoding in UTRA TDD mode as claimed in claim 12.

In accordance with a fourth aspect of the present 25 invention there is provided an encoder for efficient synchronization channel encoding in UTRA TDD mode as claimed in claim 17.

ct.; ':,. ee. ''.

:: À Brief Description of the Drawings

One encoder and method for efficient synchronization channel encoding in UTRA TDD mode incorporating the 5 present invention will now be described, by way of example only, with reference to the accompanying drawings, in which: FIG. l shows in schematic form the format of SCH in 10 UTRA TDD mode; FIG. 2 shows in tabular form code allocation for CASE l; 15 FIG. 3 shows in tabular form code allocation for CASE 2; and FIG. 4 shows in block schematic form an encoder incorporating the invention.

Description of Preferred Embodiment(s)

The general format of the SCH is shown schematically in 25 FIG. 1. As shown, the primary synchronization code (PSC), Cp, is a real-valued sequence of length 256 chips, transmitted at power PpSc. The secondary synchronization code (SSC), Cst, (i = 1, 2,3), of length 256 is transmitted simultaneously with the PSC; the total power of the SSC

ee.:.: F:.e.e ::; is set to PSSC. In addition these codes are multiplied by a complex value, by = 1, 2, 3). The subscript s in Car refers to a code set, of which there 32, as specified in the technical specification '3GPP TS 25.223' publicly

5 available on the website (www.3gpp.org) of the 3rd Generation Partnership Project. The code sets, s, in conjunction with the complex multiplier values, by, are used to transfer the information bits to the UK.

10 The location of the SCH relative to the beginning of the time slot is defined by tose''n. It is calculated as follows: n T L976 - 2s64 n < l 6 (976 + 512 + (n-1 6t 5])Tc n 2 16 which can be simplified to: n.48.Tc n < 16 Àsetn](720+ n.48)T n 2 16 20 where Tc is the chip duration and n = 0, 1,..., 31. The value of n is related to the code group and is obtained by demodulating the information on the SSC.

Encoding Informa Lion on SSC The three codes that make up the SSC are QPSK (Quadrature _hase Shift Key) modulated and transmitted in parallel_

À À with the PSC. The QPSK modulation carries the following information: À the code group that the base station belongs to (32 code groups: 5 bits; Cases 1, 2); 5 À the position of the frame within an interleaving period of 20 msec (2 frames: 1 bit, Cases 1, 2); À the position of the SCH slot(s) within the frame (2 SCH slots: 1 bit, Case 2).

10 The SSCs are partitioned into two code sets for Case 1 and four code sets for Case 2. The set is used to provide the following information: Code Set | Code Group | 1 0-15

2 16-31

Code Set Allocation for CASE 1 The code group and frame position information is provided by modulating the secondary codes in the code set.

Code Set Code Group 1 0-7 8-15 16-23 4 24-31

Code Set Allocation for CASE 2 The following SCH codes are allocated for each code set: Case 1 Code set 1: C1, C3, Cs.

Code set 2: ClO, C13, C14.

: -

. B:; - 7 Case 2 Code set 1: C1, C3, C5, Code set 2: C1O, C13, C14.

Code set 3: CO, C6, C12.

5 Code set 4: C4, C8' C15 Code allocation for CASE 1 FIG. 2 shows a table illustrating code allocation for 10 CASE 1.

It may be noted that the code construction for code groups O to 15 using only the SCH codes from code set 1 is shown. It will be understood that the construction 15 for code groups 16 to 31 using the SCH codes from code set 2 is done in the same way.

Code allocation for CASE 2 20 FIG. 3 shows a table illustrating code allocation for CASE 2.

It may be noted that the code construction for code groups O to 15 using the SCH codes from code sets 1 and 2 25 is shown. The construction for code groups 16 to 31 using the SCH codes from code sets 3 and 4 is done in the same way.

It will be understood that the conventional approach is 30 to store the information defined in the tables of FIG. 2 and FIG. 3 in memory in the network and UK. It will be

- . t. F..

À 8 appreciated that, using this conventional approach, the amount of information needing to be stored may be considerable. 5 A novel procedure, which simplifies the above mapping process, is now presented.

Efficient Encoder for CASE 1 10 For ease of explanation, the following notation is introduced. If C =(c(O),c(l),c(2)) represents the permutation of the codes in the code set, where is the permutation, then the SSC associated with a code group is given by the component-wise product 15 SS. C = hC where Sss. =(bc(o)'b2c()'b3c(2)) and b,b2,b3 (_1_j) Let u=(uO,u,u2, u3,u4) be the binary representation of the code group number, and define the following generator 20 matrix O O O O 0 1

G'= 0 0 0 1 0 0

0 1 0 0 0 0

1 0 1 0 0 0

with rows labelled gO,g,g2,g3. We define a binary codeword as a=dC'+z modulo-2 25 where d = (if Quorum u2)

: - À t 1 1 9 - Jo Frame 1 f l 1 Frame 2 and Z = U3(U2 +l)g3 reduced modulo-2. We map the elements of the codeword, a pairwise to the set of integers (0,1,2,3) using the expression Sk 2a2k+, + a2k; k=0,1,2 where the sequence 5 = (505952) has an associated complex sequence b=(jS(}, jet, j'2). The choice of code set and permutation is given by (U4 U3 U2) Code Code Set Group Permutation 000 0-3 CIC3C5..DTD: 001 4-7 CIC3C5

010 8-11 CC5C3

011 12-15 C3C5C]

100 16-19 CloCI3Ci4 101 20-23 CloCI3CI4 110 24-27 CloCI4Cl3 111 2831 CI3CI4Clo Table 1

Efficient Encoder for CASE 2 Define the following generator matrix O O O O 0 1

G2- 0 1 0 1 0 0

_ O O 0 1 0 0

1 0 1 0 0 0

15 with rows labelled gO2,g2,g22,g32. We define a binary codeword as a =dG2+z modulo-2

l - -

: - -

where d=(K'f'Uoul)T/ O slot k K= 1 slotk+1 and z=u2(u+l)g2 reduced modulo2. The process follows in identical manner to case 1 with the exception that the 5 permutation and code set map is changed to represent case 2, as shown below.

(U4, U3, U2, U') Code Code Set Group Permutation 0000 0-1 C,C3C5

0001 23 CIC3C5

0010 4-5 CIC5C3

0011 6-7 C3C5C!

0100 8-9 CloCI3CI4 0101 10-11 CloCl3CI4 0110 12-13 CloCI4CI3 0111 14CI3CI4Clo 1000 16-17 cOc6c,2 1001 18-19 cOc6c'2 1010 20-21 cOc2c6 1011 22-23 c6cl2cO 1100 24-25 C4C8C5

1101 26-27 C4C8C'5

1110 2829 C4C'5C8

1111 3031 C8C'5C4

Table 2

Thus, it will be understood that only the data in the 10 above tables 1 and 2 needs to be stored in memory, in order to allow the necessary secondary synchronization channel encoding to be effected, following the encoding

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process described above, rather than having to store the data in tables of FIG. 2 and FIG. 3 as in the prior art.

An efficient encoder 400 for carrying out the above 5 processes for CASE 1 and CASE 2 is shown generally in FIG. 4. As can be seen in this figure, in block step 410 the binary codewords a=dG +z modulo-2 are calculated.

Next, in block 420, the expressions sk=2a2k++a2k;k=0,1,2 are calculated. Finally, in block 430, the secondary 10 synchronization codes S,s=(bc(o) 'b2c()'b3c(2)) are calculated Signalling Higher Chip Rate 15 As will be explained below, modification of the generator matrix, allows encoding of the chip rate used in the cell. Let Cr denote the chip rate, where 20 C i0 3.84Mcps r t1 7.68Mcps We have the following: CASE 1:

25 Define the following generator matrix O O O 0 1 0

O O O O 0 1

G'= O O O I O O

0 1 0 0 0 0

1 0 1 0 0 0

t;'t; te " tet and a binary codeword as a=dG'+z modulo-2 where d=(Crfuou, u2) and z=u3(u2+l)g4. We note that when Cr is O the codeword produced by the generator matrix is 5 unchanged. When Cr is 1, denoting the higher chip rate, the third element of the sequence b = (jet j9l, ji2) becomes imaginary rather than real.

GASE 2:

10 Define the following generator matrix O O O 0 1 0

O O O O 0 1

G2= 0 1 0 1 0 0

O O 0 1 0 0

1 0 1 0 0 0

and a binary codeword as a=dG2+z modulo-2 where d=(C,,K,f,uo,u) and z=u2(u+l)g42. We note that when 15 Cr is O the codeword produced by the generator matrix is unchanged. When Cr is 1, denoting the higher chip rate, the third element of the sequence b = (js,,, j9,, j92) becomes imaginary rather than real.

20 It will be appreciated that the process for encoding described above will typically be carried out in software running on a processor (not shown), and that the software may be provided as a computer program element carried on any suitable data carrier (not shown) such as a magnetic 25 or optical computer disc.

:e le 's:: I: It will be appreciated that the encoder described above will typically be incorporated in a base station ('Node B' - not shown) and a mobile station ('UE' - not shown) 5 of a UMTS system.

It will be understood that the encoder and method for efficient synchronization channel encoding in UTRA TDD mode described above provides the following advantages: 10 À an efficient encoding architecture for the synchronization channel in UTRA TDD mode À in addition, by simple manipulation of the generation matrix, a higher chip rate signal may be signalled whilst still preserving the signalling 15 information for the lower chip rate.

Claims

À :: Claims

1. A method for efficient synchronization channel encoding in UTRA TDD mode, comprising: 5 producing a codeword a, where a= dig + z modulo-2, where d represents a predetermined code group to be encoded, G represents a predetermined generator matrix, and z represents a function of the code group number and a row of the 10 generator matrix, producing valuessk=2a2k++a2k,k=0,1,2, and associated values b,b2,b3, and producing a value Sysc associated with the code group, where Sysc=(bc(o),b2c(), b3c(2)), car represents 15 a code within the code group, and b,b2,b3 (_1, _j).

2. The method of claim 1, wherein the generator matrix in a first case is substantially equal to -O O O O 0 1

O O 0 1 0 0

0 1 0 0 0 0

1 0 1 0 0 0.

3. The method of claim 1 or 2, wherein the generator matrix in a second case is substantially equal to O O O O 0 1-

0 1 0 1 0 0

O O 0 1 0 0

1 0 1 0 0 0.

4. The method of claim 1, 2 or 3 wherein in a first case: d comprises (f, uo,u,u2), where f is 0 for a first 5 frame and 1 for a second frame, uO,u, u2 represent bits from a binary representation of the code group number, and Z=U3(U2 +I)g3 reduced modulo-2, where g3 represents a row of the generator matrix.

5. The method of claim 1, 2, 3 or 4 wherein in a second case: d comprises (K,f,uo,u'), where K is O for a kth slot and 1 for a (k+1)th slot, f is 0 for a 15 first frame and 1 for a second frame, uO,u,u2 represent bits from a binary representation of the code group number, and Z=U2(U'+I)g3 reduced modulo-2, where g3 represents a row of the generator matrix.

# #

r q; 1 1 - 16 6. A method for efficient synchronization channel encoding in UTRA TDD mode, comprising: producing a codeword from a predetermined code group to be encoded, a predetermined generator 5 matrix G. and a function of the code group number and a row of the generator matrix, and producing a value Sssc associated with the code group' where Sssc = (bc(o) 'b2c()'b3c(2)) car represents a code within the code group, and b',b2,b3 e(+l,+j), 10 wherein the generator matrix has values such that a parameter produced therefrom changes between a first value indicating a first chip rate and a second number indicating a second chip rate.

15 7. The method of claim 6, wherein the generator matrix in a first case is substantially equal to -O O O 0 1 O-

O O O O 0 1

O O 0 1 0 0

0 1 0 0 0 0

1 0 1 0 0 0.

8. The method of claim 6 or 7, wherein the generator 20 matrix in a second case is substantially equal to O O O 0 1 0

O O O O 0 1

0 1 0 1 0 0

O O 0 1 0 0

1 0 1 0 0 0.

I e I e 9. The method of any one of claims 6-8, wherein the codeword a, is represented by a= do + z modulo-2, where d represents a predetermined code group to be encoded, G represents a predetermined 5 generator matrix, and z represents a function of the code group number and a row of the generator matrix. 10. The method of claim 9 wherein in a first case: 10 d comprises (Cr,f,uo,ul,u2), where Cr represents a bit indicative of chip rate, f is O for a first frame and 1 for a second frame, uO,u',u2 represent bits from a binary representation of the code group number, and 15 Z=U3(U2 +l)g4 reduced modulo-2, where g4 represents a row of the generator matrix.

11. The method of claim 9 or 10 wherein in a second case: 20 d comprises (Cr'K'fuoul)' where Cr represents a bit indicative of chip rate, K is O for a kth slot and 1 for a (k+l)'h slot, f is 0 for a first frame and 1 for a second frame, uO,u,u2 represent bits from a binary representation 25 of the code group number, and Z = U2 (Ut + I)g4 reduced modulo-2, where g4 represents a row of the generator matrix.

:: À:e '. ce Àe À: - 18 12. An encoder for efficient synchronization channel encoding in UTRA TDD mode, comprising: means for producing a codeword a, where a= dG + z modulo-2, where d represents a predetermined 5 code group to be encoded, G represents a predetermined generator matrix, and z represents a function of the code group number and a row of the generator matrix, means for producing values Sk=2a2k++a2k'k= 'l'2, and 10 associated values bi,b2,b3, and means for producing a value Sysc associated with the code group, where Sssc =(b'C(o)'b2c()'b3c(2)), car represents a code within the code group, and bi,b2,b3 (+1,+j) 13. The encoder of claim 12, wherein the generator matrix in a first case is substantially equal to O O O O 0 1

O O 0 1 0 0

0 1 0 0 0 0

1 0 1 0 0 0.

20 14. The encoder of claim 12 or 13, wherein the generator matrix in a second case is substantially equal to O O O O 0 1

0 1 0 1 0 0

O O 0 1 0 0

1 0 1 0 0 O..

: : : 8 À 1 - 19 15. The encoder of claim 12, 13 or 14 wherein in a first case: d comprises (f,uo,u',u2), where f is 0 for a first frame and 1 for a second frame, uO,u,u2 5 represent bits from a binary representation of the code group number, and Z=U3(U2 +l)g3 reduced modulo-2, where g3 represents a row of the generator matrix.

10 16. The encoder of claim 12, 13, 14 or 15 wherein in a second case: d comprises (K, f,uo,u), where K is O for a kth slot and 1 for a (k+1)'h slot, f is 0 for a first frame and 1 for a second frame, uO,u,u2 15 represent bits from a binary representation of the code group number, and Z=U2(U' +l)g3 reduced modulo-2, where g3 represents a row of the generator matrix.

e.. I:.: e; À - - 20 17. An encoder for efficient synchronization channel encoding in UTRA TDD mode, comprising: means for producing a codeword from a predetermined code group to be encoded, a 5 predetermined generator matrix G. and a function of the code group number and a row of the generator matrix, and means for producing a value S,.,.c associated with the code group, where S,,c = (b'C(o)'b2c()'b3c(2))' car 10 represents a code within the code group, and b,,b2,b3 e(+1,+j), wherein the generator matrix has values such that a parameter produced therefrom changes between a first value indicating a first chip rate and 15 a second number indicating a second chip rate.

18. The encoder of claim 17, wherein the generator matrix in a first case is substantially equal to O O O 0 1 0

O O O O 0 1

O O 0 1 0 0

0 1 0 0 0 0

1 0 1 0 0 0.

ma.: t-. '..: - 21 19. The encoder of claim 17 or 18, wherein the generator matrix in a second case is substantially equal to -O O O 0 1 0

O O O O 0 1

0 1 0 1 0 0

O O 0 1 0 0

1 0 1 0 0 0.

5 20. The encoder of any one of claims 17-19, wherein the codeword a, is represented by a=dG +z modulo-2, where d represents a predetermined code group to be encoded, G represents a predetermined generator matrix, and z represents a function of 10 the code group number and a row of the generator matrix. 21. The encoder of claim 20 wherein in a first case: d comprises (Crf,Uo,U,U2)' where Cr represents a 15 bit indicative of chip rate, f is 0 for a first frame and 1 for a second frame, uO,u,,u2 represent bits from a binary representation of the code group number, and Z = U3(U2 + I)g4 reduced modulo-2, where g4 20 represents a row of the generator matrix.

22. The encoder of claim 20 or 21 wherein in a second case: d comprises (Cr'K'fuou), where Cr represents a 25 bit indicative of chip rate, K is O for a kth slot and 1 for a (k+1)'h slot, f is 0 for a

:: ': c' c'::: Be: - 22 first frame and 1 for a second frame, uO,u,u2 represent bits from a binary representation of the code group number, and Z=U2(U +l)g4 reduced modulo-2, where g4 represents 5 a row of the generator matrix.

23. A wireless base station for use in a UMTS system, comprising an encoder as claimed in any one of claims 12-22.

24. A computer program element comprising computer program means for performing encoding functions as claimed in any one of claims 1 to 10.

15 25. A method for efficient synchronization channel encoding in UTRA TDD mode substantially as hereinbefore described with reference to FIG. 4 of the accompanying drawings.

20 26. An encoder for efficient synchronization channel encoding in UTRA TDD mode substantially as hereinbefore described with reference to FIG. 4 of the accompanying drawings.