GB2393863A

GB2393863A - PLL synthesizer in a cellular phone

Info

Publication number: GB2393863A
Application number: GB0327631A
Authority: GB
Inventors: Megumi Endo
Original assignee: NEC Corp
Current assignee: NEC Corp
Priority date: 2001-09-14
Filing date: 2002-09-13
Publication date: 2004-04-07
Anticipated expiration: 2022-09-13
Also published as: GB2393863B; GB0327631D0

Abstract

A cellular phone has consecutively a receiving slot (S11), an idling slot (S12) which is either a waiting slot or a peripheral information slot, and a transmitting slot (S13) in a single frame. The PLL synthesizer includes a loop filter block (30) between a charge pump (25) and a voltage controlled oscillator (50) to control the locking time of the PLL synthesizer for switching between the oscillation frequencies. The loop filter comprises a variable resistor (38) and a variable capacitor (39) controlled by a control unit (26). The control unit stores a plurality of patterns for the variable resistor and capacitor to set the time constant and the resulting locking time in switching between the transmitting, receiving and peripheral information receiving frequencies. Alternatively, an RC low-pass filter with variable or stepped resistors and capacitors may be provided in place of the loop filter block.

Description

GB 2393863 A continuation (74) Agent and/or Address for Service: Reddie &

Grose 16 Theabalds Road, LONDON, WC1X 8PL, United Kingdom

- 1 - PLL SYNTHESIZER FOR A CELLULAR PHONE

BACKGROUND OF THE INVENTION

The present invention relates to a PLL (phase locked 5 loop) synthesizer and, more particularly, to a PLL synthesizer for a cellular phone.

PLL circuits are widely used in the fields of, for

example, television receivers, satellite communications, and radio communications. The PLL circuit generates a 10 frequency signal in synchrony with a reference signal having a reference frequency, the frequency signal having a frequency of a specified ratio with respect to the reference frequency. For example, in a cellular phone system operating with a time division multiple access (TDMA) scheme, the PLL circuit is used as a PLL synthesizer which generates the frequency of a transmission channel.

Fig. 6 shows a conventional PLL synthesizer, which includes a PLL integrated circuit (PLL-IC) 20, a first so loop filter (LPF) 40, a second loop filter (LPF) 45, and a voltage controlled oscillator (VCO) 50. The PLL-IC 20 includes therein a phase comparator 24, a register 23, a divider 22, a prescaler 21, and a charge pump (CP) 25.

An output of the VCO 50 is delivered to outside the PLL synthesizer as well as the prescaler 21 to form a feedback loop. The prescaler 21 has the function of roughly dividing the input frequency with a high speed to assist the dividing operation by the divider 22. The divided-frequency signal 104 output from the divider 22 30 and the reference frequency signal (Ref_F) 100 are fed to the phase comparator 24. The phase comparator 24 compares the phases of the two input signals against each other to deliver a phase comparison result signal which depends on

- 2 which phase leads or lags with respect to the other. The charge pump 25 receives an output signal from the phase comparator 24 to deliver an output voltage signal to the VCO 50 through the LPF 40 and the loop filter 45. The 5 output frequency of the VCO 50 is controlled by the output voltage signal of the charge pump 25. Upon coincidence of the phase of the divided-frequency signal 104 with the phase of the reference frequency signal 100, the PLL synthesizer is locked, i.e. the oscillation frequency of lo the PLL synthesizer is fixed at a desired frequency.

The loop filter 45 is provided in order to control the locking time of the PLL synthesizer, i.e. the time interval between the time instant at which the change of the oscillation frequency of the PLL synthesizer is 15 started and the time instant at which the PLL synthesizer is locked to stabilize the oscillation frequency. The time constant of the loop filter 45 is set to conform with the locking time needed in the PLL synthesizer. For example, if the frequency should be switched at a higher speed, 20 then the time constant is set at a lower value, and if the frequency need not be switched at a high speed, then the time constant is set at a larger value to obtain a longer locking time.

For reducing the locking time the time constant of 25 the loop filter should be reduced. However, a smaller time constant increases the bandwidth of the loop filter and degrades the carrier-to-noise (C/N) ratio of the signal passing therethrough, degrading the characteristics of the radio system having the PLL synthesizer.

so If the PLL synthesizer has a configuration such that the output frequency thereof is changed stepwise, the time constant of the loop filter 45 should be set at a value corresponding to the minimum locking time necessary in the changeover for a specified output frequency. However, we 35 have appreciated that setting of the locking time at the value corresponding to the minimum locking time means that the minimum locking time is used in the changeover of all

- 3 - the other output frequencies wherein such a minimum locking time is not necessary, and that this means the PLL synthesizer is used in the state of degraded C/N ratio in all the other output frequencies due to achieving the 5 shorter locking time thus selected. In short, a smaller locking time and better radio characteristics are tradeoffs in the conventional PLL synthesizer.

SUMMARY OF THE INVENTION

According to a preferred embodiment of the invention, 10 there is provided a phase locked loop (PLL) synthesizer comprising: a phase comparator for comparing the phase of a first frequency signal having a first frequency against the phase of a reference frequency signal; a voltage controlled oscillator having an input node receiving a 15 frequency control voltage controlled based on a result of the comparison by said phase comparator, and an output node outputting a second frequency signal having a second frequency controlled based on said frequency control voltage; a frequency divider for receiving said second 20 frequency signal to divide said second frequency and to output said first frequency signal; and a loop filter connected at said input node of said VCO for passing said frequency control signal to said VCO, said loop filter having three or more time constants for a filter function 25 and a selector for selecting one of said time constants; wherein said loop filter includes a variable resistor and a variable capacitor, separately controllable by the selector to select one of said time constants.

The PLL synthesizer can be used in a cellular phone 30 which has three or more slots in a single frame. An

- 4 optimum time constant can be obtained in the PLL synthesizer for achieving an optimum locking time and excellent characteristics of the cellular phone having the PLL synthesizer.

5 The variable resistor and variable capacitor provide a simple structure for the PLL synthesizer, in comparison to a PLL synthesizer comprising a plurality of loop filters. BRIEF DESCRIPTION OF THE DRAWINGS

10 The invention will now be described in more detail by way of example and with reference to the drawings in which: Fig. 1 is a block diagram of a PLL synthesizer; Fig. 2A is a time slot diagram of a cellular phone 15 operating with a PDC scheme and Fig. 2B is a time chart showing transitions in the cellular phone; Fig. 3A and 3B are time charts of the receiving station and the transmitting station in a cellular phone system of a Full Packet scheme; 20 Fig. 4 is a block diagram showing connections of the loop filter block shown in Figure 1; Fig. 5 is a block diagram showing, similarly to Figure 4, a loop filter block in a PLL synthesizer according to the preferred embodiment of the present 2 5 invention; and Fig. 6 is a block diagram of a conventional PLL synthesizer. PREFERRED EMBODIMENTS OF THE INVENTION

Now, the present invention is more specifically So described with reference to the accompanying drawings, wherein similar constituent elements are designated by similar reference numerals.

- 5 Firstly, referring to Figure 1, a PLL synthesizer developed by the present applicants will be described by way of introduction. This PLL synthesizer is the subject

of the applicant's UK patent application GB 0221337.9 from 5 which this application is divided. The PLL synthesizer includes a PLL IC 20, a LPF (loop filter) 40, and a VCO 50. The PLL IC 20 includes a phase comparator 24, a register 23, a 1/N-divider 22, a prescaler 21, a charge pump (CP) 25 and a loop filter block (LF block) 30. The lo PLL IC 20 receives a reference frequency signal Ref_F 100 supplied from outside the PLL synthesizer, and serial data 101 supplied from a baseband LSI 60. The PLL synthesizer is controlled to be set at a desired oscillation frequency based on the serial data 101, and oscillates in synchrony with the reference frequency signal Ref_F 100.

The baseband LSI 60 delivers the serial data 101, which includes information of the frequency to be locked with in the PLL synthesizer. This is stored in the register 23 in the PLL IC 20.

go The serial data indicates one of a receiving frequency, a transmitting frequency, and a peripheral information receiving frequency, to allow the PLL synthesizer to be locked therewith. The register 23 delivers the stored serial data as a frequency control 25 signal 102 to the phase comparator 24 and the loop filter block 30. The output node of the PLL IC 20 is connected to the input node of the VCO 50 via the LPF 40 and the LF block 30. The output from the VCO 50 is fed back to the prescaler 21 in the PLL IC 20 and fed outside the PLL 30 synthesizer. The prescaler 21 has a function for variably dividing the input signal at a high speed, and co-operates with the 1/N-divider 22, which delivers a divided frequency signal 104 having a frequency of 1/N of the input frequency of the prescaler 21 to the phase 3 5 comparator 25.

The phases of the frequency-divided signal 104 and the reference frequency signal 100 are compared against

each other in the phase comparator 24, which delivers a phase comparison signal to the charge pump 25. The phase comparison signal controls the charge pump 25, to raise the output voltage thereof when the phase of the divided 5 frequency signal 104 lags with respect to the phase of the reference frequency signal 100, and to lower the output voltage of the charge pump 25 when the divided-frequency signal 104 leads with respect to the phase of the reference frequency signal 100.

lo The output voltage of the charge pump 25 is delivered to the VCO 50 via the LPF 40 and the loop filter block 30.

The output voltage of the charge pump 25 controls the output frequency of the VCO 50. When the phase difference between the divided-frequency signal 104 and the reference 15 frequency signal 100 becomes zero, the PLL synthesizer is locked. The loop filter block 30 includes first to third filters, LPI, LF2 and LF3, one of which is selected based on a selection control signal.

The PLL synthesizer may be used in a cellular phone so operating with a time division multiple access (TDMA) communication scheme or a personal digital cellular (PDC) communication scheme, for example. Referring to Figure 2A, a single frame in the PDC communication scheme includes therein four slots, i.e. a receiving slot Sit, an idling 25 slot S12, a transmitting slot S13 and a diversity slot S14 in this order, which have the respective time intervals as depicted in Figure 2A. The idling slot S12 is used as a slot for waiting for switching between the frequencies or is sometimes used as slot for receiving information on a so peripheral information receiving channel, which allows receipt of the electric field of the peripheral channel.

Referring to Figure 2B, there is shown a time chart of the operation of the cellular phone for switching between the receiving frequency channel and the 75 transmitting frequency channel. When the PLL synthesizer locked with the receiving-frequency channel is to be switched for locking to the transmitting-frequency

channel, an idling slot S12 is interposed between the receiving slot S11 and the transmitting slot S13. Since the idling slot S12 has a time interval of 5.67 milliseconds, switching from the receiving frequency 5 should be completed within a time interval of 5.67 milliseconds. A diversity slot S14 is provided between the transmitting slot S13 and the next receiving slot S11.

When the PLL synthesizer is eventually to be switched from the transmitting frequency to the receiving frequency, the lo switching should be completed within a time interval of 1 millisecond, because the diversity slot S14 has a time interval of 1 millisecond.

The idling slot S12 may be used as a slot for receiving a peripheral information channel, as described above. In this operation, the frequency switching in the idling slot S12 includes a first switching operation wherein the PLL synthesizer locked with the receiving-

frequency channel is switched to be locked with the peripheral information receiving channel, and a second so switching operation wherein the PLL synthesizer locked with the peripheral information receiving channel is switched to be locked with the transmitting- frequency channel. The switching operations in this slot S12 should be completed at a high speed because a blank slot such as 25 the idling slot is not disposed for the switching operations. Figures 3A and 3B show the operation of a pair of cellular phones, i.e. the cellular phone at a receiving end and the cellular phone at a transmitting end, so respectively, wherein both the cellular phones operate in a full-packet scheme or in a PDC scheme. In these schemes the receiver at the receiving end operates to receive packet data in all the slots of a plurality of consecutive frames, as shown in Figure 3A, whereas the transmitter at 35 the transmitting end operates to transmit in a single transmitting slot allocated in each single frame, as shown in Figure 3B. The receiver at the receiving end may

sometimes receive peripheral information during the successive receiving operations.

The frequency switching in the receiver of the full-

packet scheme includes, as one of the PDC schemes, the 5 first switching operation wherein the PLL synthesizer locked with the receiving-frequency channel is switched to be locked with the peripheral-frequency channel, and the second switching operation wherein the PLL synthesizer locked with the peripheral-frequency channel is switched lo to be locked with the receiving-frequency channel. To maintain the receiving state as long as possible for achieving an efficient receiving operation for the packet data, the time length for receiving the peripheral information should be reduced, and the frequency switching should be completed at a higher speed.

The modes of the frequency switching and the allowable time lengths (locking times) for the frequency switching, as well as the loop filters selected in the loop filter block 30 for the frequency modes are tabulated so in the following table 1.

Table 1

Switching Mode Locking Time Loop Filter Receive-Transmit5.67msec. EF1 Transmit-Receivelmsec. LF2 Receive-PeripheralTransmit High Speed LF3 PacketPeripheral-Packet High Speed LF3 Each loop filter LF1, LF2 and LF3 allows the PLL synthesizer to switch the channel within the allowable locking time tabulated in Table 1, wherein the time :5 constants TC of the loop filters LF1, LF2 and LF3 are as follows: TCF1 TCI,F2 TCF3

- 9 In terms of cut-off frequency, the low-pass-filter 40 has the highest cut-off frequency, and the loop filters LF1, LF2 and LF3 have cut-off frequencies decreasing in this order. Referring to Figure 4, the connections between s the LP block 30 and the PLL IC 20 in the PLL synthesizer of Figure 1 are shown. The LF block 30 includes three filters LF1, LF2 and LF3 which are selected by a switch section of the PLL IC 20, the switch section including switches SW1 to SW4. Each filter includes a serial lo resistor and a parallel capacitor.

In selection of the mode for switching from the receiving frequency directly to the transmitting frequency, serial data 101 indicating the receiving frequency is delivered from the baseband LSI 60 to the PLL IC 20. The register 23, after receiving the serial data 101, delivers information of the receiving frequency as a frequency control signal 102 to the LP block 30. The LF block 30 then selects one of the filters LF1, LF2 and LF3 based on the frequency control signal 102 received from so the register 23. The switching from the receiving frequency to the transmitting frequency is completed within a time interval of 5.67 milliseconds. This time interval allows the filter LF1 having the largest time constant to be used for this switching operation. The 25 largest time constant of the selected filter LPI, allows the PLL synthesizer to have a moderate switching speed, to operate with an excellent C/N ratio and to improve the radio characteristics of the PLL synthesizer.

In selection of the mode for switching from the so transmitting frequency directly to the receiving frequency, serial data 101 indicating the receiving frequency is delivered from the baseband LSI 60 to PLL IC 20. This switching operation is completed within a time interval of 1 millisecond by selecting the loop filter LF2 15 having the intermediate time constant suited for the switching.

- 10 In selection of the mode for switching from the receiving frequency to the transmitting frequency via a peripheral information receiving frequency, serial data 101 indicating the peripheral information receiving 5 frequency and the transmitting frequency are consecutively delivered from the baseband LSI 60 to the PLL IC 20. This switching operation should be completed as quickly as possible, and thus the loop filter LF3 having the smallest time constant is selected.

lo In selection of the mode for switching from the receiving frequency to the packet data receiving frequency for full packet data via the peripheral information receiving frequency, serial data 101 indicating the peripheral information receiving frequency and the 15 receiving frequency are consecutively delivered from the baseband LSI 60 to the PLL IC 20. In the full packet scheme, the time length for receiving the peripheral information should be as short as possible for achieving a longer time length for receiving the packet data. The loop so filter block 30 switches to select the loop filter LF3. By using the loop filter LF3 having the smallest time constant, the PLL synthesizer has the smallest locking time. Reference will now be made to Figure 5 showing a part 25 of a PLL synthesizer according to the preferred embodiment of the present invention. The PLL synthesizer of this embodiment is similar to the PLL synthesizer of the first embodiment except for the provision of a control unit 26 in the PLL IC 20. The control unit 26 receives data from so the register 23 to control the resistance of the variable resistor 38 and the capacitance of the variable capacitor 39 in an RC filter, instead of the provision of a plurality of loop filters LPI, LF2 and LF3 as in the synthesizer shown in Figure 1.

35 The variable resistor 38 may have a plurality of fixed resistors and associated switches for connecting a selected number of the fixed resistors in parallel to

- 11 obtain a desired resistance, whereas the variable capacitor 39 may have a plurality of fixed capacitors and associated switches for connecting a selected number of the fixed capacitors in parallel to obtain a desired 5 capacitance.

The control unit 26 stores information for a plurality of patterns of time constant for setting the locking times when switching the frequency of the PLL synthesizer from the receiving frequency to the lo transmitting frequency, from the transmitting frequency to the receiving frequency, from the receiving frequency to the peripheral information receiving frequency, from the peripheral information receiving frequency to the receiving frequency, and the peripheral information 15 receiving frequency to the transmitting frequency. when a frequency control signal 102 is delivered from the register 23, the control unit 26 selects one of the patterns stored therein based on the frequency control signal 102 indicating the locking time, to output the so selected pattern as a time constant control signal 103, thereby controlling the resistance of the variable resistor 38 and the capacitance of the variable capacitor 39. Thus, the locking time in accordance with the mode for the frequency switching can be obtained for the PLL 25 synthesizer.

In the synthesizer shown in Figures 1 and 4, a desired number of loop filters is provided in the loop filter block, whereas a desired number of combinations of the fixed resistors and the fixed capacitors is sufficient so in the second embodiment. Thus, the preferred embodiment achieves a simple structure for the PLL synthesizer.

Since the above embodiment is described only as an example, the present invention is not limited to the above embodiment and various modifications or alterations can be 35 easily made therefrom by those skilled in the art without departing from the scope of the present invention.

- 12 For example, the configurations of the variable resistor and the variable capacitor may be modified from the above embodiment such that the fixed resistors and/or the fixed capacitors may be connected in combination of 5 series and parallel connections. In addition, the present invention can be applied to any PLL synthesizer other than the PLL synthesizer of the TDMA scheme.

Claims

- 13 CLAIMS

1. A phase locked loop (PLL) synthesizer comprising: a phase comparator for comparing the phase of a first frequency signal having a first frequency against the 5 phase of a reference frequency signal; a voltage controlled oscillator having an input node receiving a frequency control voltage controlled based on a result of the comparison by said phase comparator, and an output node outputting a second frequency signal having lo a second frequency controlled based on said frequency control voltage; a frequency divider for receiving said second frequency signal to divide said second frequency and to output said first frequency signal; and 5 a loop filter connected at said input node of said VCO for passing said frequency control signal to said VCO, said loop filter having three or more time constants for a filter function and a selector for selecting one of said time constants; 20 wherein said loop filter includes a variable resistor and a variable capacitor, separately controllable by the selector to select one of said time constants.

2. The phase locked loop synthesizer of claim 1, wherein the variable resistor comprises a plurality of fixed 25 resistors and associated switches for connecting a selected number of the fixed resistors to obtain a desired resistance, and wherein the variable capacitor comprises a plurality of fixed capacitors and associated switches for connecting a selected number of the fixed capacitors to so obtain a desired capacitance.

3. A cellular phone comprising the PLL synthesizer as defined in claim 1 or 2, wherein said cellular phone has three or more time slots in a single frame.

- 14

4. The cellular phone as defined in claim 3, wherein said single frame includes a receiving slot, an idling slot and a transmitting slot in this order.

5. The cellular phone as defined in claim 4, wherein 5 said idling slot is either a waiting slot or a peripheral information receiving slot for receiving information of an electric field of a peripheral information channel.

6. The cellular phone as defined in claim 5, wherein said single frame further includes a diversity slot lo succeeding said transmitting slot.

7. The cellular phone as defined in claim 5 or 6, wherein said time constants include first to third time constants which reduce in magnitude in this order, and wherein said selector selects: said first time constant upon switching from said receiving slot to said transmitting slot via said waiting slot; said second time constant upon switching from said transmitting slot to said receiving slot; and so said third time constant upon switching from said receiving slot to said peripheral information receiving slot and upon switching from said peripheral information receiving slot to said transmitting slot.

8. A phase locked loop (PLL) synthesizer as s substantially described herein and with reference to Figures 2, 3 or 5 of the drawings.

9. A cellular phone as substantially described herein and with reference to Figures 2, 3 or 5 of the drawings.