GB2386721B - A method of modeling the crossover current component in submicron cmos integrated circuit designs - Google Patents

A method of modeling the crossover current component in submicron cmos integrated circuit designs

Info

Publication number
GB2386721B
GB2386721B GB0304013A GB0304013A GB2386721B GB 2386721 B GB2386721 B GB 2386721B GB 0304013 A GB0304013 A GB 0304013A GB 0304013 A GB0304013 A GB 0304013A GB 2386721 B GB2386721 B GB 2386721B
Authority
GB
United Kingdom
Prior art keywords
modeling
integrated circuit
current component
circuit designs
cmos integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB0304013A
Other versions
GB2386721A (en
GB0304013D0 (en
Inventor
Thomas W Chen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of GB0304013D0 publication Critical patent/GB0304013D0/en
Publication of GB2386721A publication Critical patent/GB2386721A/en
Application granted granted Critical
Publication of GB2386721B publication Critical patent/GB2386721B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/32Circuit design at the digital level
    • G06F30/33Design verification, e.g. functional simulation or model checking

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
GB0304013A 2002-03-14 2003-02-21 A method of modeling the crossover current component in submicron cmos integrated circuit designs Expired - Fee Related GB2386721B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/098,112 US6728941B2 (en) 2002-03-14 2002-03-14 Method of modeling the crossover current component in submicron CMOS integrated circuits designs

Publications (3)

Publication Number Publication Date
GB0304013D0 GB0304013D0 (en) 2003-03-26
GB2386721A GB2386721A (en) 2003-09-24
GB2386721B true GB2386721B (en) 2005-11-09

Family

ID=22267194

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0304013A Expired - Fee Related GB2386721B (en) 2002-03-14 2003-02-21 A method of modeling the crossover current component in submicron cmos integrated circuit designs

Country Status (2)

Country Link
US (1) US6728941B2 (en)
GB (1) GB2386721B (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6981231B2 (en) * 2002-02-22 2005-12-27 Hewlett-Packard Development Company, L.P. System and method to reduce leakage power in an electronic device
US7007247B1 (en) * 2002-05-24 2006-02-28 Cadence Design Systems, Inc. Method and mechanism for RTL power optimization
US6862715B2 (en) * 2002-07-29 2005-03-01 Hewlett-Packard Development Company, L.P. Systems and methods of cross-over current calculation within electronic designs
US7137080B2 (en) * 2003-08-22 2006-11-14 International Business Machines Corporation Method for determining and using leakage current sensitivities to optimize the design of an integrated circuit
US7000204B2 (en) * 2003-09-02 2006-02-14 Hewlett-Packard Development Company, L.P. Power estimation based on power characterizations
JP5161035B2 (en) * 2008-10-29 2013-03-13 ルネサスエレクトロニクス株式会社 Semiconductor integrated circuit design apparatus, design method, and program
JP5492429B2 (en) * 2009-03-05 2014-05-14 ルネサスエレクトロニクス株式会社 Circuit design support device, circuit design support method, program
JP5471568B2 (en) * 2010-02-17 2014-04-16 富士通セミコンダクター株式会社 Verification program, verification method, and verification apparatus
US20120144353A1 (en) * 2010-12-06 2012-06-07 Kamdar Chetan C Method for Implementing Timing Point Engineering Change Orders in an Integrated Circuit Design Flow
US8495553B2 (en) * 2011-12-09 2013-07-23 International Business Machines Corporation Native threshold voltage switching
US9754058B2 (en) 2015-11-05 2017-09-05 International Business Machines Corporation Cross-current power modelling using logic simulation

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5446676A (en) * 1993-03-29 1995-08-29 Epic Design Technology Inc. Transistor-level timing and power simulator and power analyzer
US5471409A (en) * 1992-10-12 1995-11-28 Mitsubishi Denki Kabushiki Kaisha Logic simulation apparatus and circuit simulation apparatus
US5521834A (en) * 1993-11-30 1996-05-28 At&T Global Information Solutions Company Method and apparatus for calculating dynamic power dissipation in CMOS integrated circuits
US5696694A (en) * 1994-06-03 1997-12-09 Synopsys, Inc. Method and apparatus for estimating internal power consumption of an electronic circuit represented as netlist
US6212665B1 (en) * 1998-03-27 2001-04-03 Synopsys, Inc. Efficient power analysis method for logic cells with many output switchings

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5471409A (en) * 1992-10-12 1995-11-28 Mitsubishi Denki Kabushiki Kaisha Logic simulation apparatus and circuit simulation apparatus
US5446676A (en) * 1993-03-29 1995-08-29 Epic Design Technology Inc. Transistor-level timing and power simulator and power analyzer
US5521834A (en) * 1993-11-30 1996-05-28 At&T Global Information Solutions Company Method and apparatus for calculating dynamic power dissipation in CMOS integrated circuits
US5696694A (en) * 1994-06-03 1997-12-09 Synopsys, Inc. Method and apparatus for estimating internal power consumption of an electronic circuit represented as netlist
US6075932A (en) * 1994-06-03 2000-06-13 Synopsys, Inc. Method and apparatus for estimating internal power consumption of an electronic circuit represented as netlist
US6212665B1 (en) * 1998-03-27 2001-04-03 Synopsys, Inc. Efficient power analysis method for logic cells with many output switchings

Also Published As

Publication number Publication date
US20030177460A1 (en) 2003-09-18
GB2386721A (en) 2003-09-24
GB0304013D0 (en) 2003-03-26
US6728941B2 (en) 2004-04-27

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20080221