GB2385176A - Priority encoder - Google Patents

Abstract

A priority encoder comprises a number of nodes formed of groups of transistors. In use the transistors are connected such that a node is pulled low if the transistors in a group G(j) and the transistor H(j+1) is on when operating on a set of ordered integers. The integer set used by the encoder may also be minimised by a cost function. The encoder may also have one of three outputs. In the first embodiment each node may have N output circuits C i , i=0,1,(N-1) connected to a first input C i [0] and a second input connected to C i [1], each circuit being coupled to node N i and N i+1 respectively to provide an output voltage indicative of a logical AND. In a second and third embodiment the encoder may be used to identify the leading zero or leading one of a binary N+1 bit word (B n , B n-1 ...B 0 ).

Description

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BrokenStackPriorityEncod, Field The present in vention relates to circuits, and more particularly, to priority encodercircuits.

Background Priority encoders provide signals indicative of the leading one ("1") or zero ("0") in a binary word. Usually. a priority encoder wit ! have as many output lines as the

length or number of bits in a binary word, and the-voltages on the oueput lines indicate the leading one or zero in t binary word. For cxantplc, a priority encoder to indicate the tending one in an S-bit word may have eight output lines in w :. ich at most one output line has a HIGH voltage (the others arc at a LOW voltage), where the one output line with a HIGH voltage indicates the position of the leading one.

t Wirun a nortty encoder circuit. there may be :'ne or n''ore groups (or stacks) of L seria ! ! y connect. ed transistors which bring various nodes (0 a LOW (ground) volt@ge, depending upon the bit values of the word. To discharge (or puB down) ;). node to LOW, a transistor stack provides a conducting path between the node and gre@nd. An output circuit coupled to these nodes may then provide the necessary signats indicadng the

tcf'tng zero or one in the word- In a domino (or dynamic) type priority encoder circuit. the nodes are charged (or pulled up) to a HIGH voltage during a pre-charge state or phase of a clock signal, and then some or all of the nodes arc discharged by various transistor stacks during an

evaluation state or phase of the clock signal. The speed at which a domino priority C > encoder can operate may be lirnited by the speed at which the various nodes can be 'isch. l I discharged. For a given technology, this speed may be increased discharge t'iiie is decreased) if the stack depths of the transistors (i. e. < \ he number of serially connected transistors in a conducting path between a node and ground) are reduced. For a static type priority encoder circuFt.. tt lso may be desirable to reduce the stack depths to increase speed. Also. for CMOS (Complementary Meta Oxide Semiconductor) technology, reducing stack depths may be desirabie due to the sc-ciHed body effect. z, c

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Therefore, it is desirable to reduce the transistor stack depths in priority encoder circuits.

According to this invention there is provided a priority encoder as chimed in claim 1 herein.

Brief Description of the Drawing Fig. 1 is an embodiment of a dynamic type broken stack priority encoder.

Fig. 2 is an embodiment of a static type broken stack priority encoder.

Detailed Description of Embodiments We begin with terminology. The two-element Boolcan algcbra is relevant to switching circuits. For any point in a circuit, the term LOW will denote a set of voltages

that map into one of the two Boolean elements, and the term HIGH will denote a set of voltages that map into the olher of the two Booiean clements. The particular range of voltages that. map into the Boofcan cements depends upon the technology used. and may be different for different parts of a single circuit. To avoid dealing with set terminology, we shall say that a voltage is LOW (H ! C ! t) if it beiongs to the set LOW (HIGH). We also foHow the convention that for any given node within a circuit. LOW voltages arc less than HIGH voltages.

For the particuiar embodiments describcd herein, we sh < ; U incur a slight (but usual) abuse of notation by allowing the terms HIGH and LOW, which havc been defined as voltages, to do doub ! e duty. so that HIGH and LOW a ! so represent the two 'Boolean elements of the two-element Boolean algcbra. It will be clear from context when HIGH or LOW represent a voltage or a Boolean clement. It is customary to Identify HIGH with the identity element for the binary Boolean operation AND and to identify LOW with the identity element for the binary Boolean operation OR. and this custom is followed here. Such an identification is pedagogically useful, but arbitrary, and it should be appreciated that the present invention is not limited by this particular

identification of voltages with Boolean elements. z ; l

Let an 8-bit word IV s expressed as ' where B'ts the t'th bit of word . B7 and Bo are, rcspcctively, the most significant bit and the least significant bit D, also denote i voltac ; c of word W. We incur another slight abuse of notaLion and ict'atso denote a vohage and Boolean e. ! emcnt., and without loss of gcncraiity we take'to be HIGH if the ith bit

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of word W is I and to be LOW if the fth bit of word W is 0. The temm"word"is not to be confused with the wordlength of a computer system. Here, a word simply refers to a binary tuple.

Shown in Fig. i Is an embodiment priority encoder 100 for word The output of Fig. I is the set '''", where an'represents either a voltge or. 1 Boolean element, depending upon context. In Fig. l, a set of values such that 0 D Ei =-,'-OW for all i--k and EL = HIGH indicates that the leading zero of word W is the h it ss f ff LOW for all i, then word has no tcading zero, i. e., all the bits for if are ones.

In Fig. 1. o,', and represent voltages or Boolcan cfcments. dcpcnding > 0 a upon context As vohagcs, they represent, gate voltages for nMOSFETs (n-Mctat Oxide Semiconductor Fictd Effect Transistor) 114. 116. and II S, respectively. When considered as Boo ! ean elemcnts. A', and arc givcn by the Boolean expressions au = Bo B, Ao = Do dz J A, = B, 0 33 * B. 1 AI = . ./ ?, where. dcnotcs logical (Boolean) AND. In fig, I, domino gates 122, 124. and 126 are used ! o provide".'. and . although other types of logic gates may be employed.

A set of 8 nodes - '''-* is hbelcd in Fig-L In addition to being a A set of 8 nodes Ilabel, the symbol N, is also used to indicate the voltage or Boolean value of node Ni. depending upon context. When clock signal CLK is LOW ( or ground), pMOSFETs 102 are ON and nMOSFET 103 is OFF. so that all nodes arc charged (pulled up) to v HIGH This is the pre-chargc state (phase). The evaluation state (phase) is 0 characterized by CLK being HIGH. During an evaluation phase, pMOSFETs 102 are 1 0 OFF and nMOSFET 103 is ON, causing some of the nodes to be pulled down to LOW depending upon the values for .''"''''".

The gates of nMOSFHTs 104. 106, 10S, 110. nd 112 are at voitages Bi. i = 1.

3, 4, 6, and 7, respectively, and the gates of nMOSFETs 114, 116, and 118 are at

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voltages. 4,. i = O. 1, : md 2, respectively. During an evaluation phase. it cm be seen t t from Fig. lthatthevaJucSornoUc expressedintennsoflhebirvalues is givcn by

where the over-bar denotes Boolean complement and the product indicates the Boolean AND opcration.

The above expression assumes that a node, if not discharged to ground via a conducting path of transistors, will hold its charge during the evaluation phase. This I I al is assumption depends upon the capacitance of a node and the switching frequency of CLK. If needed, in some embodiments half-keepers may be employed at the nodes to { keep them charged HIGH if they a c not discharged to ground potential via a " conducting path of transistors.

Note that in Fig. 1 the path from any node to ground (not counting nMOSFET 103) is only three transistors. It is desirable to keep these paths as small as possible because the discharge time for any node is dependent upon the number of scrially Z > connected transistors discharging the node. to ground. In a sense, the stack of transistors 104, 106. 108, 110, and 112 is "broken" at nodes Ni. i = O. 2, and 5, so that some or,-, Il of transistors 114, 116. and 118 provide a bypass path between these nodes and ground.

Hence the name "broken stack" priority encoder.

The outputs', = 0, 1.-.. 6. arc indicative of the nodc voyages via logic gates Ei I zzl-1 0 120. In terms of node Boolean values. the values for'arc given by

(ss B... B) E In termof . heBcolean or bit inputs ( '"o). hc'are given by

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The above two Boolean expressions are equivalent to the statement that * = HIGH if and only if Bk = LOW and B''B' '' are all HIGH. Therefore, the embodiment of Fig. I is seen to be a priority encoder.

An entire class of embodiments for any word Uof arbitrary word length N+1, C > denoted by N. v- ! 0, may be described as follows. Choose a set I of ; +I . 1 = {11 11 --. II}/I > l Integers Klvvltt) Isuch tliit Xltt = N f l < =0 t=0 k=O Define the +2 sums. .. =0. L... L as t-I Sl : = Iflj'k > 0. zu J=o Fi Note that-'== + Partition the set of ordered integers (0, 1,... A) iiito K+ I disjoint ctsk 0, I.... K, of ordered integers where /, . (+i).... (S,- +)} Note that the lt the number of elements in the set I L is II L. Label the elements in from I ieftto right.. 3. s L < J-0. 1.--- (/- !) r) fe a set of S+ 1 values (Boolean or voiLaae) {4o Al a 4} whel : e voitage) iA'""- J where iu r, At Bi Note that AI ; is the logical AND of"t terms.

Using the above formalism, an embodiment can now be described as follows for C > any chosen Integer set A There are N+l nodes {NO'Afl, a by-pass stack 0 K + 1 Z > nMOSFETs connected in series, and a broken stack of (A-/\") nMOSFETs. The broken stack comprises +1 groups t. =O. I---A., oFeriaIfy connected nMOSFETs. sizicl comprises K+ I groups Group comprises ' ' serially connected nMOSFETs labcled as

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-'). The, atr- voliaze of nMOSFET G is '', where to avoid subscripts with subscripts we have set '-. -t. (This) ast statement may perhaps be more easily visualized by noting that deleting bits-'.''"-o'"')''"'-' from (B B... 8) the word ' 't"' yields a vector whose values are the gate voltages of the nMOSFETs in the broken stack.) The drain of nMOSFET [i] is connected to (or defines) node IV'Ili). Label the A+t nMOSFETs in the by-pass stack as /-/-]. = 0. 1.-.- voitagc of nMOSFET is'. the drain of NI [A :. Ot 1-1 [k j nMOSFET defines node - '. and the source of nMOSFET is connected G, (114 to the source of nMOSFET [-H.

To continue the description of the above embodiment for the chosen integer set D /. nn pMOSFET is connected to each node and has a gate controlled by a clock signal CLK, and an nMOSFET r5 connected to the source of nd has a g-itc controlled by the clock signal CLK. There sre N output circuits C ;. i =0, l,--- (A-i) each having an output voltage -,.''''. '"\."", jpach output circuit Ci has two inputs labeled as ' -J and C''having voltages''and -'. rcspcctiveiy.

(Again, our notation is performing a double duty.) For any output circuit t C, 0' (H-1) its output volta-c is-iven by Ei = : C, (0)-C, 111, in ut cicol : s C.. < =OJ..-- (/V- !) , =CJO]. CC, [Oj connected to node', and input C ; ['] is connected to nods thé embodiment also has an output voltage EN dcfined as the output voltage of node NIV.

13, 13, ---B.' In terms of the Boolean or bit inputs it can be shown that the 'are given by xi y El =) I BT t i-, e, Nr E, t= ; tel Em BH

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The above two Boolean expressions are equivalent to the statement that = HIGH if -ind only if Bk = LOW-, ind B B and only if =LOW and ''.'"'areall HIGH. Therefore, the above formalism describes a priority encoder.

An optimum integer set can be defined as that integer set which minimizes a cost function. One particular cost function is the maximum stack depth of transistors connecting each node to ground, including the number of terms in each expression for A, AI. For simplicity, we do not include any clocked transistors in the stack depth.

Including in a cost function the number of terms in each Boolean expression for A ; is warranted if these voltages are obtained by domino, logic gates performing logical I I D ANDs applied to the appropriate terms'. for then the number of such terms is indicative of the stack depth of such domino logic gates used to obtain Ai.

Such a cost function C (/) is obtained as follows. The stack depth for nodes ,.,,.. = .... (..-t) : t =0..... A-} ,,-.. A-- , nodes'-' ''''-'is ' ". foe. however, th the maxurnim stack depth for the nodes is cicarlv K + I, the totil number of I nMOSFETs in the by-pass stack. The number of terms in the Boolean expression for Ai ; is ''. Thus, we can write a cost function as (+I). {.. k O. I.-}] C (/) = max, { (-f±/ :) =I. 2.-- (-I) :/ : =0. !.-} Then, given/V. a particular optimum integer set is a set 0" k WIt íx=+i , n, Fi1 where 1 : =0 such that C (l) min C (J) The above Integer set is the so-called"min-max"solution-It can be verified that for a word length of 8 (i. e., N = 7), the min-max integer set for the above cost criterion or

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I-- : : : f2, 1. 11 function is unique and is'-"''J, which is the intcgcr set for . hc embodiment of Fis. t.

Other cost functions may be chosen. For example. if [he voltages AI are y 4. obtained by circuits in which the stack depths are rc ! ativc) y small, then the followin cost function may be of utility :

C (I) =max [(A'-t- !). {(/ ;,- < ±)./= 1. 2,-- (n,- !) A-= . !.-- }]

Other cost functions may be based upon an average stack depth, rather than the maximum stack depth. The average may weight the stack depths according to a weighting factor if there is a priori information that some nodes arc more likely to be C : 7 discharged than others. The min-max approach may be the more conservative approach, t but clearly many cost functions may be utilized.

( ft should be noted that if the integer set is chosen such chat for all "'''""\ then = . the resuming priority encoder degenerates to the case in then the rcsultin... 1, which there is only one stack (one by-pass stack and no broken stack, excluding any I stacks to obtain Ai). and the stack depth for node No is 1 Thus. for there to bc a broken stack. there should be at {cast one integer 'in the integer set for which"' I.

S : vcral priority encoder embodiments as described herein may be combined together into a single priority encoder for handling large word lengths. For example. for a 6 : t-bit word, four priority encoders for N = 7 as described herein may be used to encode eight 8-bit blocks of the 64-bit word in a parallel fashion. Relatively simple logic gates may be employed to indicate the leading one or zero of the 64-bit word based upon the outputs from the N = 7 priority encodersVarious modifications may be made to the above disclosed embodiments-For example, clocked nMOSFETs may not be needed if the gate voltages arc obtained from other domino logic gates in which inverters are used between the domino logic gates and the priority encoder, for then all gate voltages will be LOW during the pre-charge phase. In this case, the source of the last transistor in the broken stack is connected to ground. On the other hand. if the voltages At are not obtained via domino logic gates.

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then a clocked nMOSFET may be needed at the source of the last transistor in the by-

{ pass stack.

It should be appreciated that the embodiments described above arc of the domino (or dynamic) type, in that various nodes are pre-charged (pulled up) HIGH before possibly being discharged (pulled down) by stacks of serially connected transistors. However, other embodiments may include static type (dual-rail) circuits.

In the static case, the clocked transistors arc not needed, and for each relevant < t node one or more pMOSFETs are connected in parallel to pull up the node HIGH when any of the pMOSFETs are ON. Whereas in the dynamic case all relevant nodes arc pulled up HIGH during a pre-charge phase and a subset of the relevant nodes is pulled , down LOW during an evaluation phase, in the static case all relevant nodes are either LOW or HIGH (after some settling or delay time intcrval) depending upon the current gate voltages of the various nMOSFETs and pMOSFETs. To avoid cumbersome terminology, we shall say that a stack of nMOSFETs pulls down a node LOW if the

stack brings the node voltage from HIGH to LOW. or. if It keeps the node LOW if the node is already LOW. A similar statement applies to pMOSFETs that pull up (or keep) a node HIGH.

A static embodiment is easily obtained by modifying a dynamic embodiment as

follows. Remove all clocked pMOSFETs and all clockcd nMOSFETs from the dynamic embodiment, where transistor sources that were connected to a clocked nMOSFET are now connected to ground. For each N, connected to a transistor staCK of depth/I, add 11 0 pMOSFETs, each with a drain connected to Ni and a source connected to a HIGH voltage source, where each pMOSFET belonging to the added pMOSFETs has a gate connected to one and only one of the gates of the nMOSFETs within the transistor stack

for".

An example of a static priority encoder corresponding to the dynamic priority encoder of Fig. I is provided in Fig. 2. where corresponding clements in Figs. 1 and 2 have the same label. Fig. 2 is similar to Fig. I, except that the source of nMOSFET 112 is connected to ground, all clocked transistors are deleted, and pu ! ! up pMOSFETs have been added as explained above.

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It should also be appreciated that other embodiments may include technology ( other than CMOS. For example, other types of IGFETs (Insulated Gate Field Effect Transistor), or FETs (Field Effect Transistors), may be employed instead of the nMOSFETs and pMOSFETs described above. More gencrruiy, other types of transistors, such as bipolar transistors, may be employed instead of the nMOSFETs and pMOSFETs.

In other embodiments, the outputs Et may be complemented, in which case a LOW output signal provides information indicative of the leading zero bit.

Furthermore, any leading zero priority encoder is easily converted into a leading one priority encoder by complementing the word W. Therefore, the term priority encoder encompasses circuits which provide output signals indicative of either the leading one or leading zero of a word.

Consequently, it is clear that many modification may be made to the embodiments described herein without departing from the scope of the invention as claimed below.

Claims (1)

1. CLAIMS : 1. A priority encoder comprising : a set No""''". ofAH+I nodes. :, K+l transistors HJ- P. - : and G k - 0 1. K. G -. nt -1 K+ cecrps Gt,/ : = 0. 1-"'. of transistors, each group { ; comprIsIng I trsfstors H. < = 1. 2..-. (-j.). wherein the incecer set V'o. t'"'"A-/ and K are such that : . 1 X=+ ! {=oxo tir for which ni > !. wherein foreach =0. 1.-". ; = !. 2.--- (-Dhe transistor is coupled to node - to pu !) down node - LOW if transistors {CJ 7j] (I).- (- !)} 7= (I), (k. 2)..-. , I are ON, kvhcrc the latter sc. t is null if == A", where ' . where hs the/th e ! cment . , viiere is the ith element (counting from zero, 1cft to right) of the ordered set of integers = {. (+I).- (,where- k =0. 1."-+Ic such that t-f St==Ll1i'k > 0.

   /=0 C),- 50 =O ;

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   4 - tach k = 0, 1,---K, Htk, 3 is couplp-d to node Nift, o) wherein for each = O'-'", the inmsor is coupled to node '"' to pull down node LOW ifnstors - = ''''-'-" a. c ON.

   2. The priority encoder as set forth in claim 1, wherein the integer set I minimizes a cost function.

   J 3. The priority encoder as set forth in claim 2, wherein the cost function is

   < .

   ' (+1). {./ : = (U.-}.

   C (jf) =max- { (-±), f= !. 2.- (-I) :/ : 0. 1.-} 4. The priority encoder as set forth in claim 1, further comprising : N output circuits C,. f = 0. 1.--. (/V-i) having a first input having voltage and a second input having voltage'C'''-', each output circuit C ; having itsirst in ; coupled to node N, and its second input coupled to node N'to provide an output voltage indicative of C'. '. [I] where-denotes logical AND and the overbar denotes logical complemcnt.

   5. The priority encoder as set forth in claim 4, wherein the integer set I minimizes a cost function.

   6. The priority encoder as set forth in claim 5, wherein the cost function is (+1). {. -OJ.C (7) =man { (-/-t--=2.- (-t) : =0. 1..-}

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   , 7. The priority encoder as set forth in claim 1, further comprising : an output circuit to provide at least one voltage indicative of the leading zero of

   a binary A+t bit word -''") if for each k 0, 1,---K ; i1, 2,--- (n,--1), transistor GL* I'] is responsive tu bu to for each ''"'. transistor "'is responsive of"t, where AI : = TIB ; ici \. where product denotes logical AND.

   8. The priority encoder as set f01 th Ïn claim 1, further comprising : an output circuit to provide at least one volte indicative of the leading one of a binary/V+ ! bit word ('-''") if forcach = ' ' '- '" !-\ transistor is responsive of for each - '.'"- K, transistor is responsive of At, where At B ; '.

   where product denotes lo. ical AND.

   1. r 9. the priority encoder as set forth in claim 7, wherein the integer set 1 minimizes a cost function, where the cost function is

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   (+1). {. =0. !.-}.

   C (/) =max, C (-t±). f= !. 2.- (/t,- !) :/ : 0. 1.-K} (PI i + K-k), i = 1. 2.--- (., tI 10. The priority encoder as set forth in claim 8, wherein the integer set I minimizes a cost function, where the cost function is < ) (+1). {=0. 1.--}.

   C (i) = mua { (-f±). f= :. 2.-.. (-t) : =OJ.-} I 11. The priority encoder as set forth in claim 1, J : further comprising : {N N... N} at least one clocked transistor to pull up all nodes in the set L o' !'/j HIGH if a clock signal is in a first state, W en : 1I1, the tranSIstOrs'.,, and ''= !.-" C"D. = 0. !.-" coupled to the nodes to pull a subset of the nodes LOW based upon which of the transistors'"'. J. -. I,'" GJ < ].'= arc ON if the clock sl,,,, nal is in a second state complementary to the first state.

   12. The priority encoder as set forth in claim 1, further comprising : for each i ''", at least one transistor coupled to node N, to pull up node N ; HIGH if and only if transistors H [k], k = 0, 1,---K, and G, [t'J./= L.-. (n,-1)./ : = 0. 1,-.- . pj} .. o\V.