GB2381607A - Serila-parallel correlator architecture - Google Patents
Serila-parallel correlator architecture Download PDFInfo
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- GB2381607A GB2381607A GB0126238A GB0126238A GB2381607A GB 2381607 A GB2381607 A GB 2381607A GB 0126238 A GB0126238 A GB 0126238A GB 0126238 A GB0126238 A GB 0126238A GB 2381607 A GB2381607 A GB 2381607A
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/15—Correlation function computation including computation of convolution operations
Abstract
This invention relates to a parallel system architecture for the efficient computation of the time windowed or full correlation function for data series of arbitrary length and form. Data series enter the correlator serially and thus both input sequences may be sampled in real-time. The correlator arrangement enables the required correlation window to be completely formed immediately after the final data samples of the series enter the system. The correlator architecture minimises the system complexity by only calculating the correlation function over the required window allowing arbitrary length data as the input series. The system surpasses hitherto parallel architectures reducing both the complexity and correlation function acquisition time.
Description
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DIGITAL SERIAL-PARALLEL CORRELATOR ARCHITECTURE The invention relates to signal correlator for determining the measure of similarity between signals, more precisely, a digital serial-parallel signal correlator architecture in which data series enter the correlator serially and are processed in parallel.
The correlation process forms the basis for a variety of applications involving pattern recognition. It is extensively applied in areas such as statistics, prediction, geophysics, and in electronic instrumentation and systems. The method of obtaining the correlation between sets of data varies and is dependent on the form of the correlation required and the length and form of the data sequence.
In this case we arc concerned with sampled data sets which are processed digitally There are two distinct methods employed in forming the correlation of two sets of data. The first makes use of the multiplication of the discrete Fourier components of the time series, the frequency domain equivalent to correlation in the time domain. This is in general faster for signals of arbitrary data length than the second method which involves applying a shift-multiplyadd algorithm and architecture Both methods have their advantages and are suited to different applications. The different choice of correlator architecture employed will be dependent on the form of the input signal data series and constraints inherent in either architecture which render them inefficient or inappropriate in certain cases.
Much of the signal processing undertaken today is realised using general purpose digital signal processors (DSPs).
These processors are designed for number crunching and are highly efficient in accomplishing dedicated signal processing tasks such as the transform of data between the time and frequency domains. Many correlation processes take advantage of the DSP processing power in forming the correlation function between sets of data Where the correlation function is calculated by making use of the DSP processor the transform of both data sets from the time to the frequency domain is taken. The frequency components of the one data set are then multiplied by the complex conjugate of the other before transformation back to the time domain By using an efficient
algorithm such as the fast Fourier transform (FFT) data sets of arbitrary length may be correlated far more quickly than through the direct evaluation of the correlation function in the time domain Making use of the frequency domain and in particular the Fourier transform, to correlate a finite data series has implications which must be observed when evaluating either the resulting frequency or time domain function. The Fourier transform of a finite function corresponds to a periodic rather than aperiodic function This results in one cycle of a periodic correlation function, which differs from the true correlation function of the aperiodic data series.
The effects of the periodic representation of the sampled time series may be reduced by the zero padding of the data in the time domain before taking the transform to determine the frequency components.
Difficulties arise when a long time data series must be decomposed into shorter time sections for processing by means of the FFT to be variable. Addition of the resulting correlation functions does not give the same result as would be obtained by operation on the whole series without decomposition
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General purpose DSPs have extensive arrays of memory to hand which may not be dedicated to the specific task of correlation and which may also be upgraded or extended by the operator through variations in addressing.
Therefore, the complexity of the architecture required for the elevuation of the data series is in most cases is not dependent on the length of the data series. However, the memory that is used in forming the correlation must retain the full data set of the series to be correlated throughout the evaluation.
Before computation of the frequency domain components of a data series using the Fourier transform method, the full data set to be transformed must be held in memory, this places further constraints on the use of the frequency domain to calculate the correlation function. Primarily the evaluation cannot commence until the full series has been sampled and transferred to the memory accessed by the DSP. secondly the full data series must be retained in memory until the correlation is evaluated. If acquisition time of the correlation function is an issue the delay between obtaining the data and being able to compute the function becomes a constraint.
Where it is necessary to reduce redundant time, a dedicated hardware architecture may be designed to perform the specific task These dedicated architectures come in many forms but in general all compute the correlation function
in the time domain by employing a shift-multiply-add algorithm and architecture.
Conventional hardware for the time domain evaluation of the correlation function of two data sets (n) and S2 (n) both of length N, incorporate a series of shift registers to hold the values of the incoming time series and a second set of registers to hold the second of the signals. In addition memory to hold the evaluated correlation function is also required The product of the corresponding data samples of S, (n) and is computed in one of N multipliers and me sum of all products taken for each time shift. Most other correlators that evaluate the correlation function directly in the time domain comprise variations on this standard transversal filter implementation [1] [2J. To reduce the cost and complexity a commonly used variation on the standard implementation is to employ a single multiply-accumulator, which replaces the array of N multipliers and the accumulator. Calculation of products is time-shared in the multiply-accumulator for each time shift during the evaluation. Where high sample rates are not
required te bottleneck formed by time sharing of the multiplier can be overcome However, as reduction in the acquisition time becomes a requirement the time sharing method becomes unsuitable and multiple multipliers must be incorporated A development of the standard shift-multiply-add architecture is to compute values for each time shift in parallel.
This reduces the need for a series of N shift registers for the incoming data but does requires that one of the two sequences is known and parallel loaded into static registers for multiplication with the incoming sequence. Each data sample of the incoming series is multiplied in parallel with the known or reference data. The resulting products are then held in registers and shifted before summation with the product of the next sample. The use of variations on such serial-parallel correlators is widespread in applications such as the alignment of spreading sequences m code division multiple access (CDMA) channels. The drawback of such architectures is that the correlation length is limited to 2N-1. Longer series may be correlated by decomposing the reference data into sets of length N and forming the correlation by the summing of successive correlations with each reference signal subset. In this case
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additional memory will be required to store the extended reference signal along with the full sampled data signal Thus the parallel correlator is dedicated to data series of length N and its application to processing data of arbitrary lengths results in inefficiencies and additional complexity to the parallel architecture.
To summarise the limitations of hitherto correlators employing the shift-multiply-add architecture, the complexity of the system is dependent on the length of the sequences to be correlated which places restrictions on the length of data series which may be evaluated If a dedicated correlator is to be used to correlate time series of a length for which they were not designed, additional memory to hold both series will be required and the efficiency of the system greatly reduced. For a data series of the length N the delay in forming the correlation function after receiving the last data sample, will always be N times the sample rate, even when hitherto parallel architectures are employed In addition the reference signal must be known and loaded in to the correlator static registers before computation of the correlation function may begin.
In comparing the data required of the correlator hardware employed in industrial applications it becomes apparent that the evaluated data is often required in different forms In many cases only a single value of the computed correlation function is required and hardware exists to efficiently compute this. In the same way the full correlation function may be required and evaluated as described above It is, however, often necessary to only obtain a section of the full correlation function or time windowed correlation function such as in the case of system identification, where the impulse response is evaluated through the correlation of the input and output signals [3]. The time windowed correlation function may be evaluated after the full correlation function has been computed, as would be the case where the FFT method is employed, or dedicated hardware architecture may be designed to evaluate the time windowed function directly In view of the foregoing it is the object of the present invention to provide an improved parallel digital correlator
capable of evaluating the time windowed correlation function of real-time sampled data series of arbitrary length and form with minimal complexity and acquisition time The present invention provides an improved digital correlator for measuring the amount of agreement between signals of arbitrary length and form. The invention provides a correlator architecture comprising: a plurality of Ad shit registers to store the first of the sampled data series. a plurality of Al shift registers to store the second of the sampled data series. a plurality of 2M-l multipliers to form to product between corresponding series samples. a plurality of 2lvl-l accumulators for the summation for successive time shifts, a plurality of 2AI-l registers to hold the formation of the time windowed correlation function;
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In the preferred arrangement of the invention the plurality of shift registers to receive the first of the two signals is cascade connected through which the data enters at one end and is clocked serially through each of the M registers in turn at each sample interval. The second plurality of shift registers to receive the second of the two signals is in the same way cascade connected, data enters at one end and is clocked serially through each of the M registers at each sample interval.
The first register of each of the two series of M shift registers is connected in parallel to M of the 2M- ! multipliers, such that the central multiplier may be connected to the first registers of each register series. The remaining M-I registers of each series are individually connected to each multiplier to which the first register of the opposing series is connected. In such an arrangement, the product is taken in each multiplier of the content of the first register in one series and the content of one of the shift registers in opposing series.
The output from each multiplier is connected to the corresponding accumulator rom the series of 2M-I accumulators.
The output of each accumulator is connected to the corresponding register to hold the time windowed correlation function sample point.
The output of the registers holding the time windowed correlation function are connected to the corresponding accumulator for successive summing of correlation values.
The invention will now be described by way of example with reference to the accompanying Drawings of which: FIG 1. is a block diagram of the serial-parallel correlator system architecture : FIG. 2a. Shows the form of the output from the application of two data series to the correlator architecture in FIG.
1. to from the full correlation function of the two data series.
FIG 2b. Shows the form of the output from the application of two arbitrary length data series to the correlator architecture in FIG I to form the time windowed correlation function of the two data series located about the centre of the full correlation function of the series.
FIG. 1. illustrates the parallel correlator architecture in which data series. S'/ and enter the correlator serially and thus may either be sampled in real-time or be known sample data and stored in memory. Sin) enters the corresponding series ouf M shift registers 10 and Sin) enters the corresponding series of M shift registers 11. The series S, (n) and Sin) shifts one place through each of the cascaded registers 12 during each sample instant. At each cycle the data sample of. S'/ ; ; and // held in the first register of each series is multiplied in parallel in multipliers 13 with all samples in the opposing data series and summed in accumulators 14 with 1e calculated calues from the previous time shift held in memory 15.
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Initialisation of the correlator is accomplished by setting all registers to zero. This may be done without introducing time redundancy as the first samples of Sin) and S2 (n) enter the first of the appropriate registers 10 and 11, in which case all but the first registers in each set are cleared. Once the final data samples of the data series enters the correlator the final values of the correlation function are summed and the time windowed correlation function read from the correlator If the correlator is to be employed in calculating the time average of several correlations the registers holding the time windowed correlation function 15 are not cleared and thus sum with the following correlation If time averaging of successive correlations is not required the appropriate registers may be cleared Where the length of the data series to be correlated is known the architecture may be designed to evaluate the correlation function over its full length, in which case no time windowing will be applied and the full correlation function formed. This will result in a correlator architecture requiring 2N-1 multipliers and accumulators and 4N-1 registers to retain the input data and correlation function The complexity of such a correlator is comparable with hitherto parallel correlators, however, the system also enables the evaluation of the full correlation function of any length sequence less than N and the time windowed function for series greater than N. In addition the function will always be evaluated immediately following the last samples entering the correlator.
Where the length of the data sequence is arbitrary but the correlation peak is expected to always fall between certam limits such as direction finding on radar or sonar, the time windowed correlation function is ideal. In the present invention the reduced complexity and acquisition time makes such as system more efficient and economical. In general the correlation peak in such an application will always be located near the centre of the correlation function
enabling the appropriate window to be applied and the correlator designed accordingly. Where the correlation peak is located elsewhere. the application of a time lead or lag to the input series enables the evaluation of the time windowed correlation function possible over any area FIG 2a illustrates the formation of the full cross-correlation function for sampled data series n) and Y (n) where
the length N of the data is equal to 4. As the first data samples X (l) and Y enter the respective registers 20'and 21 all other registers are set to zero thus initialising the system while the correlation is in progress and reducing time redundancy. The two samples V (I) and Y and therefore all other products equal zero The product Y (l) Y (1) is stored in the appropriate register of 22 and will form the central point of the correlation function On the second sample instant the following two data samples AU (2) and Y (2) enter the respective shift registers 20 and 21. At the same time X (l) and Y are shifted to the next register in the appropriate series. The new data samples arc in the same way multiplied in parallel with the samples in the opposing series. The product of each sample point is sununed with the cumulative value from previous products and stored in the correlation function registers 22.
In the same way the third samples enter the appropriate registers as the preceding data points shift through the series The cumulative value of each correlation point is summed with the new product of the corresponding data samples
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The final data samples enter the correlator and arc processed in the same way forming the full correlation function for those data series. There is no delay between the final sample entering the correlator and the processing with all other data points to evaluate the full correlation function. Hence the full correlation function is evaluated after N clock samples. or immediately after the final sample enters the correlator and is processed in parallel with all opposing data points.
In the same way the full correlation function of any data series with a length less than that of the above data series,
may be evaluated in the same architecture and completed in K clock cycles, where K is the length of the arbitrary length data sequence to be evaluated.
FIG. Zb illustrates the time windowed correlation function for an arbitrary length series (n) and Y where A < K In this case the time windowed function is located about the centre of the full correlation function. As successive
samples enter the correlator the time windowed fucntion is evaluated in the same way as above with the products of each opposing series summing with the cumulative value of the point in the correlation function. By applying a time lag or lead to either of the two signals before commencing the evaluation the time wmdow may be located over a different section of the full correlation function.
To summarise the evaluation of data series within the present invention. series may in all cases be of dissimilar length and where data series are dissimilar it is the longer of the two series which determines the type of correlation function which is formed. Where the length N of the data series are equal to the number of registers to hold the series the full correlation function will be formed in the 2N-l registers holding the evaluation function. Where data series are of a length less than the number of registers holding the incoming series, the zero padded full correlation function will be formed in the appropriate registers. Where the data series are of a length greater than the registers required to hold the incoming series the time windowed series will be formed in the appropriate registers.
The foregoing is intended to be illustrative only and it will be apparent to those skilled in the art that numerous alternative embodiments of the above description may be devised without departing from the spirit and scope of the following claims and the equivalents References
Tung-Sang . Kun-Wah Yip and Chin-Longc C. . 0. . vol 47. pp. 1542-1547.
Dec. 2000 irmos. 7e Digital Signal Processing Databook, pp. 5-177, Inmos Ltd. 19S9. l31 D. Graupe, c. S. pp. 5-90. Van strand Reinhold Company, ew York 1972.
Claims (7)
1. A correlation architecture for determining a measure of the similarity between data of arbitrary length and form comprising a plurality of shift registers for receiving the first of the series to be evaluated, a second plurality of shift registers for receiving the second of the series to be evaluated. a plurality of A+ multipliers to form to product between corresponding data samples in said data series to be evaluated. a plurality of M accumulators for the summation of corresponding data points in said data series to be evaluated and registers to storing the cumulative points of the item windowed correlation function for successive time shifts. a plurality of. W registers to hold the cumulative values for the formation of the time windowed correlation function sunned in said accumulators
2. The correlation device in claim 1 wherein the said data samples stored in the first plurality of said shift registers are used in the formation of the full or time windowed correlation function
3. The correlation device in claim 1 where the said data samples stored in the second plurality of said shift registers are used in the formation of the time windowed or full correlation function.
4. The correlation device in claim 1 wherein the plurality of said multipliers are used to form the product of corresponding said data samples
5 The correlation device in claim 1 wherein the plurality of said accumulators are used in evaluating the cumulative value of each sample of the full or time windowed correlation function
6 The correlation device in claim 1 wherein the plurality of said registers are used to store the cumulative value of samples of the time windowed or full correlation function evaluated by said accumulators
7. The correlation device in claim 1 wherein the data samples entering the first of said shift registers may be sampled in real-time or held in memory 8 The correlation device in claim 1 wherein the data samples entering the second of said shift registers may be sampled in real-time or held in memory
'). The correlation device in claim 1 wherein the full or time windowed correlation function will be fully evaluated after K'times the sample rate of the said system. where K is the length of the data series to be evaluated 10. A correlation device as in claim I wherein the plurality of said registers to store the samples of the first series are equal to K. the length of the first of the series to be evaluated 11. The correlation device in claim 141 wherein the plurality of said registers to store the samples of the second series arc equal to K the length of the second of the series to be evaluated 12. The correlation device in claim 10 wherein the plurality of said multipliers to form the product between corresponding samples is of length 2K-1 13 The correlation device in claim 10 wheres the plurahty of said accumulators to evaluate the cumulative value
for each sample of the correlation function is of length 2K-1 14 The correlation device in claim 10 wherein die plurality of said registers to store the correlation function is of length 2K-1 and store the full correlation function for the series to being evaluated.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB0126238A GB2381607A (en) | 2001-11-01 | 2001-11-01 | Serila-parallel correlator architecture |
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| GB0126238A GB2381607A (en) | 2001-11-01 | 2001-11-01 | Serila-parallel correlator architecture |
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| GB0126238D0 GB0126238D0 (en) | 2002-01-02 |
| GB2381607A true GB2381607A (en) | 2003-05-07 |
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| GB0126238A Withdrawn GB2381607A (en) | 2001-11-01 | 2001-11-01 | Serila-parallel correlator architecture |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7826184B2 (en) | 2006-12-28 | 2010-11-02 | General Electric Company | Series arc fault interrupters and methods |
| US8054591B2 (en) | 2008-07-24 | 2011-11-08 | General Electric Company | Arc detection using discrete wavelet transforms |
| US8159793B2 (en) | 2008-12-22 | 2012-04-17 | General Electric Company | Arc detection using detailed and approximate coefficients from discrete wavelet transforms |
| US8170816B2 (en) | 2008-12-29 | 2012-05-01 | General Electric Company | Parallel arc detection using discrete wavelet transforms |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4347580A (en) * | 1980-07-21 | 1982-08-31 | The United States Of America As Represented By The Secretary Of The Navy | Array convolver/correlator |
| US4593378A (en) * | 1982-02-15 | 1986-06-03 | Secretary of State | Digital signal processor |
| US4809210A (en) * | 1984-12-17 | 1989-02-28 | Secretary Of State For Defence In Her Britannic Majesty's Government Of The United Kingdom Of Great Britain And Northern Ireland | Multichannel digital signal correlator or structurator |
| EP0692720A1 (en) * | 1994-07-15 | 1996-01-17 | Hughes Missile Systems Company | Ramp weighted correlation with oversampling |
-
2001
- 2001-11-01 GB GB0126238A patent/GB2381607A/en not_active Withdrawn
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4347580A (en) * | 1980-07-21 | 1982-08-31 | The United States Of America As Represented By The Secretary Of The Navy | Array convolver/correlator |
| US4593378A (en) * | 1982-02-15 | 1986-06-03 | Secretary of State | Digital signal processor |
| US4809210A (en) * | 1984-12-17 | 1989-02-28 | Secretary Of State For Defence In Her Britannic Majesty's Government Of The United Kingdom Of Great Britain And Northern Ireland | Multichannel digital signal correlator or structurator |
| EP0692720A1 (en) * | 1994-07-15 | 1996-01-17 | Hughes Missile Systems Company | Ramp weighted correlation with oversampling |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7826184B2 (en) | 2006-12-28 | 2010-11-02 | General Electric Company | Series arc fault interrupters and methods |
| US8054591B2 (en) | 2008-07-24 | 2011-11-08 | General Electric Company | Arc detection using discrete wavelet transforms |
| US8159793B2 (en) | 2008-12-22 | 2012-04-17 | General Electric Company | Arc detection using detailed and approximate coefficients from discrete wavelet transforms |
| US8170816B2 (en) | 2008-12-29 | 2012-05-01 | General Electric Company | Parallel arc detection using discrete wavelet transforms |
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| Publication number | Publication date |
|---|---|
| GB0126238D0 (en) | 2002-01-02 |
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