GB2380027A - Single and multiple channel memory detection and sizing - Google Patents

Single and multiple channel memory detection and sizing Download PDF

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Publication number
GB2380027A
GB2380027A GB0225877A GB0225877A GB2380027A GB 2380027 A GB2380027 A GB 2380027A GB 0225877 A GB0225877 A GB 0225877A GB 0225877 A GB0225877 A GB 0225877A GB 2380027 A GB2380027 A GB 2380027A
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group
channel
memory
counter
answered
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GB2380027B (en
GB0225877D0 (en
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Lynda M Wirt
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Intel Corp
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Intel Corp
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Priority claimed from US09/080,872 external-priority patent/US6003121A/en
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44Arrangements for executing specific programs
    • G06F9/445Program loading or initiating
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/06Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646Configuration or reconfiguration

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Stored Programmes (AREA)

Abstract

A method for BIOS code for detecting and grouping memory devices connected to one or more memory channels, comprising reading characteristics of a memory device (414) and if the characteristics have not been previously read, then programming device ID and group ID registers based upon a device counter and a group counter, respectively (422). Figs 5-7 show other embodiments.

Description

<Desc/Clms Page number 1>
Singte and Muitiptc Channel Memonr Detection an (l Sizing Field of Invention The present invention relates to a method for detecting and grouping memor. devices according to their characteristics during boot-up of a computer system.
Background To increase system memory performance in computers. memory devices with interleaved banks of memory cells can be employed. For example, Rambus Inc. provides technology for an integrated memory device, the Direct RDRAM\ (Rambus dynamic random access memory), employing interleaved banks of memory cells. along with a protocol for connecting a number of such memory devices to a memory channel. called a Direct Rambus'Channel or Direct RDRAM Channel. A plurality of such memory devices are provided in a module, called the Direct RambusTM RIMM module (Rambus in-line memory module), which may contain one or more Direct RambusTM Channels. Direct RambusTM and Direct RDRAMTM are trademarks ofRambus Inc..
Mountain View, CA.
It can be desirable for a memory system to comprise RDRAMs with varying characteristics. During boot-up of a computer system, the BIOS (basic input output system) code needs to determine how much memory is available for use. For Direct RDRAMs, their addresses need to be programmed, and the memory controller needs to provide efficient memory accesses to the various Direct RDRAM devices.
Summary of the Invention According to a first aspect of this invention there is provided a method as claimed in claim 1 herein.
According to a second aspect of this invention there is provided a computer- readable device as claimed in claim 5 herein.
Brief Description of the Drawings Fig. I is a high-level diagram of Direct Rambus RIMM modules.
Fig. 2 is a high-level diagram of Direct Rambus RIMM modules with multiple channels and connected to a memory controller.
Fig. 3 is a high-level diagram of a two-channel Direct Rambus module with RDRAMs having varying characteristics on the channels.
<Desc/Clms Page number 2>
Fig. 4 is a flow diagram for BIOS code for detecting and grouping memory for a sonie-channel Direct Rambus module. i'tg. ts a tlow diagram for BIOS code for detecting and grouping memory for a multi-channel Dtrect Rambus RIMM module where all memory devices on any given channel have the same characteristics.
Fig. 6 is a flow diagram for BIOS code for detecting and grouping memory for a multl-channel Direct Rambus R1MM module where all memory devices on any given channel have the same characteristics.
Fig. 7 is a flow diagram for BIOS code for detecting and grouping memory for a multi-channel Direct Rambus RJMM module with memory devices having varying characteristics.
Detailed Description of Embodiments Fig. I provides examples of RJMM modules 110 having one, two, and four Direct RDRAM Channels. RIMM modules with multiple Direct RDRAM Channels have Memory Repeater Hubs (MRH) 120 as shown in Fig. 1. Individual RDRAM devices 130 are indicated for the two-channet RJMM module only. The physical layer 140 of the Direct RDRAM Channels are indicated as shown, where terminators 150 provide proper termination for the Direct RDRAM Channels.
Currently, each RDRAM Channel may contain up to 32 RDRAMs. More than one PI MM module I 10 may be connected to memory controller 210, as shown in Fig.
2, via bus 220. Individual RDRAM devices have different characteristics, such as memory size, number of banks, page size, number of bank address bits, number of row address bits, number of column address bits, etc. For example, Fig. 3 is a high level diagram of a two-channel RIMM module with RDRAM devices having varying characteristics on each Direct RDRAM Channel. An EEPROM (electrically erasable programmable read only memory) 310 may be present with stored data regarding the various characteristics of RDRAMs present on an RJMM module. If no EEPROM is present, each RDRAM device on a RJMM module must be individually read to obtain its characteristics.
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To provide efficient memory accesses via a memory controller to Direct RD R.'\ \ 1s ha\ ing varying charactaistics. the BIOS should et'ficiently detect. assign dc\ cc I Ds. and group according to characteristics various RDRAMs on one or more modules with one or more Direct RDRAM Channels.
Fig. 4 is a flow diagram for BIOS code to provide device identifIcation numbers for Direct RDRAMs connected to a single Direct RDRAM Channel and to group the RDRAMs according to their characteristics. In one embodiment, the maximum number of RDRAM devices to a group are four. and there is a maximum of eight groups in a memory channel. The BIOS code is firmware, and may be stored in such devices as EEPROM or flash memory. The BIOS code causes a processor to communicate with a memory controller, which communicates with system memory via a bus. In other embodiments, DRAM devices other than RDRAM devices may be employed provided individual DRAM devices can be identified by an address.
In one embodiment, to initialize a device once it is ready, the system BIOS should program the Initialization Control Management (RICM) register in a memory controller. In some embodiments, all Direct RDRAM devices respond to IF (hex) in the Device Sequence Address before they have been assigned a device address by the system BIOS. Once the RICM register is programmed for a particular device, the Initiate Initialization Operation (110) is started. This command sends to the Direct RDRAM devices all data programmed in the RICM register and the Direct RDRAM devices return various data to the Device Register Data (DRD) register in the memory controller. The BIOS code can then read the DRD register and program all necessary PCI (Peripheral Component Interconnect) Configuration registers. The PCI Configuration registers reside in the memory controller. The device ID and group ID are then assigned, as described in more detail below. The device ID and group ID are stored in registers residing in the memory controller.
In step 402 it is determined whether a memory module is present. If so, then a channel identifier is stored in a channel address field. step 404. The channel address
<Desc/Clms Page number 4>
t) veld is stored in a register located in the memory controller. Refresh is disabled in step 406 The group counter and device counter are initialized to zero in step 40S. The RDRAM de\ices are initialized in step 410. In step 4 12 the HO bit is set to zero by the memory controller to indicate that the RDRAM device is ready. The HO bit is in PCI Configuration space, I. e.. a register in the memory controller. Direct RDRAM device characteristics are then read dunng step 414 and the PCI Configuration registers are then modified according to the data read. If the RJMM module contains EEPROM storing the RDRAM characteristics, then step 414 is modified to where the device characteristics are read directly from the EEPROM using serial presence detect. The remaining steps are directed toward properly grouping the RDRAM devices, as described below.
Step 418 determines whether the device characteristics read during step 414 have previously been read by the BIOS during memory configuraton. If the device characteristics have not been previously read, then in step 422 the RDRAMs device and group IDs are programmed based upon the current device and group counters, and the device counter is incremented by four and the group counter is incremented by one in step 424.
If, however, in step 418 it is determined that the device characteristics have previously been read, then step 420 determines whether the group having those device characteristics is full, i. e. , already has four members. If the group is full, then step 438 determines whether there are other empty groups with the same characteristics, and if so, then an empty group is chosen and step 420 is repeated. If step 438 determines that there are no other empty groups with the characteristics, then step 440 determines whether the maximum number of groups have been reached. If so, then in step 442 the device is skipped and flow control continues with step 434. If there are no other empty groups and the maximum number of groups have not been reached, then in step 426 the RDRAM device and group IDs are programmed based upon the current device and group counters. and these counters are incremented as indicated in step 428. If in step
<Desc/Clms Page number 5>
420 it is determined that the group is not full. then in step 430 the RDRAM group [D
is programmed to have the same ID as that group having the same characteristics, and in I ri 1 step 432 the Je : \ ice 10 for the RDRAM is set equal to one more than the highest device ID of the matching group. Other embodiments may have group sizes not equal to four.
The above described steps therefore perform grouping of a RDRAM. Step 434 determines whether there are any more RDRAM devices on the Direct RDRAM Channel, and if so. control is brought back to step 412. If not. then refresh is enabled.
step 436. and the grouping of the RDRAM is finished.
Fig. 5 is a flow diagram for BIOS code to assign device IDs to RDRAMs and to group them according to their characteristics for the case in which a RJMM module may have more than one Direct RDRAM Channel, but in which all the RDRAMs on any given channel have the same characteristics. The initial steps in Fig. 5 outside dashed area 502 are similar to steps 402-416 of Fig. 4, except that step 504 detects whether an MRH is present, and if not, then step 506 indicates that the steps of Fig. 4 are performed. The presence of an MRH implies a RJMM module with more than one Direct RDRAM Channel.
In addition to device and group counters, an embodiment according to Fig. 5 also comprises a channel counter and a member counter. The member counter limits the number ofuseable RIMMs on a memory channel to 32, although other embodiments may be limited to different values. If in step 508 it is determined that the characteristics of the newly read RDRAM have not been previously read, then the channel, group and device IDs are programmed according to the present values of the channel, group, and device counters, respectively, in step 510, and the group, device, and member counters are incremented by one in step 512. If, however, it is determined in step 508 that characteristics of the newly read RDRAM have been previously read, then step 514 is performed. If in step 514 it is determined that the device counter is 32 or if the end of the Direct RDRAM Channel has previously been reached, then step 516 resets the group, device. and member counters to zero, and step 518 increments the channel counter by one.
<Desc/Clms Page number 6>
[f step 5 14 is answered in the negative then in step 520 it is determined whether the member counter is less than a group size. \1, hlch for the embodiment of Fig 5 ts 8 [ :'the member counter is less than S. then step 522 programs the channel [D and
group ID registers to equal that of the most recent previously read group of devices matching the characteristics of the newly read RDRAM, step 524 programs the device ID register using the device counter, and in step 526 the device and member counters are incremented If. however, the member counter is equal to 8. then steps 528-532 are performed as indicated in Fig. 5. Note that after steps 534 or 518. step 536 determines whether there is another channel present, and if so, control is brought to step 538.
Fig. 6 is a flow diagram for BIOS code for the multiple-channel case in which there is no mixing of memory devices within a channel. Also, a serial presence detect (SPD) method is used, where an EEPROM on the Direct RIMM module provides information concerning the RDRAM devices on the RJMM. Consequently, in step 602, the device characteristics are read from the EEPROM rather than directly from the RDRAM devices. In step 604, it is determined whether the device counter equals 32 or if the end of a channel has previously been reached. If step 604 is answered in the affumative, then steps 606 and 608 are performed to reset the group, device and member counters to zero and to increment the channel counter by one. If step 604 is answered in the negative, then step 610 determmes whether the device counter is equal to various multiples of the group size, which in the embodiment of Fig. 6 is 8, 16, or 24.
The remaining steps 612-620 following step 610 perform the proper counter increments and resets needed to group the RDRAM devices into groups of size 8.
Fig. 7 is a flow diagram for BIOS code for the multiple-channel case in which various memory devices with varying characteristics may be present on the same memory channel. The embodiment of Fig. 7 limits the maximum number of useable RDRAMs per group to 8, for a total of 4 useable groups for any single channel.
However, other embodiments may be limited to different values. Step 702 determines
whether the characteristics of the newly read RDR.. \1 have already been read for other RDRAMs devices on the same channel. If not, then step 704, along with the steps 706
<Desc/Clms Page number 7>
and 708. limit the number of useable groups on a single channel to 4. [f the number of groups is less than.. L then step 710 programs the channel ID, group ID. and device ID registers based upon the corresponding counters, and step 712 increments the device counter by 8. and increments the group and member counters by one.
Step 714. followed by steps 716 and 718. limit the useable RDRAM to 32 members for each channel. If the characteristics of the newly read RDRAM match characteristics that have already been read. and if the number of RDRAM devices on a channel does not exceed 32 and if the last RDRAM device on the memory channel has not been reached, then step 720 determines whether the device ! D register with the
lar largest value among the group of RDRA-Ms matching the newly read characteristics is equal to multiples of one less the group size, which is seven for this embodiment. If step 720 is answered in the negative, indicating that the previously read group is not full, then the following steps 722-726 group the newly read SORGT with that group and update the appropriate counters. If step 720 is answered in the affirmative, and if step 728 is answered in the negative, then the number of groups on the memory channel have not exceeded 4 and steps 730 and 732 program the channel ! D, group ID, and device 10 based upon the appropriate counters. Steps 728 and 734 limit the useable number of groups on a memory channel to 4.
It is to be understood that some of the various registers described in the disclosed embodiments and in the claims below need not be physically distinct from each other. For example, a device ID register and a group ID register for a memory device may actually be distinct fields within one physical register. Various modifications may be made to the disclosed embodiments without departing from the scope of the invention as claimed below.

Claims (9)

  1. CLAIMS : 1. A method for grouping memory devices connected to at least one memory channeL the method comprising : (i) reading characteristics of a memory device connected to the at least one memory channel : and (ii) determining whether the characteristics have already been read for another memory device connected to the same memory channel to which the memory device is connected.
  2. 2. The method as set forth in claim 1, further comprising: (iii) if step ii is answered in the negative, then determining whether a group counter indicates k, where k is the maximum number of groups per memory channel ; (iv) if step iii is answered in the positive, then not grouping the memory device and determining if another memory device is connected to the memory channel to which the memory device is connected; (v) if in step iv it is determined that another memory device is not present on the memory channel, then resetting the group counter, a device counter, and a member counter to zero and incrementing a channel counter by one ; and (vi) if step iii is answered in the negative, then programming a channel ID register, a group ID register, and a device ID register based upon the channel, group, and device counters, respectively, and incrementing the device counter by g, where g is a group size, and incrementing the group and member counters by one.
  3. 3. The method as set forth in claim 2, further comprising: (vii) if step ii is answered in the positive, then determining whether the member counter indicates a member size d or whether all memory devices connected to the memory channel to which the memory device is connected have had their characteristics read;
    <Desc/Clms Page number 9>
    (vii) if step vii is answered in the positive. then resetting the group. device. and member counters to zero. incrementing the channel counter by one. and determining if another memory channel is present, and (ix) if step vii is answered in the negative, then determining whether a indicates ng-t.
    n= l. t. \, where tV is such that 'g = d. where a is the largest device 10 among a group x of memory devices with characteristics matching the characteristics of the memory device, the group x being the most recently read group of memory devices
    having the characteristics.
    1
  4. 4. The method as set forth in claim 3, further comprising : (x) if step ix is answered in the negative, then setting the channel ID register to c and the group register to m, where c and m are the channel ID and group ID of group x, respectively, setting'the device ID register to a+ I where a is the maximum device \ ID among group x and incrementing the member counter by one ; (xi) if step ix is answered in the positive, then determining whether the group counter indicates Af. where M is a maximum number of groups per channel; and (xii) if step xi is answered in the negative, then programming the channel ID, group 10. and device ID registers based upon the channel, group, and device counters, respectively, incrementing the group and member counters by one, and incrementing the device counter by g.
    1
  5. 5. A computer readable device with stored BIOS code, the BIOS code causing at least one processor to perform : (i) reading characteristics of a memory device connected to the at least one memory channel; and (ii) determining whether the characteristics have already been read for another memory device connected to the same memory channel to which the memory device is connected.
    <Desc/Clms Page number 10>
  6. 6. The computer readable device as set forth in claim 5, further comprising : (iii) if step ii is answered in the negative. then determining whether a group counter indicates k. where k is the maximum number of groups per memory channel.
    (iv) if step iii is answered in the positive. then not grouping the memory device and determining if another memory device is connected to the memory channel to which the memory device is connected : (v) if in step iv it is determined that another memory device is not present on the memory channel, then resetting the group counter, a device counter, and a member counter to zero and incrementing a channel counter by one, and
    (vi) if step iii is answered in the negative, then programming a channel 1D register. a L group ! D register, and a device ID register based upon the channei, group, and device counters, respectively, and incrementing the device counter by g, where g is a group size, and incrementing the group and member counters by one.
  7. 7. The computer readable device as set forth in claim 6, further comprising : (vii) if step ii is answered in the positive, then determining whether the member counter indicates a member size d or whether all memory devices connected to the memory channel to which the memory device is connected have had their characteristics read; (viii) if step vii is answered in the positive, then resetting the group, device, and member counters to zero, incrementing the channel counter by one, and determining if another memory channel is present; and (ix) if step vii is answered in the negative, then determining whether a indicates nu-1,
    n=l, 2,..., Nt where N is such that Vg = d, where a is the largest device ID among a group x of memory devices with characteristics matching the characteristics of the memory device, the group x being the most recently read group of memory devices having the characteristics.
  8. 8. The computer readable device as set forth in claim 7, further comprising:
    <Desc/Clms Page number 11>
    (x) if step ix is answered in the negative. then setting the channel ID register to c and the group register to m. where c and m are the channel 10 and group ID of group x. respectively. setting the device ! D register to all where a is the maximum device ID among group x, and incrementing the member counter by one ; (xi) if step ix is answered in the positive, then determining whether the group counter- indicates M. where Mis a maximum number of groups per channel ; and (xii) if step xi is answered in the negative, then programming the channel ID, group ID, and device ID registers based upon the channel, group, and device counters. respectively, incrementing the group and member counters by one. and incrementing the device counter by g.
  9. 9. A computer program ccnprising computer program code means adapted to perform all the steps of claim 1 when that program is run on a computer.
GB0225877A 1998-05-18 1999-03-03 Single and multiple channel memory detection and sizing Expired - Fee Related GB2380027B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/080,872 US6003121A (en) 1998-05-18 1998-05-18 Single and multiple channel memory detection and sizing
GB0027775A GB2353884B (en) 1998-05-18 1999-03-03 Single and multiple channel memory detection and sizing

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GB0225877D0 GB0225877D0 (en) 2002-12-11
GB2380027A true GB2380027A (en) 2003-03-26
GB2380027B GB2380027B (en) 2003-06-04

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GB0225877D0 (en) 2002-12-11

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