GB2376082A

GB2376082A - Attenuating structures for integrated optical devices

Info

Publication number: GB2376082A
Application number: GB0113311A
Authority: GB
Inventors: Ian Edward Day
Original assignee: Bookham Technology PLC
Current assignee: Lumentum Technology UK Ltd
Priority date: 2001-06-01
Filing date: 2001-06-01
Publication date: 2002-12-04
Also published as: WO2002097520A1; GB0113311D0

Abstract

An integrated optical device has a a waveguide 18 whose optical mode 22 is modulated by a PIN diode defined across the waveguide, the diode being defined by an area of p-type doping, 24 to one side of the waveguide and n-type doping 26 to the other, the separation of the n-type doping from the waveguide, 30 being greater than the separation of the p-type doping from the waveguide 28. It is preferable for the n-type diode rule to be at least 1.5 times the p-type diode rule, and more preferably at least twice. In this way, the best advantage of the effect is obtained. A ratio of between three and four times offers the best results. A ratio of four times, or a total n-type and p-type diode rule of less than 40žm is preferred in order to limit the size of the intrinsic region and hence its resistance.

Description

ATTENUATING STRUCTURES FOR INTEGRATED OPTICAL DEVICES The present invention relates to attenuating structures for integrated optical devices.

Integrated optical devices are used in the handling and processing of optical signals. One way of providing an integrated optical device is to form a waveguide on a suitable optical substrate, such as a rib waveguide on a silicon-on-insulator (SOI) substrate.

It is often required to attenuate the signal, such as (for example) in WDM (wavelength division multiplexing) or other multiplexed applications where the individual signal strengths must be adjusted prior to multiplexing to ensure that the output power of each signal is normalised to the same level.

Attenuation of the signals is normally by the free carrier dispersion effect, in which charge carriers (electrons and holes) are injected into the waveguide region. As the charge carrier density increases, so does the attenuation of the optical signal. This can be achieved by defining a PIN diode (i. e. one having p-type and n-type doped regions either side of an intrinsic or substantially undoped region) across the waveguide. The optical mode will be placed in the intrinsic region to

avoid systematic loues due to the dopant concentration. When the diode is

forward biased, a cunent flows thereby creating a charge carrier concentration in the region of the optical mode This attenuates the mode, but on ! y when the diode is forward biassed thereby offering selectivity of attenuation.

The present invention is addressed at the problem of increasing the efficiency of such devices, such as by achieving the same level of attenuation but with less electrical power consumption. Reduced power consumption will reduce the thermal output of the device and allow greater levels of integration and/or lower power demands.

Historically, lower power consumption of integrated devices has been pursued very successfully by reducing the dimensions of structures. This reduces their physical volume and thus the number of charge carriers involved. A smaller current is thus needed to move those carriers. Typically, devices have been designed with dimensions as small as the fabrication method allows. The present invention approaches the problem in a different manner.

It therefore provides an integrated optical device with a waveguide whose optical mode is modulated by a PIN diode defined across the waveguide, the diode being defined by an area of p-type doping to one side of the waveguide and n-type doping to the other, the separation of the p-type doping from the waveguide being greater than the separation of the n-type doping from the waveguide.

The separation between a doped area and the adjacent structure is often referred to as the "diode rule". There are other problems in reducing the p-type diode rule, in that dopant is more likely to fall in the volume carrying the optical mode and cause unintended attenuation. Thus, the present invention is in effect proposing an increase in the n-type diode rule, contrary to past progress in integrated devices.

The invention appears to work by exploiting a feature of PIN diodes hitherto seen as undesirable, i. e. that the charge carrier concentration across the intrinsic region is not uniform but in fact shows a distinct gradient. Her ! et ("The forward characteristic of silicon power rectifiers at high current densities", A. Herlet, J Solid State Electr, vol 11) ascribes this to the greater mobility of electrons as opposed to holes.

It is preferable for the n-type diode rule to be at least 1.5 times the p-type diode rule, and more preferably at least twice. In this way, the best advantage of the effect is obtained. We have found that a ratio of between three and four times offers the best results.

The intrinsic region is resistive in nature and thus as it grows, so does the power consumption. Thus, a ratio of four times, or a total p-type and n-type diode rule of less than 40/-im is preferred.

Embodiments of the present invention will now be described with reference to the accompanying figures, in which; Figure 1 shows charge carrier concentration across a PIN junction; Figure 2 shows a section through a PIN junction according to the present invention; Figure 3 compares simulated and experimental plots of attenuation against varying n-and p-type diode rules ; and Figure 4 shows the power consumption of two experimental designs of diodes with varying n-type diode rule.

Figure 1 shows the concentration of charge carriers across a PIN junction.

It can be seen that in the p-type region the hole concentration is high and the

electron concentration is predictably low, the opposite holding in the n-type region. In the intrinsic region, the concentration of the two carners is of course substantially equal. However, the charge carrier concentration In the intrinsic region of the edge of the p-type region is distinctly higher than that of the edge of the n-type region, bearing in mind that the scale on Figure 1 is logarithmic. As mentioned earlier, it is thought that this is due to the greater mobility of electron carriers as opposed to hole carriers.

Figure 2 shows a section through a PIN diode modulator arranged to take advantage of this effect. A silicon-on-insulator (SOI) device 10 has a silicon substrate 12 beneath an oxide-insulating layer 14, over which is a layer 16 of silicon. A rib 18 is formed in the silicon layer, and the whole device is usually covered with an insulating oxide layer 20. Thus, the upper and lower oxide layers 20,14 provide vertical confinement of an optical mode 22, whilst the rib 18 provides lateral confinement. With appropriate selection of dimensions, it is possible to arrange for a single mode to be directed by a rib 18.

In order to modulate the intensity of the mode 22, i. e. selectively attenuate it, a PIN diode structure is defined by diffusing dopants into the layer 16 to form a p-doped area 24 and an n-doped area 26, one either side of the waveguide 18. The p-doped area 24 is separated from the edge of the waveguide 18 by a distance of 28 which is the p-diode rule, whereas the n-doped region 26 is separated from the edge of the waveguide 18 by a distance 30 which is the n-diode rule.

According to the invention, as shown, the p-doped area 24 is relatively closer to the waveguide 18 than the n-doped area 26. An alternative way of seeing this is that the waveguide 18 is positioned off-centre between the two doped areas 24,26 so that the optical mode 22 lies in an intrinsic area of higher charge concentration.

Attenuation of the optical mode is related to the concentration of charge carriers through which it is required to pass, and therefore if a higher charge carrier concentration can be presented then the attenuation will be greater for the same device current, offering better efficiency. Alternatively, of course, a lower current can be passed through the diode whilst achieving the same charge carrier concentration in the vicinity of the optical mode, thereby obtaining lower power consumption and lower heat generation.

Figure 3 includes the results of simulations of asymmetric attenuator structures. The diode rule of the n-and p-doped areas is adjusted and the effect on attenuation shown. The attenuation values shown are at a standard current of 200mA. Other factors such as the remaining aspects of the diode design remain the same. It can be seen that increasing the n-diode rule and decreasing the pdiode rule both result in a greater attenuation at the same current.

Figure 3 also includes experimental verification alongside the simulated results. Whilst the absolute values of the attenuation obtained do differ, the trend lines are essentially the same. Again, in the experimental data, the attenuation shown is at 200mA and variations in diode design other than the particular diode rule are kept constant. The figure shows that the device efficiency can be improved through the use of an asymmetric structure, with improvements up to 20% available by increasing the n-diode rule to a figure within the range of 20- 30tam.

Asymmetric diodes reduce the current required for a given level of attenuation, which leads directly into a reduction in power consumption. This reduction in power consumption occurs until the total distance between the doped regions exceeds a particular value. Beyond this value, the intrinsic region becomes large enough to significantly increase the device resistance thereby increasing the overall power consumption. This is also shown in Figure 4.

Figure 4 is a plot of the overall power of the device as the n-type diode rule is varied. The power consumption shown is that necessary for an attenuation of 10dS with a fixed p-diode rule of 6. 0./im. It can be seen that improvements in power consumption occur until the n-diode rule exceeds about 25, um. It can be inferred that the total p-and n-diode rules should be maintained about 40/im, preferably about 30, um in order to minimise power consumption. Alternatively, the n-diode rule should be between 1.5 and 6 times the p-diode rule, preferably in the region of 3-4. Thus, by contradicting previous trends and positively increasing the n-diode rule, benefits can be obtained in terms of the power consumption and efficiency of the device.

11 will of course be apparent that many variations may be made to the abovedescribed examples without departing from the scope of the present invention.

Claims

CLAIMS 1. An integrated optical device with a waveguide whose optical mode is modulated by a PIN diode defined across the waveguide, the diode being defined by an area of p-type doping to one side of the waveguide and n-type doping to the other, the separation of the n-type doping from the waveguide being greater than the separation of the p-type doping from the waveguide.
2. An integrated optical device according to claim 1 in which the n-type separation is at least 1.5 times the p-type separation.
3. An integrated optical device according to claim 1 in which the n-type separation is at least twice the p-type separation.
4. An integrated optical device according to claim 1 in which the n-type separation is between three and four times the p-type separation.
5. An integrated optical device according to any one of the preceding claims in which the total of the n-type separation and the p-type separation is less than 40, um.
6. An integrated optical device substantially as herein described with reference to and/or as illustrated in the accompanying figures.