GB2374217A - A fast and accurate charge pump for PLLs or delay-locked loops - Google Patents
A fast and accurate charge pump for PLLs or delay-locked loops Download PDFInfo
- Publication number
- GB2374217A GB2374217A GB0108117A GB0108117A GB2374217A GB 2374217 A GB2374217 A GB 2374217A GB 0108117 A GB0108117 A GB 0108117A GB 0108117 A GB0108117 A GB 0108117A GB 2374217 A GB2374217 A GB 2374217A
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- transistors
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- switching
- circuit
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
- H03L7/0895—Details of the current generators
- H03L7/0896—Details of the current generators the current generators being controlled by differential up-down pulses
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
Abstract
A fast-acting charge pump is responsive to very short UP or DOWN pulses from a phase detector. To accelerate switching of the transistors P1 and P2 by a signal applied to the gate of P1, a complementary signal is applied through a capacitor 65 to the node A between the transistors P1 and P2. This provides fast turn-on and turn-off without waveform distortion of the output current pulse. The NMOS pull-down section N1, N2 has a similar speed-up capacitor 69. The charge pump may be used in frequency multiplying phase-locked loops or delay-locked loops for producing precisely delayed signals from an input clock signal. The loops may be used in processors or in their peripherals. The bias transistors 43, 45 set the amplitude of the output current pulses.
Description
TITLE : LOW INJECTION CHARGE PUMP The present invention relates to charge pumps which have particular utility in phase lock loop (PLL) and delay lock loop (DLL) circuits.
DISCUSSION OF THE RELATED ART
Phase lock loop and delay lock loop circuits are widely used for frequency multiplication and to produce precise delay signals : from an incoming dock signal. When such circuits are used in high speed environments such as serial communications, they often need very low phase offset between input and output signals. One common PLL architecture is shown in Figure 1 and is described in greater detail in the article "A Wide-Bandwidth Low-Voltage PLL for Power PCTM
Microprocessors"by Alvarez et aL, Journal of Solid-State Circuits, Vol.
30, No, 4 April 1995. The entire contents of this article are incorporated herein by reference. The PLL of Figure 1 relies on a charge pump 11
which receives UP 15 and DOWN 17 pulse signals from a phase detector 13 with the output of the charge pump 11 feeding a PLL loop integrating
filter 19. The filter 19 drives a voltage controlled oscillator 20 and the output of oscillator 20 is frequency divided by programmable divider 22.
The output of frequency divider 22 drives a delay equalization circuit 24 and different taps of the delay equalization circuit are provided to respective clock regenerator circuits 26, one of which is fed to a programmable divider which in turn feeds one of the inputs of phase detector 13. A system dock SYSCLK signal is applied to the other input of phase detector 13 through a programmable delay match circuit 30.
With this circuit, regenerated clock signals RCLK are frequency and
. Ltion Of phase locked to the SYSCLK signal. Further details of the operation of the Figure 1 circuit can be found in the noted Alvarez et al. article.
One problem with charge pump 11 is that with real world transistor devices and process spreads, when the PLL is in lock, neither the UP 15 nor the DOWN 17 pulses occur. This causes a dead-band in the PLL response where differences in phase between an applied system clock signal SYCLK and a PLL generated clock signal CPU cannot be detected. The usual remedy for such a situation is to make sure the UP 15 and DOWN 17 pulses occur under all conditions of operation, that is
the duration of the up and down pulses may be limited to very short durations, but they never disappear completely. However, there is a problem in producing a very short pulse at the output of charge pump 11, as it requires a very fast turn on and turn off of the charge pump 11 without a large amount of charge coupling which might distort the output signal.
Figure 2 illustrates one possible CMOS implementation of a fast switching charge pump 21 which produces a fast current spike at its output 23. Current sources 25 and 27 are switched by respectively serially connected p-channel and n-channel transistors 29,31 in response to respective DOWN (the inverse of a DOWN pulse) and UP pulses applied to respective gates 33 and 35.
The operation of the Figure 2 circuit is represented by the waveform produced by the Figure 2 circuit in response to a UP input pulse, which is shown in Figure 5. As seen, the output current upon the rom-off of transistor 31 goes positive in the shaded region of the output signal before returning to a steady zero state. This output current overshoot is caused by the considerable capacitive charge coupling 41
which occurs between the gate and output of transistor 31. A similar situation exist$ when transistor 29 is switched by the DOWN pulse due to capacitive charge coupling 43 between the gate and output of transistor 29. Any mismatch in the charge coupling at transistors 29 and 31 causes current pulse distortion which is applied to the VCO. The unbalanced charge coupling is compensated by a phase offset at the input to the phase detector 13. Thus, the loop must adjust the UP/DOWN pulse lengths to ensure the net charge flow is zero. It would be desirable to minimize this current pulse distortion.
Figure 3 illustrates a CMOS charge pump 41 which does not suffer from capacitive charge coupling due to the presence ofp-channel and n-channel biasing transistors 43, 45. The transistors 43, 45 are DC biased so that they pass the correct amount of current during switching operations of transistors 29 and 31. Although the Figure 3 arrangement significantly mitigates the problem of current pulse distortion inherent in the Figure 2 circuit, operation of the Figure 3 circuit is relatively slow, as shown in Figure 6, which illustrates in cross-hatching a trailing edge of the output pulse current produced in response to an UP pulse at the gate
of transistor 31. The illustrated slowness in transistor turn-off is attributed to a parasitic load capacitor 57 which exits across the UP source and drain of the UP switching transistor 31. A similar parasitic load capacitor 53 is present across the source and drain of transistor 29. The parasitic load capacitors 51 and 53 produce slow turn off of transistors 29 and 31 and a delay in the trailing edge of the output signal, which is again applied as a phase offset at the input to the phase comparator.
What is needed is a charge pump for use in a PLL and DLL which is fast and which mitigates problems with current overshoot and transistor turn-off slowness.
SUMMARY OF THE INVENTION The present invention provides a charge pump which has a fust switching characteristic and which mitigates the effected noise, current overshoot and transistor turn-off slowness at the charge pump output.
The invention also provides a PLL or DLL circuit which uses the charge pump.
The charge pump incorporates n-channel and p-channel switching transistors and n-channel and p-channel biasing transistors, as well as a capacitive coupling of complementary versions of the signals used to switch the n-channel and p-channel switching transistors to respective nodes which interconnect the p-channel switching and biasing transistors and the n-channel switching and biasing transistors. The capacitively coupled complementary signals cause the charge pump to maintain a fast switching response without output waveform distortion.
These and other features and advantages of the invention will be more clearly understood n'om the following detailed description of the invention which is provided in connection with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 illustrates a conventional phase lock loop (PLL) circuit which employs a charge pump 11 ;
Figure 2 illustrates a charge pump circuit which may be used in the PLL of Figure 1 ;
Figure 3 illustrates a charge pump circuit which is an improvement upon that illustrated in Figure 2 ; Figure 4 illustrates a charge pump circuit in accordance with an embodiment of the invention ;
Figure 5 illustrates a timing diagram which shows operation of the charge pump illustrated in Figure 2;
Figure 6 illustrates a timing diagram of the operation of the charge pump depicted in Figure 3;
Figure 7 illustrates the timing diagram of the charge pump of
Figure 4 in accordance with an exemplary embodiment of the invention ; and Figure 8 illustrates a processor system which may employ the charge pump of the invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Figure 4 illustrates an exemplary embodiment of a CMOS charge pump 61 in accordance with the invention. The circuit is essentially the same as that illustrated in Figure 3, except for the addition of coupling capacitors 65 and 69 which respectively receive an inverted form of the DOWN signal applied to gate 33, that is a DOWN signal and capacitor 69 which receives an inverted form of the UP signal, that is an
UP signal
The signal DOWN is applied through capacitor 65 to the common node A of respective switching and D. C. biasing transistors 29 and 43, while the switching signal UP is applied through capacitor 69 to the common node 13 between respective transistors 45 and 31. The provision of the switching signals DOWN and UP to respective nodes A
and B provides a fast turn on and turn off of the transistors 29 and 31 without waveform distortion in the resulting output signal. The voltage on the capacitors 65 and 69 settles to a DC point where the voltage across transistors 29 and 31 is minimal, but the net effect is a fast mm on and
turn off of transistor 29 and 31 with low capacitively coupled charge injection.
Figure 7 illustrates the output of the Figure 4 circuit when an
UP puke is applied. As shown) the output current switches very quickly following the switching timing of the UP pulse. As also shown, there is no significant waveform distortion in the output signal which might produce a phase onset at the phase comparator 13 of a PLL or DLL.
The charge pump 61 of the invention can be used in the Figure I phase lock loop circuit, as well as in delay lock loop (DLL) circuits to achieve fast turn on and tum off in response to short duration pump UP and pump DOWN input signals which may be generated in the PLL or
DLL to keep it operating) even when phase lock is achieved.
The charge pump 61 may also be used in any situation where fast switching of logic signals is needed, including in high speed processor systems. As shown in Figure 8 a processor system, such as a computer system, for example, generally comprises a central processing unit (CPU) 210, for example, a microprocessor, that communicates with one or more
input/output (I/O) devices 240, 250 over a bus 270. The computer system 200 also includes random access memory (RAM) 260, a read only memory (ROM) 280 and may also include peripheral devices such as a floppy disk drive 220 and a compact disk (CD) ROM drive 230 which also communicate with CPU 210 over the bus 270. Any one or more of the elements depicted in Figure 8 may use the charge pump 61 of the invention and/or a PLL or DLL which employs the inventive charge pump 61.
While an exemplary embodiment of the invention has been described and illustrated, it should be apparent that many modifications and substitutions can be made without departing from the spirit and scope of the invention. Accordingly, the invention is not limited by the foregoing description, but is only limited by the scope of the appended claims.
Claims (24)
1. A charge pump circuit comprising ; a first plurality of serially connected transistors of a first conductivity type ; a second plurality of serially connected transistors of a second conductivity type ; said first plurality of serially connected transistors being serially connected to the second plurality of serially connected transistors; the interconnection of said first and second plurality of transistors providing an output ; a gate of one of said first plurality of transistors being adapted to receive a DOWN pulse signal, a gate of another one of said first plurality of transistors being adapted to receive a DC bias signal, a gate of one of said second plurality of transistors being adapted to receive an UP
pulse signal, and a gate of the other of said second plurality of transistors being adapted to receive another DC bias signal, and a first node at the interconnection of transistors of said first plurality of transistors being adapted to receive a DOVVN pulse signal and a second node at the interconnection of transistors of said second plurality of transistors being adapted to receive an UP pulse signal.
2. A charge pump circuit as in claim 1 wherein said first plurality of transistors are p-channel transistors and said second plurality of transistors are n-channel transistors.
3. A charge pump circuit as in claim 1 further comprising a first capacitor circuit for coupling said DOWN pulse signal to said first node and a second capacitor circuit for coupling said UP pulse signal to said second node.
4. A charge pump circuit as in claim I wherein said first plurality of transistors is a pair of transistors and said second plurality of transistors is a pair of transistors.
5. A CMOS logic circuit comprising :
a first circuit portion containing transistors of a first conductivity type and a second circuit portion containing transistors of a second conductivity type, said first and second circuit portions being interconnected and the interconnection defining an output, said first circuit portion being responsive to first and second complementary pulse signals and a first DC bias signal, said second circuit portion being responsive to third and fourth complementary pulse signals and a second DC bias signal.
6. A CMOS logic circuit as in claim 5 further comprising a respective capacitor circuit for coupling said second and fourth complementary signals to said respective first and second circuit portions.
7. A CMOS switching circuit comprising :
a p-channel switching transistor, said p-channel switching, I transistor having a gate for receiving a first switching signal; a p-channel bias transistor connected in series with said p channel switching transistor, said p-channel bias transistor having a gate for receiving a bias voltage, said serially connected p-channel switching
transistor and p-channel bias transistor being connected between a first potential source and an output terminal ; an n-channel switching transistor, said n-channel switching transistor having a gate for receiving a second switching signal; an n-channel bias transistor connected in series with said nchannel switching transistor, said n-channel bias transistor having a gate for receiving a bias voltage, said serially connected n-channel switching transistor and n-channel bias transistor being connected between said output terminal and a second potential source; a first capacitor for coupling a complementary version of said first switching signal to a connection node of said p-channel transistors ;
and a second capacitor for coupling a complementary version of said second switching signal to a connection node of said n-channel transistors.
8. A charge pump circuit comprising :
a first plurality of serially connected transistors of a first conductivity type ; a second plurality of serially connected transistors of a second conductivity type ; said first plurality of serially connected transistors being serially connected to the second plurality of serially connected transistors ; the interconnection of said first and second plurality of transistors providing an output; a gate of one of said first plurality of transistors being adapted to receive a first switching signal, a gate of another one of said first plurality of transistors being adapted to receive a DC bias signal, a gate of one of said second plurality of transistors being adapted to receive a second switching signal, and a gate of the other of said second plurality of transistors being adapted to receive another DC bias signal; and
a first node at the interconnection of transistors of said first plurality of transistors being adapted to receive a complementary first switching signal and a second node at the interconnection of transistors of said second plurality of transistors being adapted to receive a complementary second switching signal.
9. A lock loop circuit comprising : a voltage controlled oscillator ;
I a circuit for deriving a first dock signal from said voltage controlled oscillator ; a phase detector for receiving said first clock signal and a second clock signal, said phase detector producing first and sc : cond switching signals in accordance with a phase difference between said first and second clock signals, a charge pump circuit for receiving said first and second switching signals and producing an output signal therefrom ; and
a filter circuit receiving the output signal from said charge pump and providing a filtered signal to control said voltage control oscillator; said charge pump circuit comprising: a first plurality of serially connected transistors of a first conductivity type ; a second plurality of serially connected transistors of a second conductivity type ; said first plurality of serially connected transistors being serially connected to the second plurality of serially connected transistors ; the interconnection of said first and second plurality of transistors providing an output ; a gate of one of said first plurality of. transistors being adapted to receive a first switching signal, a gate of another one of said first plurality of transistors being adapted to receive a DC bias
signal, a gate of one of said second plurality of transistors being adapted to receive a second switching signal, and a gate of the other of said second plurality of transistors being adapted to receive another DC bias signal; and a first node at the interconnection of transistors of said first plurality of transistors being adapted to receive a complemcntary first switching signal and a second node at the interconnection of transistors of said second plurality of transistors being adapted to receive a complementary second switching signal.
10. A phase lock loop circuit as in claim 9 wherein said first I plurality of transistors are p-channel transistors and said second plurality of tranSistors are n-channel transistors.
11. A phase lock loop as in claim 9 further comprising a first capacitor circuit for coupling said complementary first switching signal to said first node and a second capacitor circuit for coupling said complementary second switching signal to said second node.
12, A phase lock loop as in claim 9 wherein said first plurality of transistors is a pair of transistors and said second plurality of transistors is a pair of transistors.
13. A lock loop circuit comprising : a voltage controlled oscillator ; a circuit for deriving a first clock signal from said voltage controlled oscillator;
I a phase detector for receiving said first clock signal and a second clock signal, said phase detector producing first and second switching signals in accordance with a phase difference between said first and second clock signals ; a charge pump circuit for receiving said first and second switching signals and producing an output signal therefrom ; and a filter circuit receiving the output signal from said charge pump and providing a filtered signal to control said voltage control oscillator ;
said charge pump circuit comprising : a first circuit portion containing transistors of a first conductivity type and a second circuit portion containing transistors of a second conductivity type, said first and second circuit portions being interconnected and the interconnection defining an output) said first circuit portion being responsive to said first switching signal and its complement and a first DC bias signal, said second circuit portion being responsive to said second switching signal and its complement and a second DC bias signal.
14. A lock loop circuit as in claim 13 further comprising a respective capacitor circuit for coupling said first and second complementary signals to said respective first and second circuit portions.
15. A lock loop circuit comprising : a voltage controlled oscillator ; a circuit for deriving a first clock signal from said voltage controlled oscillator,
a phase detector for receiving said first dock signal and a second clock signal, said phase detector producing first and second switching signals in accordance with a phase difference between said first and second clock signals; a charge pump circuit for receiving said first and second switching signals and producing an output signal therefrom ; and a filter circuit receiving the output signal from said charge pump and providing a filtered signal to control said voltage control oscillator ; said charge pump circuit comprising : a p-channel switching transistor, said p-channel switching transistor having a gate for receiving said first switching signal ; a p-channel bias transistor connected in series with said pchannel switching transistor, said p-channel bias transistor having a gate for receiving a bias voltage, said serially connected p-channel switching
transistor and p-channel bias transistor being connected between a first potential source and an output terminal ; an n-channel switching transistor, said n-channel switching transistor having a gate for receiving said second switching signal; an n-channel bias transistor connected in series with said nchannel switching transistor, said n-channel bias transistor having a gate for receiving a bias voltage, said serially connected n-channel switching transistor and n-channel bias transistor being connected between said output terminal and a second potential source; a first capacitor for coupling a complementary version of said first switching signal to a connection node of said p-channel transistors ; and a second capacitor for coupling a complementary version of said second switching signal to a connection node of said n'channel transistors.
16. A processor system comprising :
a processor ; and a data device coupled to said processor, at least one of said processor and data device including a charge pump circuit, said charge pump circuit comprising : a first plurality of serially connected transistors of a first conductivity type ; a second plurality of serially connected transistors of a second conductivity type; said first plurality of serially connected transistors being serially connected to the second plurality of serially connected transistors ; the interconnection of said first and second plurality of transistors providing an output; a gate of one of said first plurality of transistors being adapted to receive a DOWN pulse signal, a gate of another. one of said first plurality of transistors being adapted to receive a DC bias signal, a gate of one of said second plurality of transistors being adapted to receive an UP
pulse signal, and a gate of the other of said second plurality of transistors being adapted to receive another DC bias signal ; and a first node at the interconnection of transistors of said first plurality of transistors being adapted to receive a DOWN pulse signal and a second node at the interconnection of transistors of said second plurality of transistors being adapted to receive an UP pulse signal.
17, A processor system as in claim 16 wherein said first plurality of transistors are p-channel transistors and said second plurality of transistors are n-channel transistors.
18. A processor system as in claim 16 further comprising a first capacitor circuit for coupling said DOWN pulse signal to said first node and a second capacitor circuit for coupling said UP pulse signal to said second node.
19. A processor system as in claim 16 wherein said first plurality of transistors is a pair of transistors and second plurality of transistors is a pair of transistors,
20. A processor system comprising :
a processor ; and a data device coupled to said processor, at least one of said processor and data device including a charge pump circuit, said charge pump circuit comprising : a first circuit portion containing transistors of a first conductivity type and a second circuit portion containing transistors of a second conductivity type, said first and second circuit portions being interconnected and the interconnection defining an output, said first circuit portion being responsive to first and second complementary pulse signals and first dc bias signal, said second circuit portion being responsive to third and fourth complementary pulse signals and a second dc bias signal.
21. A processor system according as in claim 20 further comprising a respective capacitor circuit for coupling said second and fourth complementary signals to said respective first and second circuit portions.
22. A processor system comprising :
a processor ; and a data device coupled to said processor, at least one of said processor and data device including a charge pump circuit, said charge pump circuit comprising : a p-channel switching transistor, said p-channel switching transistor having a gate for receiving a first switching signal; a p-channel bias transistor connected in series with said pchannel switching transistor, said p-channel bias transistor having a gate for receiving a bias voltage, said serially connected p-channel switching transistor and p-channel bias transistor being connected between a first potential source and an output terminal ; an n-channel switching transistor, said n-channel switching transistor having a gate for receiving a second switching signal ; an n-channel bias transistor connected in series with said nchannel switching transistor, said n-channel bias transistor having a gate for receiving a bias voltage, said serially connected n-channel switching
transistor and n-channel bias transistor being connected between said output terminal and a second potential source ; a first capacitor for coupling a complementary version of said first switching signal to a connection node of said p-channel transistors; and a second capacitor for coupling a complementary version of said second switching signal to a connection node of said n-channel transistors.
23. A method of operating a charge pump comprising : switching a first switching transistor in response to a first applied switching signal to affect an output at an output terminal ; switching a second switching transistor in response to a second applied switching signal to affect an output at said output terminal ; biasing the switching characteristics of said-first and second switching transistors with bias transistors respectively serially connected to said first and second switching transistors ; coupling a complementary signal of said first applied switching signal to a connection between said first switching transistor and an associated bias transistor; and coupling a complementary signal of said second applied switching signal to a connection between said second switching transistor and an associated bias transistor.
24. A method as in claim 23 wherein said coupling is a capacitive coupling.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB0108117A GB2374217B (en) | 2001-03-30 | 2001-03-30 | Low injection charge pump |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB0108117A GB2374217B (en) | 2001-03-30 | 2001-03-30 | Low injection charge pump |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB0108117D0 GB0108117D0 (en) | 2001-05-23 |
| GB2374217A true GB2374217A (en) | 2002-10-09 |
| GB2374217B GB2374217B (en) | 2005-01-05 |
Family
ID=9911994
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB0108117A Expired - Fee Related GB2374217B (en) | 2001-03-30 | 2001-03-30 | Low injection charge pump |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2374217B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5592113A (en) * | 1995-03-28 | 1997-01-07 | National Semiconductor Corp. | Gradual frequency changing circuit |
| EP0798862A1 (en) * | 1996-03-28 | 1997-10-01 | Nec Corporation | Charge pump circuit for use in a phase locked loop |
| US5825640A (en) * | 1997-06-30 | 1998-10-20 | Motorola, Inc. | Charge pump circuit and method |
| US6052015A (en) * | 1997-08-27 | 2000-04-18 | U.S. Philips Corporation | Output stage for a low-current charge pump and demodulator integrating such a pump |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5532636A (en) * | 1995-03-10 | 1996-07-02 | Intel Corporation | Source-switched charge pump circuit |
| KR100374631B1 (en) * | 2000-06-09 | 2003-03-04 | 삼성전자주식회사 | Charge pump circuit |
| US6483358B2 (en) * | 2001-02-02 | 2002-11-19 | Broadcom Corporation | Low power, charge injection compensated charge pump |
-
2001
- 2001-03-30 GB GB0108117A patent/GB2374217B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5592113A (en) * | 1995-03-28 | 1997-01-07 | National Semiconductor Corp. | Gradual frequency changing circuit |
| EP0798862A1 (en) * | 1996-03-28 | 1997-10-01 | Nec Corporation | Charge pump circuit for use in a phase locked loop |
| US5825640A (en) * | 1997-06-30 | 1998-10-20 | Motorola, Inc. | Charge pump circuit and method |
| US6052015A (en) * | 1997-08-27 | 2000-04-18 | U.S. Philips Corporation | Output stage for a low-current charge pump and demodulator integrating such a pump |
Also Published As
| Publication number | Publication date |
|---|---|
| GB0108117D0 (en) | 2001-05-23 |
| GB2374217B (en) | 2005-01-05 |
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| Date | Code | Title | Description |
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| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20140330 |