GB2373921A

GB2373921A - Fabrication of integrated modulated waveguide structures by self-alignment process

Info

Publication number: GB2373921A
Application number: GB0107613A
Authority: GB
Inventors: Adrian Petru Vonsovici
Original assignee: Bookham Technology PLC
Current assignee: Lumentum Technology UK Ltd
Priority date: 2001-03-27
Filing date: 2001-03-27
Publication date: 2002-10-02
Also published as: GB0107613D0

Abstract

An self-aligning process for fabricating integrated modulated waveguide structures involves steps of laying a resist mask (116) on a vertical feature (112) (e.g a ribbed waveguide) of a partially formed structure, and then forming further features (118) (e.g. recesses) based on this mask. This process may be performed by forming ribbed waveguide (112) using mask (110), then adjusting the extent of the mask to form fillets or lobes (116) prior to forming recesses (118). The process may also be used to form waveguide (10) and modulator (20,22,24) by defining the higher feature of the waveguide and modulator, and then locating a resist mask relative to this feature, and defining the remaining features of the structure. The fillets (116) may be formed by anisotropic etching of resist mask layer (115, Fig. 5) . As the fillets (116) are located relative to the ridge waveguide structure (112), the recesses (118) will be accurately located relative to the ridge waveguide (112), thus avoiding the need for a highly precise alignment step to form recesses (118) following the formation of waveguide (112). The separation between the ribbed waveguide (112) and the trench (118) can be defined to an accuracy of 50 nm, so variations are under 20% for separations in the range of 1 žm to 2 žm.

Description

Fabrication of Integrated Modulated Waveguide Structures The present invention relates to the fabrication of modulated waveguide structures.

Lateral injection PIN diodes are currently used for modification of the complex refractive index of two dimensional semiconductor waveguides (rib, strip-loaded etc). The silicon-on-insulator (SOI) two dimensional waveguides have a layer of buried oxide that acts both as a confinement layer for the optical mode and injected carriers. Lateral PIN diodes are currently fabricated by diffusion of the dopants in a slab layer a few microns thick.

The performance and reproducibility of such diodes is presently poor and this is mainly due to the fact that a great amount of injected carriers escape underneath the p and n junctions with a junction depth less than the slab layer thickness. A practical method to circumvent such problems is by using recessed junctions having a substantially high level of dopant concentration at the base of the recess, typically greater than the level of free carrier concentration expected. This solution is straightforwardly extendable to the case of modern doping technologies that use ion implantation.

Figure 1 shows such a device. A rib waveguide 10 is formed on an SOl wafer 12 comprising a silicon (Si) substrate 14, a buried SiO2 layer 16, and an upper Si layer 18. On either side of the waveguide 10, a trench 20 is formed extending part way to the buried SiO2 layer. A doped region 22 is formed at the base of the trench 20 and extends to the buried SiO2 layer. A metal contact 24 over the top of the trench 20 allows electrical contact to be made with the doped region 22 in a known manner.

Fabrication of such devices requires alignment of the rib (optical waveguide) structure and the injection (PIN) structure. To date, this has required close control of the deposition photolithography (mask alignment) and etch processes, but the present invention provides an approach which can automatically align the two structures.

The present invention therefore provides a method of forming an integrated modulated waveguide structure comprising the steps of forming a mask including detail pertaining to the waveguide and/or the modulator, forming features of at least one of the modulator and/or waveguide prior to adjusting the extent of the mask, and subsequently forming features of at least one of the waveguide and/or modulator respectively.

A modulated waveguide is one that is associated with a modulator structure, such as one with adjacent doping that can be used as an attenuator etc.

The present invention also provides a method of forming an integrated modulated waveguide structure comprising the steps of defining a vertical feature of the highest of the waveguide and modulator, forming a resist mask located relative to the vertical feature, and defining remaining features of the modulated waveguide structure.

The mask is preferably located relative to the edges of the vertical feature.

It is preferred that the mask comprises a first resist layer with structural features and a second resist layer with further structural features. One layer can include features of one of the waveguide and modulator, whilst the other layer can include features of the modulator or waveguide respectively.

The resist layer can be laid in selected areas, or laid and etched selectively.

In this case, it is preferred that the etch is an anisotropic etch which can thereby limit the resist layer to aspects of the vertical feature such as its edges.

The waveguide is preferably a rib waveguide, more preferably an SOI rib waveguide. This will normally be the highest feature of the modulated waveguide structure.

Suitable modulators include PIN modulators which operate by way of the influence on refractive index of charge carrier concentration, or thermal modulators which rely on a similar influence of temperature.

The remaining feature is preferably a doped area, such as for use in forming a PIN modulator.

Alternatively, the remaining feature can be a recess, in which case it is preferred that a doped region is formed in the recess extending from a base thereof.

The recess can be formed with angled walls, such as via a partially anisotropic etch, i. e. an etchant which etches predominantly in one direction, with some etching taking place in other directions. Electrical contacts which traverse the edge of such a recess are more reliable since they are less prone to failure at the edge.

Embodiments of the present invention will now be described, by way of example, with reference to the accompanying figures, in which: Figure 1 (already described) is a vertical section through a known waveguide and modulator structure; Figures 2-8 are sequential steps in the present invention, each being a vertical section, i. e. perpendicular to the plane of the chip; and Figure 9 shows a vertical section of a second embodiment.

Figure 1 has been described previously, and will not be described further.

Figure 2 shows an SOI wafer 100 comprising a silicon substrate 102 beneath an insulating oxide layer 104, over which is a thin epitaxial silicon layer 106 (the "epi layer"). A resist mask 108 of (for example) silicon nitride, silicon dioxide silicon oxynitride or metal oxide is deposited over the epi layer 106. As shown in figure 3, the resist layer 108 is then etched back to a resist stripe 110 which defines the rib waveguide which is to be formed.

The epi layer 106 is then dry etched. The resist stripe 110 will protect the silicon beneath it so that a rib waveguide structure 112 is formed, as shown in figure 4.

In figure 5, further areas of the epi layer 106 are masked by resist areas 114 to define other features of the modulated waveguide structure in question, or other features of the device. A further resist layer 115 is then overlaid to a thickness of about 125% of the intended separation of the waveguide and modulator structure, and the further resist layer is anisotropically etched. This anisotropic etch will leave behind fillets 116 on either side of the rib waveguide structure 112. As these are formed in this way, they will automatically be located relative to the actual location of the rib waveguide itself. Any absolute errors in the positioning of either will selfcorrect.

The epi layer can then be further etched as in figure 7 to form recesses 118, 120 either side of the rib waveguide structure 112. The fillets 116 will protect the epi layer beneath them and form a step 122 between the rib 112 and the recesses 118, 120 on either side. This step will provide the necessary spacing. All resists can then be removed to form the bare structure ready for doping by diffusion or ion implantation, as shown in figure 8, or (preferably) doping can be carried out whilst protective resists are in place to limit the extent of doping.

The spacing 122 will be defined by the width of the fillet 116 remaining after the anisotropic etch. This will depend on the nature of the etchant and resist, and

the thickness of the resist layer. It can thus be controlled as desired.

I If intended, the recesses can be omitted and the doped area defined by the fillets 116. The separation of the modulator structure and the rib waveguide will still be controlled, although the modulator will not be recessed, a structure found by the applicant to be advantageous.

Figure 9 shows an alternative embodiment in which a partially anisotropic etch is used to form the rib 112'and the recesses 118', 120'. Doped areas 124, 126 are formed in the recesses 118', 120'by diffusion or by ion implantation.

Electrical contacts leading to the doped areas are not shown in figure 9 but, when formed, will not have as sharp a corner to traverse (for example at 126) and are thus expected to be more reliable.

In practice, the invention delivers accuracy via the steps shown in relation to figure 7. A separation between the rib edge and the trench of about 1 to 2 Im is presently desired, whereas current techniques allow a positioning accuracy of below 1/im. The invention, on the other hand, allows an accuracy of 50nm thereby making a 1 to 2/im separation achievable.

It will be appreciated that many variations can be made to the abovedescribed embodiments, without departing from the scope of the present invention.

Claims

CLAIMS 1. A method of forming an integrated waveguide and a neighbouring doped region comprising the steps of forming a mask including detail pertaining to the waveguide and/or the doped region, forming features of at least one of the doped region and/or waveguide respectively prior to adjusting the extent of the mask, and subsequently forming features of at least one of the waveguide and/or doped regions respectively.
2. A method of forming an integrated modulated waveguide structure comprising the steps of defining a vertical feature of the highest of the waveguide and modulator, forming a resist mask located relative to the vertical feature, and defining remaining features of the modulated waveguide structure.
3. A method according to claim 2 in which the mask is located relative to the edges of the vertical feature.
4. A method according to any one of the preceding claims in which the mask comprises a first resist layer with structural features and a second resist layer with further structural features.
5. A method according to claim 4 in which one layer includes features of one of the waveguide and modulator, whilst the other layer can include features of the modulator or waveguide respectively.
6. A method according to any one of the preceding claims in which the resist layer is laid in selected areas.
7. A method according to any one of claims 1 to 5 in which the resist layer is laid and etched selectively.
8. A method according to claim 7 in which the etch is an anisotropic etch.
9. A method according to claim 7 in which the etch is an isotropic etch.
10. A method according to claims 8 and 9 in which the etch limits the resist layer to aspects of the vertical feature.
11. A method according to claim 10 in which the etch limits the resist layer to edges of the vertical feature.
12. A method according to any one of the preceding claims in which the waveguide is a rib waveguide.
13. A method according to claim 12 in which the waveguide is an SOI rib waveguide.
14. A method according to any one of claims 2 to 13 in which the modulator is a PIN modulator.
15. A method according to any one of the preceding claims in which the remaining feature is a doped area.
16. A method according to claim 15 in which the doped area is or is to be part of a PIN modulator.
17. A method according to any one of claims 2 to 14 in which the remaining feature is a recess.
18. A method according to claim 17 in which a doped region is formed in the recess, extending from a base thereof.
19. A method according to claim 18 in which the recess is formed with angled walls.
20. A method according to claim 19 in which the angled walls are formed via a partially anisotropic etch.
21. A wafer containing a plurality of integrated optical devices thereon, each including a waveguide and a neighbouring doped region, the waveguide and doped regions of each of the plurality being positioned relative to each other with a distribution of distances which is less than 20% of an average separation distance which is itself below 2jam.
22. A method substantially as herein described with reference to and/or as illustrated in the accompanying figures.