GB2373350A - Configuring a digital data processing device - Google Patents

Configuring a digital data processing device Download PDF

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Publication number
GB2373350A
GB2373350A GB0108194A GB0108194A GB2373350A GB 2373350 A GB2373350 A GB 2373350A GB 0108194 A GB0108194 A GB 0108194A GB 0108194 A GB0108194 A GB 0108194A GB 2373350 A GB2373350 A GB 2373350A
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United Kingdom
Prior art keywords
processing device
data bus
bits
digital processing
configuring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB0108194A
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GB0108194D0 (en
GB2373350B (en
Inventor
Anthony Paul Banks
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Technologies UK Ltd
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NEC Technologies UK Ltd
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Publication date
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Publication of GB0108194D0 publication Critical patent/GB0108194D0/en
Publication of GB2373350A publication Critical patent/GB2373350A/en
Application granted granted Critical
Publication of GB2373350B publication Critical patent/GB2373350B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)

Abstract

A method for configuring a digital processing device 2 which is coupled to a data bus is provided. A data bit is applied to each of the lines of the data bus and these bits are read by the digital processing device. The functionality of the digital processing device is then configured in dependence on the bits. The bits are applied to the data lines D0, D1, D2, D3 by pull-up and pull-down resistors 4, 8 during an initialisation sequence.

Description

Configuration of Features of a Digital Processing Device This invention relates to the configuration of features of a digital processing device.
Complex digital devices such as a system ASIC may incorporate processor cores. These may have a number of configuration options which require setting at power up.
The settings are usually stored in a separate memory and are applied to the digital device at power up using extra configuration pins on the device. The use of such a system adds to the cost of the digital processing device and to the package size of the digital processing device.
The present invention seeks to overcome these problems by using signals applied to the data bus of the digital device as a method of setting configuration at power up without the use of any additional package pins.
The invention is defined in more detail in the appended claims to which reference should now be made.
A preferred embodiment of the invention will now be described in detail by way of example with reference to the accompanying single figure.
The figure shows a system ASIC device 2 which has four input bus pins DO, Dl, D2, and D3. The invention could be used with any number of input pins for the data bus.
The data bus is of the tri-state type and this will be the case for any device which utilises a bidirectional data bus interface, such as a micro processor or DSP. The tristate bus requires a pull-up or pull-down resistor to prevent it floating to a mid rail level when it is not being actively driven. The resistors required to achieve this are
either located externally to the device or, more commonly are incorporated within it.
The preferred embodiment of this invention make use of location of these resistors to indicate configuration data to the device during an initialisation sequence which is commenced at power up.
The figure shows two resistors 4 coupled to the bus lines DO and Dl which pull up the levels on those bus lines to that of the power supply VCC 6. Bus lines D2 and D3 are coupled to two further resistors 8, which pull the level of those lines down to system ground 10.
The apparatus operates by the device sampling the signal levels present on the data bus when it is not being driven, for example at power up or on a re-configuration for a new purpose. At such times all other devices on the bus are turned off. The pull-up and pull-down resistors 4 and 8 pull the levels on the respective bus lines up or down so that each bit can be used to indicate the configuration of the device. For example, in the system of figure 1 the bits applied to the data bus will be 1100. With, for example an 8 bit wide data bus and pull-up resistors on bits 0-3 and pull-down resistors on bits 4-7 the configuration of bits which the system ASIC 2 can read from the data bus are 11110000.
The reason this works is that it does not matter whether the data bus is pulled high or low in order to prevent it floating, when it is in the tri-state mode and not being driven. Therefore, a choice of pull-up and pulldown resistors can be applied to the data bus lines in any desired order to indicate a particular configuration.
The system ASIC 2 on power up reads the bits applied to the data bus lines and using this value is able to retrieve configuration data for the device 2 which can then apply to the various functions of the device.
The system could be modified to enable re-configuration to a different state by applying bits to the data bus to set up a particular configuration of the system ASIC device 2.

Claims (5)

  1. Claims 1. A method for configuring a digital processing device coupled to a data bus comprising the steps of applying a data bit to each of the lines of the data bus, reading the bits at the digital processing device, and configuring the functionality of the digital processing device in dependence on the read bits.
  2. 2. A method according to claim 1 in which the bits are applied to the data bus by pull-up and pull-down resistors which operate to set the levels of the lines of the data bus when no driving signal is being applied to them.
  3. 3. A method according to claim 1 or 2 in which the bits are applied to the data bus as part of an initialisation sequence.
  4. 4. A method according to claim 3 in which the initialisation sequence commences at power up of the digital processing device.
  5. 5. A method for configuring the state of a digital processing device substantially as herein described with reference to the figure.
GB0108194A 2001-03-07 2001-04-02 Configuration of features of a digital processing device Expired - Fee Related GB2373350B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GBGB0105609.2A GB0105609D0 (en) 2001-03-07 2001-03-07 Configuration of features of a digital processing device

Publications (3)

Publication Number Publication Date
GB0108194D0 GB0108194D0 (en) 2001-05-23
GB2373350A true GB2373350A (en) 2002-09-18
GB2373350B GB2373350B (en) 2004-03-17

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ID=9910151

Family Applications (2)

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GBGB0105609.2A Ceased GB0105609D0 (en) 2001-03-07 2001-03-07 Configuration of features of a digital processing device
GB0108194A Expired - Fee Related GB2373350B (en) 2001-03-07 2001-04-02 Configuration of features of a digital processing device

Family Applications Before (1)

Application Number Title Priority Date Filing Date
GBGB0105609.2A Ceased GB0105609D0 (en) 2001-03-07 2001-03-07 Configuration of features of a digital processing device

Country Status (1)

Country Link
GB (2) GB0105609D0 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0341511A2 (en) * 1988-05-09 1989-11-15 Siemens Nixdorf Informationssysteme Aktiengesellschaft High-availability computer system with a predefinable configuration of the modules
US5230058A (en) * 1989-12-05 1993-07-20 Zilog, Inc. IC chip having volatile memory cells simultaneously loaded with initialization data from uniquely associated non-volatile memory cells via switching transistors
US5590305A (en) * 1994-03-28 1996-12-31 Altera Corporation Programming circuits and techniques for programming logic
EP0774713A1 (en) * 1995-11-20 1997-05-21 Lucent Technologies Inc. Integrated circuit with programmable bus configuration
US5727207A (en) * 1994-09-07 1998-03-10 Adaptec, Inc. Method and apparatus for automatically loading configuration data on reset into a host adapter integrated circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0341511A2 (en) * 1988-05-09 1989-11-15 Siemens Nixdorf Informationssysteme Aktiengesellschaft High-availability computer system with a predefinable configuration of the modules
US5230058A (en) * 1989-12-05 1993-07-20 Zilog, Inc. IC chip having volatile memory cells simultaneously loaded with initialization data from uniquely associated non-volatile memory cells via switching transistors
US5590305A (en) * 1994-03-28 1996-12-31 Altera Corporation Programming circuits and techniques for programming logic
US5727207A (en) * 1994-09-07 1998-03-10 Adaptec, Inc. Method and apparatus for automatically loading configuration data on reset into a host adapter integrated circuit
EP0774713A1 (en) * 1995-11-20 1997-05-21 Lucent Technologies Inc. Integrated circuit with programmable bus configuration

Also Published As

Publication number Publication date
GB0105609D0 (en) 2001-04-25
GB0108194D0 (en) 2001-05-23
GB2373350B (en) 2004-03-17

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Legal Events

Date Code Title Description
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20080402