GB2373116A - Optical cross-connect with dynamic bandwidth allocation - Google Patents

Optical cross-connect with dynamic bandwidth allocation Download PDF

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Publication number
GB2373116A
GB2373116A GB0105835A GB0105835A GB2373116A GB 2373116 A GB2373116 A GB 2373116A GB 0105835 A GB0105835 A GB 0105835A GB 0105835 A GB0105835 A GB 0105835A GB 2373116 A GB2373116 A GB 2373116A
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GB
United Kingdom
Prior art keywords
ports
cards
slots
matrix
bandwidth
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB0105835A
Other versions
GB0105835D0 (en
Inventor
Jonathan Munns
Goete Joerg Mueller
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telent Technologies Services Ltd
Marconi Communications Ltd
Original Assignee
Telent Technologies Services Ltd
Marconi Communications Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telent Technologies Services Ltd, Marconi Communications Ltd filed Critical Telent Technologies Services Ltd
Priority to GB0105835A priority Critical patent/GB2373116A/en
Publication of GB0105835D0 publication Critical patent/GB0105835D0/en
Priority to PCT/GB2002/001039 priority patent/WO2002073846A2/en
Priority to AU2002238728A priority patent/AU2002238728A1/en
Publication of GB2373116A publication Critical patent/GB2373116A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q11/00Selecting arrangements for multiplex systems
    • H04Q11/0001Selecting arrangements for multiplex systems using optical switching
    • H04Q11/0005Switch and router aspects
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q11/00Selecting arrangements for multiplex systems
    • H04Q11/0001Selecting arrangements for multiplex systems using optical switching
    • H04Q11/0005Switch and router aspects
    • H04Q2011/0037Operation
    • H04Q2011/0039Electrical control
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q11/00Selecting arrangements for multiplex systems
    • H04Q11/0001Selecting arrangements for multiplex systems using optical switching
    • H04Q11/0005Switch and router aspects
    • H04Q2011/0037Operation
    • H04Q2011/0043Fault tolerance

Abstract

An optical multiplexer apparatus, in particular for an SDH communications system, has in addition to the usual M-port-equivalent cross-connection matrix and a number of traffic slots with associated printed-circuit cards, a bandwidth-distribution function which enables the available ports of the matrix to be allocated to the various cards on an as-needed basis instead of on a fixed basis as is currently the case. The bandwidth-distribution function may be realised as a series of asymmetric switches, one per matrix equivalent-port, each interfacing one of the slots to one of the M ports. The slots may equally be tributary or line-interface cards.

Description

OPTICAL MULTIPLEXER APPARATUS The invention relates to an optical multiplexer apparatus and in particular, but not exclusively, an optical multiplexer apparatus for an SDH communications system.
Optical multiplexers are known which allow a plurality of end-users to share a common optical path. A much simplified representation of this is shown in Figure 1, in which a cross-connection matrix 10 allows access to the traffic contained within the optical and/or electrical line and tributary interfaces associated with an optical-fibre arrangement 11. The tributary interfaces 13, or"slots,"are shown as being n in number and the matrix has a capacity of M ports or"equivalent"ports (i. e. the matrix may have a number of "equivalent ports"sharing one physical port; thus M refers to the total number of ports actually available). In what follows it is to be understood that the term"ports"may also include the concept of"equivalent ports".
In practice the matrix 10 may be a switch forming part of an add-drop multiplexer, the switch interleaving the low-bandwidth (e. g. 2 Mb/s) signals from the tributary cards onto the line interface, which may be, for example, 155 Mb/s in bandwidth or some multiple thereof. The line interface is also known as an"aggregate".
A typical schematically illustrated rack arrangement corresponding to the Figure 1 scheme is shown as a front view in Figure 2a and as a top view in Figure 2b. Here the "slots"are shown at 20 as sites on a backplane 21 and include in each case a card (14,15) and an associated connector 22 mounted on the backplane. The connectors act as internal traffic interfaces and carry electrical signals between the respective cards and the matrix cards via backplane wiring 23 (see Figure 1). The cards interface with respective end-users.
Both the east and west portions of the optical fibre 11 are taken to respective line interface
cards 14 and from there, internally, to the cross-connection matrix 12 for distribution and cross-connection. Matrix A is the main unit, matrix B being a backup in case of failure of the main unit. In this example the matrices are 64-port (i. e. port-equivalent) devices. Also mounted in the rack are tributary cards 15, marked a-j in the drawing. These plus the line interface cards are assumed to have a port-allocation as shown by the bracketed numbers, thus the line cards are allotted 16 ports each, card a 8, cards b, e, f and g 4 and cards c, d, h and j 2. The sum total of all these port allocations is the same as the equivalent capacity of the matrices, in this case 64. Note that, although the distribution of the total equivalentport capacity is shown as being the same on the two sides of the matrix (i. e. 32 ports on the East side, 32 on the West), in practice these distributions may be skewed, depending on physical and space-related considerations.
It is also assumed in this example that the actual electrical wiring (i. e. backplane wiring) between the matrices and the various slots is such that a higher port requirement than the figures shown could in some cases be accommodated. Thus the wiring may in practice be sufficient to allow up to, say, 8 ports per slot a-j.
A major drawback with this known system of port allocation is that it is fixed, being drawn up in accordance with expected port allocation requirements in respect of the cards to be used. There are, however, occasions when it would be useful to be able to insert cards anywhere in the rack, regardless of whether they are line cards or tributary cards and regardless of their port-rating. It may, to take one example, be more expedient to place card a in slot b instead of in slot a. Since the port-allocation for slot b is limited to 4 ports (although slot b could physically take 8 ports due to its internal wiring capacity), this is not possible under this kind of arrangement. The only solution under the present system,
assuming the rack had sufficient backplane capacity, would be to substitute a larger crossconnection matrix for the 64-port matrices 12, e. g. 128-port equivalent devices. This is illustated in Figure 3, where the overall effect of this change is seen in the revised portallocation ratings in brackets for each card. Now card b can be allotted 8 ports instead of 4, leaving the other slots unchanged (see the upper row of bracketed figures), or-to take advantage of the increased matrix capacity-each card can now be allocated up to 8 ports (lower row of bracketed figures) and still remain within the total capacity of the matrix and the backplane wiring.
The major drawback with this amended scheme, however, is the wastage in bandwidth, since now under the best-case scenario (i. e. increasing slot capacity to 8 ports each) 24 of the available 128 ports in the matrix 12 will be unexploitable by the existing cards. In the scenario where the only change in port allocation is the change to slot b, the wastage will be far greater.
In accordance with a first aspect of the invention there is provided an optical multiplexer apparatus as specified in Claim 1. In a second aspect of the invention there is provided a method for allocating the ports of an M-port switch to N traffic slots and their associated cards in an optical multiplexing rack, as specified in Claim 7. Various embodiments of the invention are covered by the subclaims.
An embodiment of the invention will now be described, by way of example only, with reference to the drawings, of which: Figure 1 is a simplified representation of a known multiplexing arrangement; Figures 2a and 2b are schematic front and top views, respectively, of a multiplexer switch rack for use in connection with the known arrangement of Figure 1;
Figure 3 is the same rack as in Figure 2a, but modified for use with an"overrated" card ; Figure 4 is a simplified representation of a multiplexing arrangement in accordance with the present invention; Figure 5 is an example of a switching rack under the multiplexing arrangement according to the invention; Figure 6 is a modified configuration of the rack illustrated in Figure 5; Figure 7 is a block diagram of a multiplexer arrangement under the present invention realised as part of a single integrated-circuit device; Figures 8a and 8b illustrate a possible realisation of the bandwidth distribution function of the present invention, and Figure 9 illustrates an exemplary bandwidth-distribution configuration in the bandwidth-distribution function of the present invention.
Turning now to Figure 4, the multiplexer arrangement in accordance with the present invention includes an extra function, namely a bandwidth distribution function 20 interposed between the switch 10 and the various slots, which are now designated simply as"traffic slots"16, without any differentiation between line or tributary interfaces. There are N slots in total. The purpose of the inclusion of this new bandwidth distribution function is to make it possible to reprogram the individual port allocations of the various slots so as to allow flexibility in the kinds of cards to be used. This extra function is designed to allow for example a situation such as shown in Figure 5, in which the various cards (line and tributary) are allocated ports as shown in brackets, these ports as usual adding up to the total of the matrix itself (here 64). The actual cards accommodated in the slots have port ratings
as shown by the numbers without the brackets. Since these two exactly correspond, there is no wastage in bandwidth.
In order to achieve this flexibility in bandwidth allocation there is mounted in the rack a control means 30 which interfaces with the bandwidth-distribution sections and controls the way in which the available ports from the matrices are distributed between the cards.
A second configuration of the same rack is depicted in Figure 6. Here it is seen that the 16-port cards that were in slots b and I (in practice these would be line interfaces) are located in different locations from the previous configuration (i. e. they now occupy slots a and h). In addition, the 8 and 4-port cards in slots e and j in Figure 5 have been transposed, thereby creating a skewed port-allocation arrangement (28 ports on one side of the matrices, 36 on the other), which was mentioned as a possibility earlier. Provided the physical backplane wiring allowed it, the line cards could be placed in any slot in the rack.
One possible embodiment of the new distribution function is shown in Figure 7 and Figures 8a and 8b. In Figure 7 a single integrated device, e. g. an ASIC, houses the M-portequivalent matrix and in addition a pair of bandwidth-distribution sections 31,32, one for each side of the switch. This combined matrix/bandwidth-distribution arrangement is shown as block 24 in Figure 4. Section 31 interfaces the N slots, which have in total P portequivalent electrical traffic interfaces (P > N), to the M ports of the switch in one direction, while section 32 interfaces the M ports of the switch to the N slots and traffic interface in the other direction.
The sections 31 and 32 may be realised in a number of ways, one way being shown in Figures 8a and 8b. Here each section comprises as many asymmetric switches 33 as there
are (equivalent) ports, each switch having N inputs (section 31) or outputs (section 32). A concrete example of the way in which the bandwidth is distributed amongst the slots is illustrated in Figure 9, in which for the sake of simplicity it is assumed that there are 4 slots (N = 4) and 16 ports (M = 16). In this case the control section 30 in the switching rack instructs the asymmetric switches 33 to assume the positions shown in Figure 9 so as to result in 8 ports being allocated to slot 1,4 to slot 2 and 2 each to slots 3 and 4. Figure 9 represents the situation for section 31 only; in practice section 32 will be controlled in a similar way to yield the same port-distribution configuration (the signal direction of section 32 being, however, opposite to that of section 31).
The controller 30 is arranged to configure the switches 33 on the basis of a prior knowledge of the individual cards to be used. This may be achieved either on a"plug-andplay'principle, where the controller reads the individual port-ratings from the various cards (e. g. either by reading from a memory location on board each card, or by means of jumpers on the card), or by a specific manual programing of the controller.
By means of the invention it is achieved that a switch of a particular equivalent capacity (e. g. 64 ports) appears to be larger than it actually is (i. e. up to almost twice as large), since none of the available bandwidth is wasted, in contrast to the existing situation.
This is of particular value where large-capacity switches are required to be used (e. g. 128port), since the larger the switch under the conventional scheme, the greater the bandwidth wastage. In addition, the invention is useful in extending the performance of a 128-port switch, which is the limit of the technology presently available, into one almost twice as large and not yet manufacturable.

Claims (14)

  1. CLAIMS 1. Optical multiplexer apparatus comprising an optical fibre interface; N card slots for the accommodation of a corresponding number of traffic cards; an M-port cross-connection matrix coupled to the fibre interface and to the slots for the switching of signals associated with the traffic cards onto the optical-fibre channels; a bandwidth-distribution means interposed between the matrix and the slots, and a controller means coupled to the bandwidth-distribution means, wherein by means of the controller means and bandwidthdistribution means the M matrix ports can be distributed in a flexible manner among the slots.
  2. 2. Apparatus as claimed in Claim 1, wherein the ports can be distributed in accordance with the bandwidth requirement of one or more of the cards.
  3. 3. Apparatus as claimed in Claim 2, wherein the ports can be distributed among the slots in accordance with the bandwidth requirement of all of the cards.
  4. 4. Apparatus as claimed in Claim 3, wherein all M ports are distributed to the cards.
  5. 5. Apparatus as claimed in any one of the preceding claims, wherein the matrix forms part of an add-drop multiplexer and the traffic cards include line cards and tributary cards.
  6. 6. Apparatus as claimed in any one of the preceding claims, wherein the bandwidthdistribution function is realised as a series of asymmetric switches, one for each of the M ports, each asymmetric switch interfacing one of the N slots to one of the M ports.
  7. 7. Apparatus as claimed in Claim 6, comprising two series of asymmetric switches, one series interfacing the N slots to the M ports of the matrix, the other interfacing the M ports of the matrix to the N slots.
  8. 8. Apparatus as claimed in any one of the preceding claims, wherein the matrix and bandwidth-distribution function are disposed on the same integrated device.
  9. 9. Apparatus as claimed in Claim 8, wherein the integrated device is an ASIC.
  10. 10. Method of allocating the ports of an M-port switch to N traffic slots and their associated cards in an optical multiplexing rack, comprising: ascertaining the individual bandwidth requirements of each of the cards in association with their location in the rack and instructing a bandwidth-distribution function in the rack to allocate a corresponding number of ports to each of the cards, whereby the total number of ports allocated does not exceed M.
  11. 11. Method as claimed in Claim 10, wherein the total number of ports allocated is equal toM.
  12. 12. Method as claimed in Claim 10 or Claim 11, wherein the bandwidth requirement of the various traffic cards is derived by the control means automatically through a"plug-and- play"procedure.
  13. 13. Method as claimed in Claim 10 or Claim 11, wherein the bandwidth requirement of the various traffic cards is supplied to the control means through a manual programming procedure.
  14. 14. Optical multiplexing apparatus substantially as shown in, or as hereinbefore described with reference to, Figures 5 to 9 of the drawings.
GB0105835A 2001-03-09 2001-03-09 Optical cross-connect with dynamic bandwidth allocation Withdrawn GB2373116A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
GB0105835A GB2373116A (en) 2001-03-09 2001-03-09 Optical cross-connect with dynamic bandwidth allocation
PCT/GB2002/001039 WO2002073846A2 (en) 2001-03-09 2002-03-07 Multiplexer apparatus
AU2002238728A AU2002238728A1 (en) 2001-03-09 2002-03-07 Multiplexer apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB0105835A GB2373116A (en) 2001-03-09 2001-03-09 Optical cross-connect with dynamic bandwidth allocation

Publications (2)

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GB0105835D0 GB0105835D0 (en) 2001-04-25
GB2373116A true GB2373116A (en) 2002-09-11

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GB0105835A Withdrawn GB2373116A (en) 2001-03-09 2001-03-09 Optical cross-connect with dynamic bandwidth allocation

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AU (1) AU2002238728A1 (en)
GB (1) GB2373116A (en)
WO (1) WO2002073846A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111490904A (en) * 2020-04-22 2020-08-04 北京星网锐捷网络技术有限公司 Uplink bandwidth allocation method, device, medium and equipment

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0559091A2 (en) * 1992-03-02 1993-09-08 Alcatel N.V. Inter-network element transport of SONET overhead
US5491694A (en) * 1994-01-28 1996-02-13 Cabletron Systems, Inc. System and method for allocating a shared resource among competing devices
US6125111A (en) * 1996-09-27 2000-09-26 Nortel Networks Corporation Architecture for a modular communications switching system

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9408574D0 (en) * 1994-04-29 1994-06-22 Newbridge Networks Corp Atm switching system
US5838681A (en) * 1996-01-24 1998-11-17 Bonomi; Flavio Dynamic allocation of port bandwidth in high speed packet-switched digital switching systems

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0559091A2 (en) * 1992-03-02 1993-09-08 Alcatel N.V. Inter-network element transport of SONET overhead
US5491694A (en) * 1994-01-28 1996-02-13 Cabletron Systems, Inc. System and method for allocating a shared resource among competing devices
US6125111A (en) * 1996-09-27 2000-09-26 Nortel Networks Corporation Architecture for a modular communications switching system

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WO2002073846A2 (en) 2002-09-19
AU2002238728A1 (en) 2002-09-24
GB0105835D0 (en) 2001-04-25
WO2002073846A3 (en) 2003-05-22

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