GB2373094A - Semiconductor device with 3-D resurf junctions - Google Patents

Semiconductor device with 3-D resurf junctions Download PDF

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Publication number
GB2373094A
GB2373094A GB0105692A GB0105692A GB2373094A GB 2373094 A GB2373094 A GB 2373094A GB 0105692 A GB0105692 A GB 0105692A GB 0105692 A GB0105692 A GB 0105692A GB 2373094 A GB2373094 A GB 2373094A
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semiconductor device
regions
region
rings
doped
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GB0105692D0 (en
GB2373094B (en
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Gehan Anil Joseph Amaratunga
Florin Udrea
Tatjana Traijkovic
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Dynex Semiconductor Ltd
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Dynex Semiconductor Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8611—Planar PN junction diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure

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  • Microelectronics & Electronic Packaging (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Thyristors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A high voltage device having 3-D resurf junctions comprises an active semiconductor body 1, such as a diode, bipolar transistor, IGBT or MOSFET, surrounded by a plurality of spaced highly doped surface floating rings 4, 5, 6 of opposite conductivity type. The surface area between each pair of rings comprises a plurality of shallow lowly doped p and n type regions 9,10 arranged in an alternating pattern of radial stripes or in a rectangular grid. The regions increase the resistance of the device to breakdown, and permit a reduced edge termination area for the device.

Description

SEMICONDUCTOR DEVICE WITH 3-D RESURF JUNCTIONS Field of the Invention This invention relates to a semiconductor device, typically a very high voltage device, for example above 1. 2kV, having 3-D RESURF (3-Dimensional REduced SURface Field) junctions to resist breakdown of the termination.
Background to the Invention The ability of a high voltage semiconductor device to withstand the voltage for which it has been rated is determined by a successful design of the device termination.
There are several reasons which make the edge termination problem more difficult as the voltage rating increases. Firstly, the standard termination technique which uses floating field rings (FR) requires a large number of rings, and hence a large area. Since this area is not used to carry more current in the on-state, a larger termination area adversely affects the on-state performance of the device. In addition, the larger the termination area, the lower are the yields of devices from a given area of substrate. Secondly, high voltage devices are more exposed to the influence of the parasitic charge present at the surface passivation layer or at the interface between the passivation layer and the silicon, since the n-drift region is very lowly-doped and even small levels of charge can cause formation of an inversion or accumulation layer at the surface. This can easily upset the balance of the optimised electric field distribution, necessary to achieve maximum breakdown capability, resulting in a premature breakdown.
Summary of the Invention According to the invention, there is provided a semiconductor device having 3 D resurf junctions, comprising an active semiconductor body surrounded by a plurality of spaced highly-doped surface floating rings of opposite conductivity type, characterised in that the area between each pair of rings comprises a plurality of alternating regions of shallow lowly-doped p-and n-type semiconductor materials.
Preferably, the alternating regions fill the whole space between the two adjacent floating rings.
In one embodiment of the invention, each region extends radially from one ring to the next.
The width of each region is preferably less than the radial distance between the respective pair of floating rings.
In an alternative embodiment of the invention, the regions comprise elements of a rectangular grid or other cellular structure. Each of the elements is preferably a square, and is suitably of less than 34m side and preferably of 1 m side. Regardless of the shapes of the regions, it is desirable that they should be as narrow as possible so that the distance of any point within a region from the junction with the next region of opposite conductivity type is as small as possible, leading to rapid depletion of the region.
The invention also provides a method of making a semiconductor device, comprising forming in the surface of the device around an active semiconductor body a plurality of spaced highly-doped surface floating rings of opposite conductivity type, characterised by forming in the surface area between each pair of rings a plurality of alternating regions of shallow lowly-doped p-and n-type semiconductor materials.
The alternating regions are suitably formed by implantation and diffusion. A preferred method of the invention comprises, forming a layer of a first lowly doped semiconductor material extending over substantially the whole of the termination area of the device, and then implanting regions of a second lowly doped semiconductor material in said layer to form n/p junctions therein.
The active semiconductor body may be, for example, a diode, a bipolar transistor, an IGBT (Insulated Gate Bipolar Transistor), a MOSFET device, or a thyristor.
Brief Description of the Drawings In the drawings, which illustrate exemplary embodiments of the invention: Figure 1 is a three-dimensional sectional view on line A-A through a portion of a device according to one embodiment of the invention as shown in Figure 2; Figure 2 is a top plan diagrammatic view of the complete device of which Figure 1 shows a section; Figure 3 is a diagram illustrating schematically the electric field between two p+ rings for the prior art floating field rings termination technique;
Figure 4 is a corresponding diagram to that shown in Figure 3, but for a device in accordance with the present invention ; and Figure 5 is a top plan view of a portion of a device according to an alternative embodiment of the invention.
Detailed Description of the Illustrated Embodiments Referring first to Figures 1 and 2, the semiconductor device, which in the illustrated embodiment is a diode, by way of example, has an active central area 1 of p-type semiconductor material in a body of n-type semiconductor material 2 and located on a layer of more highly doped n-type semiconductor material 3, which will be provided with an underlying metal electrode (not shown). The central area 1, which will also be provided with an electrode (not shown) thereon, is surrounded by three highly-doped p-type semiconductor rings 4,5 and 6, the floating field rings as in the prior art. An outer n-type doped ring 7 is provided as a channel stopper. A passivation layer 8 is provided on the surface of the device in conventional manner (shown separated in Figure 1 for clarity). The passivation layer 8 is of conventional form and may comprise an oxide layer. It may be a multi-layer structure.
It will be appreciated that, while a structure including three highly-doped p-type floating rings is described, the device may have fewer or more than three rings.
The area between each two p+ rings is filled with narrow stripes or cells of alternating shallow and lowly-doped p-and n-implants or doped layers 9 and 10.
In the embodiment shown in Figures 1 and 2, n and p doped layers are formed as radially-extending stripes 9 and 10 occupying the whole space between the adjacent p+ rings. n/p stripes or cells can also be provided at the edge of the outermost p+ ring 6, but they might not cover the whole of the space between the p+ ring and the channel stopper 7.
In a method of manufacturing a diode of the type illustrated in Figures 1 and 2, a silicon wafer 2, usually of low n-type concentration (typically less than 10e ions/cm3) forms the basis of the device. The implanted body 1 of p-type material forms the anode of the diode, while the layer 3 of more highly doped n-type semiconductor material is the cathode. The body 1 and the rings 4,5 and 6 are formed by standard semiconduc
tor manufacturing techniques. A masking layer is produced by photolithography methods and p-type ions (for example boron ions) will be implanted through openings, typi cally 10 u. m wide, in this masking layer. After removal of the masking layer, the p-type ions are diffused at high temperature to a depth of, typically, 3 to 10 film. The channel stopper n-type region 7 is similarly formed using n-type ions (for example phosphorus).
The lowly-doped regions 9 and 10 may also be formed by lithography, implantation and diffusion. A preferred method comprises forming a layer of a first lowly-doped semiconductor material by ion implantation extending over the whole area between the body 1 and the third floating ring 6, and then implanting regions of a second lowlydoped semiconductor material of opposite type. These second regions 10 are defined by photolithography and are of fine dimension, typically less than 3 u, m and preferably about 1 u. m wide. The second regions are of substantially higher dopant concentration, thereby compensating for the first lowly-doped layer in the regions 10. Both lowlydoped layers may be simultaneously diffused, typically to a depth of 1 film. the surface concentration of the lowly-doped regions 9 and 10 should typically be of the order of 10e ions/cm3 or less. The termination layer is then covered with a passivation layer 8 of suitable material and metal contacts are applied to the body 1 and the electrode layer 3.
If the stripes 9 and 10 are very narrow and relatively lowly doped when compared with the p+ rings 4, 5 and 6, but highly doped when compared with the drift region, the depletion region formed at each -/n-junction spreads very rapidly until the whole area between two adjacent p+ floating rings 4 and 5, or 5 and 6, is fully depleted, as may be seen from Figure 4. Compared with the standard p+ floating ring termination, the full depletion of the area between two adjacent p+ rings takes place at a much lower voltage due to the presence of the additional junctions formed between the thin n and p stripes. The shape of the electric field between two p+ floating rings changes from a triangular profile seen with the standard floating ring termination of the prior art, as illustrated by Figure 3, to a more rectangular profile with the present invention, as illustrated in Figure 4. The voltage supported by each pair of floating rings is equal to the area below the electric field curve between two adjacent floating rings. It follows
that each pair of rings in the 3D termination can withstand a higher fraction of the total voltage than in the standard floating ring termination. Therefore, a smaller number of rings can be used to support the same breakdown voltage, and thus reduce the termination area. Alternatively, the same number of rings can be employed, but with a smaller area between two consecutive p+ rings.
The number of the rings, and the spacing between each two adjacent rings, is optimised for the case of no charge at the surface or in the oxide or passivation layer. In the case of charge present at the surface (or in the oxide/passivation layer), the elec- tric field may change between two p+ rings, but the change is significantly less than in the case of the standard termination. For small to medium levels of charge (up to 5et 1 cm-2), the electric field maintains virtually a rectangular shape, since the area between p+ floating rings is still fully depleted at relatively high voltages. This is in spite of an ini tial presence of an inversion or accumulation layer at the interface before depletion takes place. As mentioned hereinbefore, the presence of an inversion or accumulation layer at the interface is due to the charge at the surface or in the oxide/passivation layer and the condition for charge neutrality across the layer 8. For higher levels of charge, the electric field changes substantially. However, the change is less than in the case of the standard floating ring termination.
An alternative configuration is illustrated in Figure 5, which shows in enlarged scale a portion between two of the floating rings 4 and 5 of a device of the general type shown in Figure 2. The p-and n-cells 9 and 10 are formed as squares uniformly distributed across the surface of the device. The dimensions of the squares should be as small as possible, for example less than 3jj. m and preferably of the order of 1 Vm side.

Claims (19)

  1. CLAIMS 1. A semiconductor device having 3-D resurf junctions, comprising an ac tive semiconductor body surrounded by a plurality of spaced highly-doped surface floating rings, characterised in that the surface area between each pair of rings comprises a plurality of alternating regions of shallow lowly-doped p-and n-type semiconductor materials.
  2. 2. A semiconductor device according to Claim 1, wherein each region has a width less than the radial distance between the respective pair of floating rings.
  3. 3. A semiconductor device according to Claim 1 or 2, wherein each region
    has a width less than 3 m.
  4. 4. A semiconductor device according to Claim 3, wherein each region has a width of 1 ism.
  5. 5. A semiconductor device according to any preceding claim, wherein the alternating regions fill the whole space between the two adjacent floating rings.
  6. 6. A semiconductor device according to any preceding claim, wherein each region extends radially from one ring to the next.
  7. 7. A semiconductor device according to any of Claims 1 to 5, wherein the . regions comprise elements of a cellular grid.
  8. 8. A semiconductor device according to Claim 7, wherein each of the re gions is square.
  9. 9. A semiconductor device, substantially as described with reference to, or as shown in, the drawings.
  10. 10. A method of making a semiconductor device, comprising forming in the surface of the device around an active semiconductor body a plurality of spaced highlydoped surface floating rings, characterised by forming in the surface area between each pair of rings a plurality of alternating regions of shallow lowly-doped p-and n-type semiconductor materials.
  11. 11. A method according to Claim 10, wherein each region has a width less than the radial distance between the respective pair of floating rings.
  12. 12. A method according to Claim 10 or 11, wherein each region has a width less than 3 urn.
  13. 13. A method according to Claim 12, wherein each region has a width of 1 . m.
  14. 14. A method according to any of Claims 10 to 13, wherein the alternating regions are formed by implantation and diffusion.
  15. 15. A method according to any of Claims 10 to 14, comprising forming a layer of a first lowly doped semiconductor material extending over substantially the whole of the termination area of the device, and then implanting regions of a second lowly doped semiconductor material in said layer to form n/p junctions therein.
  16. 16. A method according to any of Claims 10 to 15, comprising forming the regions as radial stripes extending between adjacent floating rings.
  17. 17. A method according to any of Claims 10 to 15, comprising forming a cellular grid of the alternating regions.
  18. 18. A method according to Claim 17, comprising forming the regions as squares.
  19. 19. A method of making a semiconductor device, substantially as described.
    19. A method of making a semiconductor device, substantially as described.
    Amendments to the claims have been filed as follows
    1. A semiconductor device having 3-D resurf junctions, comprising an active semiconductor body surrounded by a plurality of spaced highly-doped surface floating rings, characterised in that the surface area between each pair of rings comprises a plurality of alternating regions of shallow lowly-doped p-and n-type semiconductor materials alternating in the peripheral direction thereof.
    2. A semiconductor device according to Claim 1, wherein each region has a width less than the radial distance between the respective pair of floating rings.
    3. A semiconductor device according to Claim 1 or 2, wherein each region
    has a width less than 3 u, m.
    4. A semiconductor device according to Claim 3, wherein each region has a width of 1 u. m.
    5. A semiconductor device according to any preceding claim, wherein the alternating regions fill the whole space between the two adjacent floating rings.
    6. A semiconductor device according to any preceding claim, wherein each region extends radially from one ring to the next.
    7. A semiconductor device according to any of Claims 1 to 5, wherein the regions comprise elements of a cellular grid.
    8. A semiconductor device according to Claim 7, wherein each of the regions is square.
    9. A semiconductor device, substantially as described with reference to, or as shown in, the drawings.
    10. A method of making a semiconductor device, comprising forming in the surface of the device around an active semiconductor body a plurality of spaced highlydoped surface floating rings, characterised by forming in the surface area between each pair of rings a plurality of alternating regions of shallow lowly-doped p-and n-type semiconductor materials alternating in the peripheral direction thereof.
    11. A method according to Claim 10, wherein each region has a width less than the radial distance between the respective pair of floating rings.
    12. A method according to Claim 10 or 11, wherein each region has a width less than 3 u, m.
    13. A method according to Claim 12, wherein each region has a width of 1 Mm.
    14. A method according to any of Claims 10 to 13, wherein the alternating regions are formed by implantation and diffusion.
    15. A method according to any of Claims 10 to 14, comprising forming a layer of a first lowly doped semiconductor material extending over substantially the whole of the termination area of the device, and then implanting regions of a second lowly doped semiconductor material in said layer to form n/p junctions therein.
    16. A method according to any of Claims 10 to 15, comprising forming the regions as radial stripes extending between adjacent floating rings.
    17. A method according to any of Claims 10 to 15, comprising forming a cellular grid of the alternating regions.
    18. A method according to Claim 17, comprising forming the regions as squares.
GB0105692A 2001-03-08 2001-03-08 Semiconductor device with 3-D resurf junctions Expired - Fee Related GB2373094B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8110888B2 (en) 2007-09-18 2012-02-07 Microsemi Corporation Edge termination for high voltage semiconductor device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI496289B (en) * 2012-01-10 2015-08-11 Univ Asia Resurf semiconductor device with p-top rings and sti regions, and method for manufacturing the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5266831A (en) * 1991-11-12 1993-11-30 Motorola, Inc. Edge termination structure
WO1999023703A1 (en) * 1997-11-03 1999-05-14 Infineon Technologies Ag High voltage resistant edge structure for semiconductor elements
EP1076363A2 (en) * 1999-08-11 2001-02-14 Dynex Semiconductor Limited High voltage semiconductor device
US20010028083A1 (en) * 2000-02-09 2001-10-11 Yasuhiko Onishi Super-junction semiconductor device and method of manufacturing the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5266831A (en) * 1991-11-12 1993-11-30 Motorola, Inc. Edge termination structure
WO1999023703A1 (en) * 1997-11-03 1999-05-14 Infineon Technologies Ag High voltage resistant edge structure for semiconductor elements
EP1076363A2 (en) * 1999-08-11 2001-02-14 Dynex Semiconductor Limited High voltage semiconductor device
US20010028083A1 (en) * 2000-02-09 2001-10-11 Yasuhiko Onishi Super-junction semiconductor device and method of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8110888B2 (en) 2007-09-18 2012-02-07 Microsemi Corporation Edge termination for high voltage semiconductor device

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