GB2371690A

GB2371690A - Gain control of a stage of a tuner in a radio frequency receiver based on a quality of the demodulated signal

Info

Publication number: GB2371690A
Application number: GB0101783A
Authority: GB
Inventors: Bernard Arambepola; David Albert Sawyer
Original assignee: Mitel Semiconductor Ltd
Current assignee: Microsemi Semiconductor Ltd
Priority date: 2001-01-24
Filing date: 2001-01-24
Publication date: 2002-07-31
Also published as: GB0101783D0

Abstract

A radio frequency receiver for receiving digital signals comprises a tuner (3) for selecting a desired channel for reception. A demodulator (6-16) demodulates the signal in the desired channel and determines at least one quality of the demodulated signal, such as the bit error rate or the mean square error. An automatic gain controller (18) controls the gain of a front-end stage, preferably an attenuator 2, in accordance with the measured quality, for example so as to minimise the error or error rate or so as to reduce the front-end gain and hence tuner power consumption while maintaining an acceptable demodulator performance. Preferably the digital signals are quadrature amplitude modulated (QAM) signals. Further preferable features include the gain control being halted during an acquisition mode and reactivated (e.g. periodically) during a subsequent tracking mode or when a signal quality falls below a predetermined level. Disclosed are details of an algorithm (figure 7) for controlling the said automatic gain controller 18 along with other gain control elements 3,5 of the receiver front-end such that the order in which the different elements are controlled can be governed.

Description

Radio Frequency Receiver The present invention relates to a radio frequency receiver for receiving digital signals.

Such a receiver is suitable for use, for example, as a cable television (TV) receiver, a cable modem, a satellite TV receiver and a terrestrial digital TV receiver.

Figure 1 of the accompanying drawings illustrates a receiver"architecture"or arrangement which does not represent any particular prior art but which is representative of techniques employed in the prior art. The receiver comprises an input 1 for connection to, for example, a cable distribution network. The input 1 is connected to the input of an attenuator 2, whose output is connected to the input of a tuner 3. The output of the tuner 3 is connected via a channel filter 4 to an amplifier 5, whose output is connected to an analogue/digital converter (ADC) 6. The ADC 6 and the circuit blocks 7 to 16 constitute a demodulator, for example of the quadrature amplitude modulation (QAM) type. Although shown separately for clarity of explanation the stages 2,4 and 5 actually constitute part of the tuner 3.

The output of the ADC 6 is connected to a down conversion and filtering stage 7 whose output is connected to a timing recovery arrangement 8 which includes a matched filter.

The output of this arrangement is connected via an equaliser 9 to an arrangement 10 comprising a carrier recovery and coherent automatic gain control (AGC) arrangement 11 and a mean square error (MSE) estimator (or signal to noise ratio (SNR) estimator) 12. The output of the arrangement 10 is connected to an arrangement 13 comprising an error correction module 14 for performing error correction, which may include turbo decoding, TrellisNiterbi decoding and Block/Reed-Solomon (RS) decoding. The module 14 may be arranged to provide a bit error rate (BER) estimator 15. The demodulator also comprises a hardwired state machine or a software-controlled microcontroller 16 which performs demodulator acquisition and tracking control.

The receiver comprises an AGC controller 17 having an input connected to the output of the ADC 6 and separate outputs supplying signals X A, X B and X-C for controlling the gain of the attenuator 2, the tuner 3 and the amplifier 5, respectively.

In use, the input 1 receives all of the channels supplied by the cable distribution system and this broadband signal is attenuated by the attenuator 2 in accordance with the gain control signal X A from the AGC controller 17. The resulting signal is supplied to the tuner 3, which comprises a plurality of stages, generally including one of more frequency changers and one or more stages whose gains are controllable in accordance with the gain control signal X-B. The tuner 3 selects one of the channels available at the input 1 for reception and supplies this at an intermediate frequency to the channel filter 4 which passes the selected channel and substantially rejects other channels. The amplifier 5 compensates for the insertion loss of the filter 4 and its gain is controlled by the gain control signal X C.

The ADC 6 converts the selected channel at intermediate frequency to a corresponding digital signal, the remainder of the demodulator operating in the digital domain. QAM demodulators are well known and described, for example, in"Practical blind demodulators for high order QAM signals"by J. R. Treichler, M. G Larimore and J. C.

Harp, Proceedings of the IEEE, Vol. 86, No. 10, October 1998, pp. 1907-1926. Other demodulation techniques may be used, such as those disclosed in digital terrestrial

television (ETSI standard EN 300 744, v. 1. 3. 1 (2000-08)) and digital audio broadcast reception (ETSI standard EN 300 401 vl. 3. 2 (2000-09)). In some modulation schemes, for instance in digital terrestrial television, a pilot tone is transmitted and demodulated by the demodulator. In such cases, a measure of the signal-to-noise ratio may be derived or estimated from the demodulated pilot tone. Detailed operation of the demodulator will not, therefore, be described in detail. The demodulator signal is supplied in the form of digital data at the output of the arrangement 13 and may, for example, comprise a television signal.

The AGC controller 17 is shown in more detail in Figure 2 of the accompanying drawings and comprises an average square-value arrangement 20 so as to determine the average power of the signal at the output of the ADC 6. Possible alternatives include finding the average amplitude and determining a value based on signal statistics, such as minimum, maximum, mean value and mean square value. The average value is compared with a reference in a subtractor 21 and the difference is supplied to an arrangement 22 for forming a non-linear function, such as a logarithmic function, of the difference. The resulting signal is supplied to a multiplier 23 where it is multiplied by a parameter K for controlling the settling time of automatic gain control in the receiver.

The output of the multiplier 23 is supplied to low pass filter 24 which forms a signal X as a monotonically increasing function of the difference between the actual signal level and a required signal level at the input of the ADC 6.

The signal X is supplied to the inputs of three modules 25,26 and 27, which generate the control signals XC, XB and XA using the algorithm shown in Figure 4.

Although the total gain of the receiver and of the individual gain-controlled stages may be set to any desired initial value, it is assumed in the algorithm description below that all the gains are set to their maximum values initially. It is also assumed that the gain of the individual stages are reduced (attenuation increased) with increasing values of the respective gain control signals XA, B and XC. Hence the values of X~A, ~B and XC are initially at their minimum values. In practice, the gain of the amplifier 5 may be set to a mid-range initial value instead of maximum, but this does not alter the algorithm description given below.

Figure 3 shows the way in which the attenuation control signals of the three stages should ideally be set with reference to the signal Y at the input of the receiver. This shows that the attenuation in the tuner 3 is increased only when the attenuation in the amplifier 5 is at a maximum. Similarly, the attenuation of the attenuator 2 is increased only when the attenuation in the tuner 3 is at a maximum.

However, the gain control circuit 17 does not have access to the input signal level Y.

Hence it cannot base its AGC control algorithm directly on Figure 3. The AGC control circuit 17 only has access to the signal at the ADC 6.

The demodulator gain control algorithm is described using the flow diagram in Figure 4, which comprises three identical (and interconnected) vertical segments. The leftmost segment corresponds to the X~C~GEN circuit 25 of Figure 2. This outputs a signal [CB] to the middle segment and receives a signal [BC] from the middle segment, which corresponds to the X~B~GEN circuit 26 of Figure 2. The signals [CB] and [BC] are also shown in Figure 2. The rightmost segment of Figure 4 corresponds to the XAGEN circuit 27 of Figure 2.

At the start, when XA, XB and XC are at their minimum values, the ADC output is very likely to be greater than the reference. If this is not the case, then the AGC loops cannot bring the ADC output to the reference level.

To achieve optimum performance, the demodulator begins by increasing the attenuation of the amplifier 5 which is the last in the chain. The increment or

decrement operations shown for XC in Figure 4 can be achieved by adding the signal X to XC. If the error signal X becomes very small (less than a small threshold) before XC reaches its upper limit, then the AGC loops have settled and there is no need for any adjustments in 3 or 2.

However, ifXC reaches its upper limit XCMAX before X approaches zero, then XC is held at this value and XB is increased. IfXB reaches its upper limit XBMAX, then XB is held at this value and XA is increased. Hence the attenuation of the attenuator 2 is increased only if it is not possible to bring the signal level at the ADC 6 down to the required level with minimum gain settings in the amplifier 5 and the tuner 3.

When the AGC loop has settled, if there is subsequently a drop in the signal level, then XA is decreased first. IfXA reaches XAMIN then XB is decreased. IfXB also reaches its lower limit ofXBMIN, then XC is decreased.

As shown in Figure 4, a step 34 initialises the values of the gain control signals XA, XB and XC to the minimum values XAMIN, XBMIN and X~C~MIN,

respectively. At a step 35, XC is compared with its maximum value XCMAX and, if less than the maximum value, a step 36 determines whether XC is greater than its minimum value XCMIN. If not, XC is set equal to XCMIN and control returns to the step 35. Otherwise, a step 37 determines whether the signal X is greater than zero.

If not, a step 38 decrements X-C and control returns to the step 35. Otherwise, XC is incremented at 39 and control returns to the step 35.

If the step 35 determines that X C is not less than its maximum value, XC is set to its maximum value and a step 40 compares XB with its maximum value XBMAX. If XB is less than its maximum value, a step 41 compares it with its minimum value X B MIN. If XB is not greater than its minimum value, it is set to its minimum value and control returns to the step 35. Otherwise, a step 42 determines whether X is greater than zero and, if not, a step 43 decrements X-B and control returns to the step 40.

Otherwise, XB is incremented at a step 44 and control returns to the step 40.

If the step 40 determines that XB is not less than its maximum value, it is set to its maximum value and a step 45 compares XA with its maximum value XAMAX. If XA is not less than its maximum value, it is set to its maximum value and control returns to the start of the step 45. Otherwise, a step 46 compares X-A with its minimum value XAMIN and, if greater, a step 47 determines whether X is greater than zero. If not, a step 48 decrements XA and control returns to the step 45.

Otherwise, a step 49 increments XA and control returns to the step 45.

If the step 46 determines that XA is not greater than its minimum value, it is set to its minimum value and control returns to the step 40.

Thus the gain of the most down-stream gain-controlled circuit 5 is initially controlled so as to reduce the receiver gain in the presence of a larger than required signal in the selected channel. If it is not possible to bring the signal at the ADC 6 down to the required value with minimum gain in the amplifier 5, the one or more stages within the tuner 3 whose gains are controllable are then controlled. Again, if the gain range of tuner 3 is insufficient to achieve the desired signal level, then finally the attenuation provided by the attenuator 2 is controlled. Figure 4 also shows the way in which gains are controlled if there is a subsequent reduction in the input signal level. The attenuation of the attenuator 2 is reduced (if it is above the minimum) before the gain of the tuner 3 is increased. The gain of the amplifier 5 is increased only if it is not possible to increase the signal level at the ADC 6 to the required value with the gain of the tuner 3 at its maximum.

This type of gain control strategy is appropriate where the stages of the receiver upstream of the ADC 6 have substantially linear transfer characteristics so that additive noise is the main source of signal degradation. It is therefore desirable that attenuation at the input i. e. the attenuator 2, should be held to a minimum in order to ensure the optimum noise performance. In particular, assuming that the attenuator 2 does not generate any substantial noise, all noise degradation will occur between the attenuator 2 and the ADC 6 so that maximising the gain of the attenuator 2 provides the best signalnoise performance of the receiver.

According to the invention, there is provided a radio frequency receiver for receiving digital signals, comprising a tuner for selecting a desired channel for reception, a demodulator for demodulating a signal in the desired channel and for determining at least one quality of the demodulated signal, and a first controller for controlling the gain of at least one first stage of the tuner in accordance with the at least one quality.

The at least one quality may comprise a measure of signal to noise plus distortion. The demodulated signal may include a pilot tone and the measure may be derived from the pilot tone.

The at least one quality may comprise at least one measure of error in the demodulated signal. The at least one measure may comprise the bit error rate. The digital signals may be quadrature amplitude modulated signals and the at least one measure may comprise the mean square error.

The at least one first stage may comprise a single stage of the tuner.

The at least one first stage may comprise the input stage of the tuner.

The at least one first stage may comprise an attenuator.

The at least one first stage may be connected to the input of a first or a single frequency changer of the tuner.

The first controller may be arranged to vary the gain of the at least one first stage so as to improve the at least one quality. The first controller may be arranged to vary the gain of the at least one first stage until a maximum in the function of quality against gain is achieved. The first controller may be arranged initially to decrease the gain until the maximum is achieved. The first controller may be arranged to vary the gain by discrete steps, to determine a change in the at least one quality before and after each at least one of the steps, and to stop varying the gain when the magnitude of the change is less than a predetermined value.

The first controller may be arranged to decrease the gain of the at least one stage to a minimum gain at which the at least one quality is greater than or equal to a minimum acceptable quality.

The first controller may be disabled during an acquisition mode of the demodulator and may be enabled during a subsequent tracking mode of the demodulator. The first controller may be enabled periodically during the tracking mode. The first controller may enabled whenever the at least one quality falls below a predetermined value. The tuner may be arranged to have a maximum gain at the start of the acquisition mode.

The receiver may comprise a second controller for controlling the gain of at least one second stage of the tuner in accordance with a signal level within the receiver. The demodulator may comprise an analog/digital converter and the second controller may be arranged to control the gain of the at least one second stage so as to maintain a desired signal level at the input of the converter. The at least one second stage may comprise the at least one first stage and at least one further stage of the tuner. The second controller may be arranged to be prevented from controlling the gain of the at least one first stage whenever the first controller is enabled.

Any non-linearalities in the transfer characteristics of stages within the tuner, such as frequency conversion stages, create intermodulation products because of intermodulation between different channels which are present in the broadband signal at the input of the tuner. Some of these intermodulation products may occur in the same frequency band as the desired channel and are thus capable of affecting performance, such as, increasing the MSE value and BER. It has been found that these problems can be reduced or overcome by controlling the receiver gain on the basis of the quality of the demodulated signal, such as the MSE and/or BER. By reducing the gain upstream of any stage which has a substantially non-linear transfer function, such as a frequency changer, such intermodulation products can be reduced so that receiver performance can be improved as compared with automatic gain control based on stabilising a signal level at some point within the receiver.

Provided the receiver performance upstream of a digital demodulator exceeds a minimum performance, the actual performance of the receiver does not improve for increased signal level. This may be used to reduce the performance of the receiver to or near to the minimum level which provides proper demodulation and this in turn allows the power consumption of the receiver to be reduced while maintaining acceptable performance. Thus, by automatically controlling gain based on the quality of the demodulator signal, receiver performance may be optimised or power consumption may be minimised for acceptable performance. It may be convenient for optimisation to take place first followed by the strategy for reducing power consumption.

The invention will be further described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a block circuit diagram of a receiver illustrating known automatic gain control techniques: Figure 2 is a block circuit diagram of an AGC controller of the receiver of Figure 1; Figure 3 is a graph of attenuation control signals against input signal level of the receiver of Figure 1;

Figure 4 is a flow diagram illustrating the AGC strategy used in the receiver of Figure 1 ; Figure 5 is a block circuit diagram of a receiver constituting an embodiment of the invention ; Figure 6 is block circuit diagram of part of the AGC arrangement of the receiver of Figure 5; Figure 7 is a flow diagram illustrating an AGC strategy for optimising performance of the receiver of Figure 5; and Figure 8 is a flow diagram illustrating an AGC strategy for minimising power consumption of the receiver of Figure 5.

Like reference numerals refer to like parts throughout the drawings.

The receiver shown in Figure 5 is similar to that shown in Figure 1. Those parts of the receiver of figure 5 which have already been described with reference to Figure 1 will not therefore be further described.

The receiver of Figure 5 differs from that shown in Figure 1 by the provision of an AGC controller 18 and a summer 19. The summer 19 adds the gain control signal X A from the AGC controller 17 to a gain control signal DELTA from the AGC controller 18 and supplies the sum as the gain control signal X-D to the attenuator 2. The AGC controller 18 derives the gain control signal DELTA on the basis of the mean square error (MSE) (and/or the signal to noise ratio (SNR) ) and the bit error rate (BER) as supplied by the estimators 12 & 15. The controller 18 also receives a signal from the arrangement 16 to indicate whether the demodulator is in an acquisition mode, during which it is attempting to lock onto a signal, or in a tracking mode such that demodulator lock has been achieved and the signal is being demodulated by the demodulator.

During the acquisition mode, there is no valid mean square error or bit error rate from which the controller 18 can derive the gain control signal so that, during this mode, the control signal DELTA is set to zero and automatic gain control is performed on the basis of the signal level at the output of the ADC 6 as describe hereinbefore with reference to Figure 1. When the acquisition mode has been successfully completed and the demodulator is operating in the tracking mode, the controller 18 supplies the signal DELTA to the summer 19. In this mode, it is necessary to prevent the attenuation control signal XA from overriding the addition of DELTA, and to ensure that the X~B and/or XC are modified appropriately to compensate for the DELTA increase in XA.

When DELTA (which is usually positive, but is allowed to be negative) is added to XA, to compensate for this k. DELTA is subtracted from X~B and the module XBGEN 26 is activated. The factor k accounts for the difference in voltage vs attenuation slopes of A and B. If the slopes are the same, then k is equal to one. The

value ofk is approximated by the ratio of the above two slopes.

When there is an incremental change in the value of DELTA, i. e. when it is modified from (DELTA old) to (DELTAnew), the values ofXD and XB are changed as follows : XD = XA + DELTAjnew [or XD < -XD + (DELTA~new-DELTA~old] XB < -XB-k. (DELTAnew-DELTApld) Because of the change to XJB, the XBGEN module takes over the AGC control and hence does not allow the XAGEN module to negate the effect of change in DELTA.

If the above equation takes XB below XBMIN, then control is passed to XC.

Hence XB and XC appropriately compensate for the DELTA increment ofXA.

This arrangement prevents XA control from overriding the DELTA change, but does not restrict the operation of the AGC control circuit 17. Hence the AGC control can respond to changes in signal levels in the normal way with or without the addition of DELTA. Since XB is decreased when XA is increased by a DELTA change, the signal level at the ADC 6 is held substantially unchanged, thus minimising or reducing disturbance to the demodulator.

Subsequently, if there is a drop in the signal level, then XA, XB and XC will be adjusted as described in flow diagram of Figure 4 to bring the ADC signal level to the required value. However, limit checks should not be performed on both XA and XD.

Hence when the DELTA value is added, the limit check on XA is abandoned and the only limit check is on XD. Actually, the limits XDMIN and XDMAX are the same as XAMIN and XAMAX, as these apply to the same attenuator. Figure 6 shows the limit checks being done after the addition of DELTA by a circuit 32 and the control back to XBGEN which occurs as a result of these limit checks. This circuit is equivalent to that shown in Figure 2 when DELTA is zero, so that AGC control can begin without DELTA and include DELTA when the demodulator is switched to the tracking mode.

Figure 7 illustrates the control strategy of the AGC controller 18 during the tracking mode of the demodulator. This assumes that the appropriate gain structure has already been established by the controller 17 during the acquisition mode so as to achieve the desired signal level at the input of ADC 6. As mentioned hereinbefore, during the acquisition mode, the signal DELTA is set to zero. The strategy illustrated in Figure 7

is entered at A and a step 50 tests whether the signal X D supplied to the attenuator 2 is less than the upper bound or limit value X D MAX. If not, the strategy is stopped at 51 because the attenuator 3 is set to its maximum attenuation. Otherwise, a step 52 increments the value DELTA by an increment delta. The attenuation of the attenuator 2 is thus incrementally increased and a step 53 compares the effect of this on the MSE or the BER. It is necessary to store the previous value of the BER or MSE in order to perform the comparison. Also, the test performed by the step 53 should be delayed with respect to completion of the step 52 because the change in attenuation by the attenuator 2 may increase BER or MSE during a transition period. Also, in the case of a QAM demodulator, the performance continues to improve after demodulator lock has been achieved because of training of the equaliser 9. Thus, no measurements of BER or MSE should be made until the values have first stabilised after lock has been achieved.

The value of delta has to be made small so as to prevent the demodulator from loosing lock. It is therefore possible that a single increment of relatively small size may not give rise to a measurable change in BER or MSE. Thus, the step 52 may be repeated several times with an appropriate pause in between each such step so as to prevent loss of lock, after which the step 53 may be performed.

The step 53 measures the error value (BER or MSE) resulting from the change in attenuator gain performed in the step (or steps) 52 and compares this with the previous error value. In particular, if the absolute value of the difference between the consecutive error values is less than a predetermined threshold, the step 53 indicates that the error values are the same. The step 54 thus stops the algorithm for the time being but this algorithm may be subsequently reactivated, for example periodically.

If the step 53 determines that the error value has been reduced, control returns to the step 50. The steps, 50,52 & 53 are then repeated until the signal X D reaches its upper bound or limit X D MAX, until the maximum demodulated signal quality and hence minimum error value are achieved, or until the test 53 detects an increase in the error value.

If an increase in an error value is detected, a step 55 compares the gain control signal X D with its minimum or lower bound X D MIN. If the control signal reaches its lower limit, the algorithm is stopped at 56. Otherwise, the signal DELTA is decremented by the amount delta at 57 (which may be repeated as described hereinbefore for the step 52) and a step 58 performs the same test as the step 53. If the error value has not changed, control passes to the step 54. If the error value has been reduced as a result of decrementing the control signal to the attenuator 2 and hence reducing its attenuation (increasing its gain), control returns to the step 55, and the steps 55,57 and 58 are repeated. If the error value has increased, control returns to the step 50. The steps 55,57 and 58 are thus repeated until the signal X D reaches its minimum limit or bound, until there is no change in the error value or until the error value increases.

The control strategy illustrated in Figure 7 results in an optimisation of the tuner performance and, in particular, an optimisation of the demodulated signal quality by minimising the BER or MSE (or maximising the SNR). As an alternative to this strategy or subsequent to this strategy, the attenuation or gain of the attenuator 2 may be controlled so as to minimise the gain ahead of the tuner 3 while maintaining acceptable demodulator performance. A strategy for achieving this is illustrated in Figure 8, where the strategy of Figure 7 is indicated at Figure 9 as having achieved optimisation. A step 60 compares the BER with the required BER which represents the maximum acceptable error rate for quasi-error-free output of the receiver. If the actual BER is not significantly less than the required BER, the control strategy is stopped at 61.

Otherwise, a step 62 tests whether the value of the control signal X-D is less than its maximum limit value. If not, the strategy is stopped at 63. Otherwise, a step 64 increments the value of DELTA by the increment delta and control returns to the step 60. The steps 60,62 and 64 are then repeated until the gain of the attenuator 2 is reduced to the point where the actual BER is acceptable by a predetermined margin with respect to the required BER or until the control signal supplied to the attenuator 2 reaches its maximum value.

The strategy illustrated in Figure 8 thus has the effect of reducing the gain ahead of the tuner 3 as much as possible while maintaining the quasi-error-free output and hence operation of the receiver. By minimising this"front-end"gain, it is possible to reduce the power consumption of the receiver. If the performance of the receiver subsequently falls below the acceptable performance, control may be passed to the control strategy shown in Figure 7, which would then be entered at the point B so as to re-optimise

receiver performance before if d receiver performance before, if desired, again minimising front-end gain so as to reduce power consumption.

Claims

CLAIMS: I A radio frequency receiver for receiving digital signals, comprising a tuner for selecting a desired channel for reception, a demodulator for demodulating a signal in the desired channel and for determining at least one quality of the demodulated signal and a first controller for controlling the gain of at least one first stage of the tuner in accordance with the at least one quality.
2. A receiver as claimed in claim 1, in which the at least one quality comprises a measure of signal to noise plus distortion.
3. A receiver as claimed in claim 2, in which the demodulated signal includes a pilot tone and the measure is derived from the pilot tone.
4. A receiver as claimed in any one of the preceding claims, in which the at least one quality comprises at least one measure of error in the demodulated signal.
5. A receiver as claimed in claim 4, in which the at least one measure comprises the bit error rate.
6. A receiver as claimed in claim 4 or 5, in which the digital signals are quadrature amplitude modulated signals and the at least one measure comprises the mean square error.
7. A receiver as claimed in any one of the preceeding claims, in which the at least one first stage comprises a single stage of the tuner.
8. A receiver as claimed in any one of the preceeding claims, in which the at least one first stage comprises the input stage of the tuner.
9. A receiver as claimed in any one of the preceeding claims, in which the at least one first stage comprises an attenuator.
10. A receiver as claimed in any one of the preceeding claims, in which the at least one first stage is connected to the input of a first or single frequency changer of the tuner.
11. A receiver as claimed in any one of the preceeding claims, in which the first controller is arranged to vary the gain of the at least one first stage so as to improve the at least one quality.
12. A receiver as claimed in claim 11, in which the first controller is arranged to vary the gain of the at least one first stage until a maximum in the function of quality against gain is achieved.
13. A receiver as claimed in claim 12, in which the first controller is arranged initially to decrease the gain until the maximum is achieved.
14. A receiver as claimed in claim 12 or 13, in which the first controller is arranged to vary the gain by discrete steps, to determine a change in the at least one quality before and after each at least one of the steps, and to stop varying the gain when the magnitude of the change is less than a predetermined value.
15. A receiver as claimed in any one of the preceeding claims, in which the first controller is arranged to decrease the gain of the at least one stage to a minimum gain at which the at least one quality is greater than or equal to a minimum acceptable quality.
16. A receiver as claimed in any one of the preceeding claims, in which the first controller is disabled during an acquisition mode of the demodulator and is enabled during a subsequent tracking mode of the demodulator.
17. A receiver as claimed in claim 16, in which the first controller is enabled periodically during the tracking mode.
18. A receiver as claimed in claim 16 or 17, in which the first controller is enabled whenever the at least one quality falls below a predetermined value.
19. A receiver as claimed in any one of the preceding claims, comprising a second controller for controlling the gain of at least one second stage of the tuner in accordance with a signal level within the receiver.
20. A receiver as claimed in claim 19, in which the demodulator comprises an analog/digital converter and the second controller is arranged to control the gain of the at least one second stage so as to maintain a desired signal level at the input of the converter.
21. A receiver as claimed in claim 19 or 20, in which the at least one second stage comprises the at least one first stage and at least one further stage of the tuner.