GB2370434A - Digital and analogue signal conversion - Google Patents

Digital and analogue signal conversion Download PDF

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Publication number
GB2370434A
GB2370434A GB0031059A GB0031059A GB2370434A GB 2370434 A GB2370434 A GB 2370434A GB 0031059 A GB0031059 A GB 0031059A GB 0031059 A GB0031059 A GB 0031059A GB 2370434 A GB2370434 A GB 2370434A
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GB
United Kingdom
Prior art keywords
digital
analogue
signal
node
signals
Prior art date
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Withdrawn
Application number
GB0031059A
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GB0031059D0 (en
Inventor
Mel Long
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Aeroflex Cambridge Ltd
Original Assignee
Ubinetics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ubinetics Ltd filed Critical Ubinetics Ltd
Priority to GB0031059A priority Critical patent/GB2370434A/en
Publication of GB0031059D0 publication Critical patent/GB0031059D0/en
Publication of GB2370434A publication Critical patent/GB2370434A/en
Withdrawn legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/02Reversible analogue/digital converters
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12Analogue/digital converters
    • H03M1/50Analogue/digital converters with intermediate conversion to time interval
    • H03M1/56Input signal compared with linear ramp

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mobile Radio Communication Systems (AREA)

Abstract

DAC 10 is used to perform both analogue to digital, and digital to analogue, conversion. Digital signals to be convened into analogue signals are supplied to node a, passed through DAC 10 and supplied to node d as analogue signals. Analogue signals to be converted to the digital domain are supplied to node f. A digital estimate of the signal at f is provided to node a and converted to an analogue signal which is presented at node c. The signals at c and f are compared at comparator 12. The comparator output at node e is monitored as the digital input at node a is varied so that the digital input at node a can be adjusted to provide an adequate estimate of the analogue signal input at f. The final estimate is extracted from the input to DAC 10 at b.

Description

DIGITAL AND ANALOGUE SIGNAL CONVERSION The invention relates to the conversion of analogue signals to digital signals, and vice versa.
It is known to provide a wireless signals communications device, such as a mobile telephone, with a section that processes digital signals and a section which handles analogue signals. The analogue section can be thought of as the interface between the device's antenna for receiving and transmitting signals and the digital section which produces the data to be transmitted and recovers the data which has been received.
Conventionally, such wireless signals communications devices comprise digital to analogue converters (DACs) and analogue to digital converters (ADCs). The DACs handle signals transferred from the digital section to the analogue section for conditioning and transmission from the device, whereas the ADCs handle signals received at the antenna which have been conditioned by the analogue section and which are now being transferred to the digital section.
An aim of the invention is to provide enhanced apparatus for transforming signals between the analogue and digital domains.
According to one aspect, the invention provides apparatus for converting digital signals into analogue signals and vice versa, comprising digital and analogue inputs, digital and analogue outputs, means for converting a digital input signal from the digital input into an analogue output signal and providing it to the analogue output, means for comparing the analogue output signal with the analogue input signal, means for adjusting the digital input signal to cause the comparing means to attain a desired comparison result, and means for providing the digital input signal to the digital output.
Thus, the invention provides that elements used for digital to analogue conversion can be re-used for analogue to digital conversion. This may be of use in providing for analogue to digital conversion of signals where an ADC is not available, or where it is not desirable to use an ADC. The invention may provide the benefit of reducing the size of the ADC and DAC taken together which provides an economy particularly when the ADC and DAC are implemented in an integrated circuit.
In one embodiment, the adjusting means changes the digital input signal with a uniform gradient. In another embodiment, the adjusting means changes the digital input signal with a gradient that changes sign and reduces in magnitude each time the analogue input signal crosses the analogue output signal's value. Where the initial gradient is large, the latter alternative provides for rapid convergence of the analogue output signal with the analogue input signal's value.
The invention may be used in wireless signals communications apparatus to provide for the conversion to the digital domain of signals received at the apparatus and conversion to the analogue domain of signals to be transmitted from the apparatus. In one embodiment, there is a plurality of the signal conversion apparatus within the wireless signals communications apparatus, each signal conversion apparatus operating on a different (component of a) signal being handled by the wireless signals communications device.
By way of example only, certain embodiments of the invention will now be described, with reference to the accompanying Figures, in which: Figure 1 is a block diagram of a signal converter; Figure 2 is a block diagram of a mobile telephone utilising the signal converter of Figure 1; Figure 3 is a graph describing a comparison process performed by the signal converter of Figure 1; Figure 4 is a graph describing another comparison process that can be performed by the signal converter of Figure 1; and Figure 5 is a block diagram of a mobile telephone using an arrangement'of signal converters. The circuit 1 of Figure 1 comprises a DAC 10 enabled for performing analogue to digital conversion in addition to digital to analogue conversion.
To perform digital to analogue conversion, a digital signal is provided to node a and is operated on by DAC 10 to produce an analogue signal which is presented to node d.
The circuit 100 can also perform conversion to the digital domain of analogue signals presented to node f, as follows. An estimate of the digital value corresponding to the analogue signal at f is presented to node a. DAC 10 outputs an analogue signal corresponding to the digital signal at a. The output of DAC 10 is sampled at node c and provided to an input of comparator 12. The other input of comparator 12 receives the signal from node f. The output from comparator 12 is presented to node e. The signal at node e adopts a low value when the signal at node c is lower than the signal at node f.
When the signal at node f is higher than the signal at node c, then the signal at node e adopts a high state.
To provide a digital estimate of the signal at f, the value of the digital signal applied to node a is varied and the comparator output, at node e, is monitored. When the signal at node a provides a digital estimate of the signal at fto a desired degree of accuracy, then the value supplied at node a is tapped off at node b to provide a digital approximation of the analogue signal supplied to node f.
There are many ways of varying the node a signal and monitoring the node e signal in order to arrive at the digital approximation of the signal at f. Two such methods will now be described with reference to Figures 3 and 4 respectively.
Figure 3 shows two plots, a plot of voltage against time (and showing the node c signal 18 and the node f signal 20) and a plot of the node e signal, Se, against time. The signal 20 is assumed to be constant for the duration of the estimation process. This is achieved by providing successive constant increments to the digital signal applied to node a. As seen in the voltage plot, the signal 18 increases with a constant gradient. At time ti, the signals 18 and 20 cross, and the output of the comparator, at node e, changes from its low state (shown as 22 in the Se plot of Figure 3) to its high state (shown as 24 in the Se plot of Figure 3). The digital value of the signal at node a at time tl is taken to be the digital approximation of the analogue signal supplied to node f.
Figure 4 similarly shows a plot of voltage against time (for the node f signal 20 and the node c signal 18) and a plot of the signal at node e, Se, against time. Again, the analogue node f signal is assumed to remain constant for the duration of the duration of the estimation process. In the approximation method illustrated in Figure 4, the node c signal 18 is produced by incrementing the node a digital value by successive, constant, and relatively large increments so that it quickly crosses the signal 20 at t2. Thereafter, the node c signal 18 is decreased by applying successive and constant decrements to the node a signal. The decrements used are one half the magnitude of the increments previously used.
When the signal 18 again crosses signal 20 at t3, then the signal 18 is incremented using constant, successive increments of one half the magnitude of the decrements previously employed.
This procedure continues with the decrements and increments being halved each time signal 18 crosses signal 20 until a predetermined number of crossing events of the signals 18 and 20 has occurred, at time t4. The predetermined number of crossing events is chosen to provide a desired degree of accuracy in the approximated digital signal. The larger the number of crossing events, the more accurate the digital estimate (but the longer the estimation time becomes). It will be seen from Figure 4 that, by choosing an appropriate value for the initial increment of the node a signal and an appropriate value for the number of crossing events, the approximation time can be reduced relative to the Figure 3 method, i. e. ts is less than ti Figure 2 illustrates the incorporation of the circuit 1 in a mobile telephone 15. The circuit 1 provides an interface between the digital section 14 and the analogue section 16 of the mobile telephone 15. Digital signals produced by digital section 14 for transmission from the mobile telephone 15 are supplied to node a and are processed by circuit 1 which delivers the corresponding analogue signal to node d which, in turn, is conditioned in analogue section 16 and supplied to an antenna 18 for transmission from the mobile telephone 15. Analogue signals received on antenna 18 are conditioned by analogue section 16 and supplied to circuit 1 via node f. The digital section 14 varies the value supplied to node a (e. g. in the manner described with reference to Figure 3 or 4) and monitors the comparator feedback at node e to produce a digital approximation of the signal at node f which is extracted by the digital section 14 at node b. It will be apparent that the mobile telephone 15, using circuit 1, cannot undertake simultaneous transmission and reception since the DAC 10 in circuit 1 is required in both transmission and reception.
It will be apparent to the skilled person that several signal conversion circuits can be provided, one for each component of a multi-component signal handled by the mobile telephone 15. For example, when the mobile telephone 15 handles signals having I and Q components, the mobile telephone 15 can have a digital approximation circuit 1, 1'in each of the I and Q channels, as shown in Figure 5.

Claims (9)

  1. CLAIMS 1. Apparatus for converting signals between the digital and analogue domains, comprising digital and analogue inputs, digital and analogue outputs, means for converting a digital input signal from the digital input into an analogue output signal and providing it to the analogue output, means for comparing the analogue output signal with the analogue input signal, means for adjusting the digital input signal to cause the comparing means to attain a desired comparison result, and means for providing the digital input signal to the digital output.
  2. 2. Apparatus according to claim 1, wherein the adjusting means changes the digital input signal with a uniform gradient.
  3. 3. Apparatus according to claim 1, wherein the adjusting means changes the digital input signal with a gradient that changes sign and reduces in magnitude each time the analogue output signal crosses the analogue input signal's value.
  4. 4. Apparatus according to any one of claims 1 to 3, arranged such that it can perform only one of digital to analogue and analogue to digital conversion at any given time.
  5. 5. Communications apparatus comprising the signal converting apparatus of any one of claims 1 to 4, wherein the digital input signal is digital data to be transmitted from the communications apparatus, and the analogue input signal is a signal transmitted to the communications apparatus.
  6. 6. Communications apparatus according to claim 5, comprising a plurality of converting apparatus as claimed in any one of claims 1 to 4, each for operating on a separate component of signals being handled by the wireless signals communications apparatus.
  7. 7. Communications apparatus according to claim 5 or 6, adapted for serial transmission and reception of wireless signals.
  8. 8. Apparatus for converting signals between the analogue and digital domains, substantially as hereinbefore described with reference to the accompanying Figures.
  9. 9. Communications apparatus, substantially as hereinbefore described with reference to the accompanying Figures.
GB0031059A 2000-12-20 2000-12-20 Digital and analogue signal conversion Withdrawn GB2370434A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB0031059A GB2370434A (en) 2000-12-20 2000-12-20 Digital and analogue signal conversion

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB0031059A GB2370434A (en) 2000-12-20 2000-12-20 Digital and analogue signal conversion

Publications (2)

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GB0031059D0 GB0031059D0 (en) 2001-01-31
GB2370434A true GB2370434A (en) 2002-06-26

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GB0031059A Withdrawn GB2370434A (en) 2000-12-20 2000-12-20 Digital and analogue signal conversion

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8576099B2 (en) 2012-02-03 2013-11-05 Avago Technologies General Ip (Singapore) Pte. Ltd. Digital-to-analog converter (DAC) with common mode tracking and analog-to-digital converter (ADC) functionality to measure DAC common mode voltage

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2048000A (en) * 1978-06-05 1980-12-03 Grass Valley Group Analogue-to-digital and digital-to-analogue conversion circuit
EP0797305A1 (en) * 1996-03-22 1997-09-24 STMicroelectronics S.r.l. Combined ADC-DAC

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2048000A (en) * 1978-06-05 1980-12-03 Grass Valley Group Analogue-to-digital and digital-to-analogue conversion circuit
EP0797305A1 (en) * 1996-03-22 1997-09-24 STMicroelectronics S.r.l. Combined ADC-DAC

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8576099B2 (en) 2012-02-03 2013-11-05 Avago Technologies General Ip (Singapore) Pte. Ltd. Digital-to-analog converter (DAC) with common mode tracking and analog-to-digital converter (ADC) functionality to measure DAC common mode voltage

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Publication number Publication date
GB0031059D0 (en) 2001-01-31

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