GB2370384A

GB2370384A - Shifter

Info

Publication number: GB2370384A
Application number: GB0031514A
Authority: GB
Inventors: Mark St John Owen
Original assignee: Cambridge Consultants Ltd; Alphamosaic Ltd
Current assignee: Cambridge Consultants Ltd; Broadcom Europe Ltd
Priority date: 2000-12-22
Filing date: 2000-12-22
Publication date: 2002-06-26
Anticipated expiration: 2020-12-22
Also published as: GB2370384B; GB0031514D0

Abstract

The invention is an N-bit shifter for receiving as its input a sequence of N bits x<SB>0</SB>....x<SB>N-1</SB> and for giving as its output a plurality of bits z<SB>0</SB>....z<SB>N-1</SB> representing a selected permutation transposition or rearrangement of the input bits, wherein the shifter comprises for each of the input bits (x<SB>0</SB>....x<SB>N-1</SB>) a pair of first and second multiplexers (14,15), each of which gives an output of a single bit to an associated output multiplexer (17) so that for an input bit x<SB>a</SB>(0 & a<N) the first multiplexer has as its inputs those bits of the input sequence which can be output by a left shift/rotate operation, the second multiplexer has as its input those bits of the input sequence which can be output by a right shift/rotate operation, and the output multiplexer has as its inputs the outputs of the first and second multiplexer, the original input bit x<SB>a</SB>, and a bit selected from one of the output bits of first and second multiplexers in accordance with the required permutation.

Description

SHIFTER

The present invention concerns what are known as shifters. These are devices which are widely used in digital signal processors (DSPs). Essentially a shifter receives an input sequence and rearranges the sequence in a predetermined manner. Thus in image processing, for example, it is frequently necessary to deal with rectangular blocks of data representing rectangular blocks of pixels. Useful operations on such blocks include shifts and rotations in the x-and y-directions, transposition and bit reversal in which the order of bits in the pixel indices are reversed in the x-and/or ydirections. However circumstances also occur where more complex permutations of sequences or blocks of data are required. As it will be appreciated the number of permutations which can be carried out on a sequence of numbers is the factorial of the length of the sequence the problems of providing a hard-core solution to generating complex permutations is very considerable. Accordingly the present invention is concerned with providing a shifter which enables an arbitrary permutation to be performed as a product of a reasonably small number of available shift operations.

Accordingly in a first aspect the present invention provides an N-bit shifter for receiving as its input a sequence of N bits oxo.... xi and for giving as its output a plurality of bits so.... ZN-l representing a selected permutation transposition or rearrangement of the input bits, wherein the shifter comprises for each of the input bits (x0.... Xni) a pair of first and second multiplexers, each of which gives an output of a single bit to an associated output multiplexer so that for an input bit xa (0a < N) the first multiplexer has as its inputs those bits of the input sequence which can be output by a left shift/rotate operation, the second multiplexer has as its input those bits of the input sequence which can be output by a right shift/rotate operation, and the output multiplexer has as its inputs the outputs of the first and second multiplexer, the original input bit xa, and a bit selected from one of the output bits of first and second multiplexers in accordance with the required permutation.

In order that the present invention may be more readily understood an embodiment thereof will now be described by way of example and with reference to the accompanying drawings, in which:

Figure 1 is a block diagram illustrating a shifter in a digital processor ; Figure 2 is a block diagram of part of the architecture of a shifter usable in the processor shown in Figure 1 and in accordance with an embodiment of the present invention; and Figures 3 and 4 are diagrams illustrating the operation of the shifter of Figure 2; Figure 5 is a block diagram illustrating the inputs and outputs to a 4-bit shifter ; Figure 6 is a block diagram of a complete 4-bit shifter according to the present invention; and Figures 7A, 7B and 7C are tables illustrating the operation of the shifter of Figure 5.

Referring now to Figure 1 of the accompanying drawings, this shows a DSP having a program memory 1 which contains the program being executed by the processor. Each instruction from the program memory activates and deactivates, via the links shown, the other units of the

processor so as to perform the correct operations on the data.

The data that the program is operating upon resides in a data memory 2 which sends data to the registers for subsequent processing and can also receive the data back once it has been successfully manipulated. Thus the data memory 2 is connected to registers 3 which are a holding area for data from the data memory from where it can be efficiently fed into the processing units for manipulation. The registers 3 also hold data that has been returned from the processing units, prior to

returning these to the data memory 2. e4--L. t-JL 14 Ll r A multiplexer 4 selects the appropriate registers the contents of which are to be passed on to a shifter 5 and from there on to an Authentic Logic Unit (ALU) 6, this being done under the control of the instruction currently being executed. The shifter 5 will be described in greater detail with regard to Figure 2.

The register values received from the multiplexer 4 by the shifter 5 can be transformed, shifted and permuted before being presented to the ALU 6. The shifter thereby removes the need for the processor to spend dedicated

time shifting and permuting data as this operation can happen as the data is passed through. It must be appreciated that a complete block diagram for a shifter dealing with more than 4 bits will be exceptionally complex. Accordingly a general discussion of the operation of an n-bit shifter will be given followed by a description of the 4-bit shifter of Figure 5.

As in any processor, ALU 6 performs arbitrary arithmetic and logical operations on the data received from the shifter in accordance with instructions from the program memory 1, and returns the result back to the registers.

As described so far the processor is entirely conventional.

Turning now to Figure 2 of the drawings this shows the architecture of one embodiment of a shifter in accordance with the present invention and which is used as the shifter 5 shown in block form in Figure 1. The architecture shown in Figure 2 is actually for dealing with a single bit and is thus only part of a complete shifter. Initially a general discussion will be

given in relation to shifters for acting on N bits where N=2n for some integer n. In a practical embodiment for handling blocks of video n might equal 6, with N=64 with the group of 64 bits representing pixels in an 8-by-8 square, or more generally from some 2k-by-2N- rectangle. Thus the block diagram of Figure 2 represents a one bit slice of a shifter for acting on N bits. The input to the shifter is shown at 10 and can be represented as x=xi, Oi < N. Each one-bit slice of the total shifter will of course receive this input. Accordingly the output of the slice of the shifter shown in Figure 2 is also a

single bit zi, where z=Oi < N.

.. 3-L-L JLL u-I Thus for N=64, that is N bits to be permuted, there will be 64 slices similar to that shown in Figure 2. Each of these slices receives as its input xi together with all the bits which could be shifted or permuted to zi. Thus for a N-bit shifter the input to each slice will be

2n+l bits in total. For a 4-bit shifter five bits will be entered at each slice and for an 8-bit shifter there will be 7 bits entered at each slice and so on. The slice of the shifter shown in Figure 2 operates in

its simplest procedure by interchanging (or not) the value of the input bit xi with one of the other bits Xi-N/2''--Xl+N/2. The basic shift amount is determined by a value k in a manner which will be described hereinafter and runs in powers of 2 from 20=1 to 2n=N/2.

In Figure 2 each of the bits associated with the slice is shown as being supplied to one input of an individual AND eight gate 11 over its own input line 12. In practice the number of AND-gates 11 per slice varies with regard to the position of the slice within the longitudinal array of the shifter. In order to understand the relationship between the number of AND-gates 11 and a slice of the shifter as shown in Figure 2 it has to be appreciated that an ANDgate 11 is only required when a bit from one end of the shifter is wrapped around to the other end. Thus when considering the indices of the bits being permuted for every bit with index i+N/2 where i+N/2N an AND-gate 11 is required at the right hand end of the slice.

Conversely wherein the bit index is i-N/2 where i-N/2 < 0 an AND gate 11 is required at the other end of the slice.

Thus there will be a patterned decrease in the number of AND-gates for any multi-bit shifter according to the

present invention from the outermost ends of each slice towards the middle of the slice. It is for this reason that a simple 4-bit shifter will be described in detail hereinafter in order to assist in the understanding of the shifter. It must accordingly be emphasised that the slice shown in Figure 2 is in essence generic rather than a practical embodiment as for every bit there is shown an associated AND-gate. The other input of each gate 11 is connected to a line 13

the input of which controls shift/rotate operations of L L the shifter. The outputs of the gates 11 to the left of input 10 are supplied to a multiplexer 14, and the outputs of the other gates are supplied to multiplexer 15. Each multiplexer 14,15 is adapted to select one of the outputs of the gates 11 connected to it in response to the value k thus setting the shift amount. Each multiplexer 14,15 supplies its output in parallel to a 2-1 multiplexer 16 and to a 4-1 multiplexer 17. The output of multiplexer 16 is also supplied to the 4-1 multiplexer 17. Multiplexer 17 also receives as an input bit Xi so that the input from multiplexers 14,15 and 16 together with xi provide four inputs from which zi is

selected.

Multiplexer 17 gives zi as its output in response to the output of an AND-gate 18. AND-gate 18 has two inputs, namely a control bit Yi and an input corresponding to the type of shift to be carried out. As there are four types of shifts, namely left shift/rotate and right shift/rotate, exchange and NO shift AND-gate 18 will in practise be realised as shown in Figure 2B. The AND-gates 11 and the line 13 enable the bits from xi- N/2 to Xi-l and xi, l to xi+N/2 to wrap around or not according to whether a rotate or a shift is wanted. In the slice shown multiplexer 16 receives on a control or select input which is the output of a multiplexer 19 which receives at its select input the value k.

Multiplexer 19 selects in response to k from a range of inputs shown as io, il, i2, ..... in-1. These inputs are the bits of number i written in binary. The multiplexer 19 is required for the exchange operation in which one of the initial input bits is to be exchanged with another of the input bits. In a practical shifter for each slice i will be known and

in a practical shifter such as the embodiment of Figure 6 i will always be known so that it can be supplied directly to multiplexer 16. At the extreme ends of the slice there is no need for multiplexer 16, as can be seen from the 4-bit shifter to be described hereinafter. The arrangement just described allows operations to be selected. These operations include: a) no shift b) left shift or rotate c) right shift or rotate d) exchange.

Simplified versions of these operations will be described in detail hereinafter with regard to the architecture shown in Figure 2. However a general analysis of the theory behind the operations available from the shifter will now be given as to give a key to the versatility of the shifter being described. Firstly general theory behind the exchange operation will be described.

Let n=3, N=8. Then the available exchange operations for k=O, 1, and 2, assuming all shifts are enabled in each

case are

k=O : (01) (23) (45) (67) k=1 : (02) (13) (46) (57) k=2: (04) (15) (26) (37) The notation used in what is known as the product of disjoint cycles. If it is assumed that wherever bits i and j are involved in the same transposition then Yi=Yj so that a permutation is generated, then the effect of the Yi can be included by writing: k=O : (01) α (23) 0 (45) Y (67) 3 k=1 : (02) a (13) (46) Y (57)' k=2: (04) α(15) (26)γ (37) # where each of the a, , y, and 5 can be either 0 or 1. As an example of how to generate more complex permutations from compositions of the available ones, consider the permutations no= (01) (23) (45) (67), #1= (02) (13) (46) (57) and n2= (04) (15) (26) (37). Now no ni il2= (01) (23) (45) (67) (01) (23) (45) (67) (04) (15) (26) (37) =

(07) (16) (25) (34), a left-to-right reversal of the bits.

For a more complex example, consider the two permutations no= (45) (67) and ni= (15) (37). The first permutation is a "k=O class"permutation witha= =0, y=S=l ; and the second

is a"k=2 class"permutation with c < =y=O, P=5=l. The commutator no-nino=nonlno= (45) (67) (15) (37) (45) (67) = (14) (36) which is the"bit reversal"permutation. Thus a bit reversal of eight points can be achieved in three operations: first with k=O, then with k=2, and finally with k=O again. The last example can be analysed as follows. Consider the action of a permutation n on the indices of the bits it is permuting. If n is in class k it inverts bit k of each index where the mask y so enables. If, for example, bit 0 of the index is inverted wherever bit 2 of the index is set, the effect is to exclusive-OR bit 2 of the index into bit 0 ; and this is exactly what no above does.

Likewise, #1 exclusive-ORs bit 0 of the index into bit 2. Writing ai for index bit i, the sequence #0#1#0 therefore

performs the following operations :

a0 ^ a2 ; a2=a2 ^ aO ;

A ao=ao ^ a2 ;

which, as is well known, exchanges index bits 0 and 2. It is easy to see how the method generalises to bit reversal for a word of length n in 3Ln/2j operations.

Another general operator can be called"select". This is a powerful shuffling operation. It is defined as follows: given an input word xi and a selector yi, the selection z=x: y is obtained by extracting those bits xi where yl and packing them at the least significant end of z. The remaining bits of z are set to zero. For example, let x=10? 1 ?? 10 and y=11010011 (with the most

significant bit at the left, and with" ?" representing a "don't care"value) ; then x : y=OOO10110.

"Select"can be implemented on the architecture of Figure 2 as follows. In general n steps are required, with k running over the values 0 to n-1 in sequence. The shift type is set to"right shift", and at each step some of the selected bits are moved closer to their destination locations. Writing d (i) for the ultimate destination position for bit i of x, bit k of the binary expansion of i-d (i) gives the information as to whether shifting must be enabled for a particular bit at step k,

and therefore allow us to generate a suitable sequence of y's. For example, consider the sequence required to calculate x: OOl0l00010101100, i. e. selecting bits 2,3, 5,7, 11 and 13 from an N=16-bit word. Here n=4, so four steps will be required. Figure 3 of the accompanying drawings shows what happens: as can be seen, y has a 1 where id (i) has bit k set; and that bit is shifted right by 2k places.

This particular example requires non-zero y for each of the four steps. Many more realistic permutations would have y=O for some steps; these steps can then of course be skipped. Note also that this example does not result in the more-significant bits of the result being zeroed. This can be achieved by appropriate setting of the more significant bits of the y's. It is important to verify that"clashes"can never arise during a select operation; in other words, it must not happen that two bits are ever temporarily stored in the same place. One way to show that this cannot happen is by induction on the word length N. Evidently clashes cannot occur in the case N=1. Now consider 2 < N < 2n, and

assume the induction hypothesis that clashes do not occur for any selection for word sizes smaller than N. Observing that the sequence i-d (i) is nondecreasing with i, and that precisely those bits with i-d (i) N/2 are shifted in the last step, where k=n-l, it can be seen that the procedure prior to the last step can be partitioned into two smaller selection procedures on words of sizes No and N1, where No+Nt=N, N0#2n-1 < N, and Ni2n-l < N. Because the rightmost bit of the left-hand partition moves n/2 places in the last step, while the leftmost bit of the right-hand partition can only move at most n/4+n/2+n/8+... +1=n/2-1 places in all previous steps, the two partitions cannot interact. Further, by the induction hypothesis, clashes cannot occur earlier in the procedure.

Another general operation can be referred to as"spread". This is, in a sense, the inverse of the select. Given an input word xi and a mask y, the spread z=x&num;y is obtained by unpacking the least-significant bits of x into those positions Zi where yi=l. The remaining bits of z are not defined. For example, if x=OOO10110 and y=11010011 (with most-significant bit at the left) then x&num;y=10X1XX10, where"X"indicates"not defined".

One spread operation can be implemented in a rather similar way to the"select"operation, the steps being carried out in the reverse order. Figure 4 shows an example complementary to that of Figure 3. If it is required to set the undefined bits of the result to zero, a further mask operation will be required. The potentially useful, and well-defined, result of replicating unpacked bits to the left and filling with zeros at the right (so the result in the example of Figure 4 would be"aaabbccccddeefOO") can be obtained by suitable modification to the control words y.

It is interesting to note the application of sorting algorithms in relation to the above discussion. The merge sort algorithm sorts any list of N items in O (log N) passes; thus any permutation can be obtained in O (log N)"unmerge"passes. An"unmerge"can be performed by two select operations (one for each of the two resulting lists), a shift and a logical OR. Each select operation requires O (log N) steps, and so the total number of steps is just O (log2N). Most permutations wanted in practice will require many fewer steps than this, but an arbitrary permutation can be got in a reasonable time.

If a faster general permutation is nevertheless required, it is possible to construct a cascade of O (log N) copies of the hardware shown, one for each value of k. Then a "select"could be carried out in a single step.

Referring now to Figure 5 of the drawings the block 30 represents a 4-bit shifter operating on the principles discussed with regard to the shifter of Figure 2. The four input bits are as before indicated at 10 with the subsequent input lines showing how the input bits are divided to each"slice"of the shifter.

It will be appreciated that in order to achieve a permute operation involving successive shift operations that either the outputs z0, zi, z2, z3 can be returned as new inputs 10, or instead the outputs Zo, Zit Z21 23 supplied as new inputs to another similar shifter identical to shifter 30. Thus a number of shifters can be cascaded if very rapid operation is required.

Turning now to Figure 6 this shows a 4-bit shifter. Integers common with Figure 2 have been given the same reference numerals. In the 4-bit shifter there are five inputs to each slice,

with each slice containing a pair of multiplexers 14, 15 giving their outputs to a multiplexer 17 the select input of which is connected to the output of an AND-gate 18.

Thus AND-gate of course operates as shown in Figure 2B.

As will be appreciated from the preceding description of the"generic"slice shown in Figure 2 the left and right ends of the shifter each have two AND-gates connected to the respective multiplexers 14,15. Similarly only the inner two slices have the additional multiplexer 16. The way in which the input values are manipulated within the shifter are illustrated in the diagrams of Figure 7. In the three diagrams of Figure 7 the first row of each diagram marked"INPUTS"corresponds to the four sets of inputs to the four slices of the 4-bit shifter of Figure 6.

The second row shows for each slice the inputs to the respective multiplexers 14 and 15. The third now shows the outputs of the multiplexers 14,15 together with the unchanged input bits. The fourth now shows the inputs to the respective multiplexers 17 and the final row the outputs of the multiplexer 17 which represent the requisite shift.

Claims

1. An N-bit shifter for receiving as its input a sequence of N bits Oxo.... XN-1 and for giving as its output a plurality of bits Zo.... Zi representing a selected permutation transposition or rearrangement of the input bits, wherein the shifter comprises for each of the input bits (x0....xN-1) a pair of first and second multiplexers, each of which gives an output of a single bit to an associated output multiplexer so that for an input bit xa (0 < a < N) the first multiplexer has as its inputs those bits of the input sequence which can be output by a left shift/rotate operation, the second multiplexer has as its input those bits of the input sequence which can be output by a right shift/rotate operation, and the output multiplexer has as its inputs the outputs of the first and second multiplexer, the original input bit Xa, and a bit selected from one of the output bits of first and second multiplexers in accordance with the required permutation.

2. A shifter according to claim 1, wherein each of said first and second multiplexers has a select input for selecting the output bit from the input bits, and wherein the select input is adapted to receive a control value representing the size of the shift, this control value

being 2k where for an N-bit shifter the range of values for the control value is 20 to 211-1 where N=2n.

3. A shifter according to claim 2, wherein for each of said pairs of first and second multiplexers there is associated at least one AND-gate in the input path of one of the input bits, and wherein the disposition of the

AND-gates is such that an AND-gate is present in an input of the multiplexer where a shift operation in one of the two directions shift would result always in a 0 bit input.

4. A shifter according to claim 3, wherein each ANDgate has one input connected to an input bit and another input connected to a control line which determines wherein the operation is a shift or a rotate.

5. A shifter according to claim 4, wherein the output of each output multiplexer is selected in accordance with the operation selected is a right shift or rotate, a left shift or rotate, an exchange or output the original bit (ra).

6. A shifter according to any preceding claim and further comprising a second shifter according to any one of the preceding claims the inputs of which are connected to the outputs of the first shifter.