GB2361857A - Data transmission circuit - Google Patents

Abstract

There is described a circuit for the serial transmission of digital data from a transmitter RS-485 to a receiver RS-485 via a cable CAT5. The outputs of the transmitter are connected to the cable via parallel RC circuits C<SB>tx</SB>, R<SB>tx</SB> which serve as passive circuit blocks, thereby eliminated pattern-related jitter. Zener diodes D<SB>tx</SB> may be used to protect the circuit from excessive transient voltages.

Description

470/84/P/GB 2361857 Title - Serial Communication System This invention

relates to a serial communication system, and in particular to such a system which allows high transmission rates over extended distances. More particularly, the present invention relates to improving the consistency of digital data transmissions over long cables and especially to reducing pattern-dependent jitter when such cables are used.

Digital data is typically transmitted between electronic devices such as telephones, fax machines, computers and the like, by simple electric cables. eg a pair of twisted wires. When such cables are used to transmit data over substantial distances (perhaps a few tens of metres or more), especially when the rate of data transmission is high, the cable itself becomes an important component of the overall system, in that its increasing resistance can result in data errors being introduced at the receiving end of the cable. Such errors depend on the particular sequence of pulses transmitted and the effect is therefore known as pattern-dependent jitter or skew. Skew is the difference in time for a transition from either LOW-to-HIGH or HIGH-to-LOW of a measured signal compared to the predicted value. Jitter is the variation in skew for one bit of the signal to another bit contained within the serial stream of data.

The transmission cable can be thought of as a single pair of wires connected to a transmitter which at any instant is imposing on one member of the pair a signal and on the other member of the pair a signalcomplement. The signal is binary and at any time one wire will have imposed on it by the transmitter either a HIGH signal or a LOW signal, while the complement of that signal is imposed on the other member of the pair. Of course, either wire can conduct either signal. The two wires are typically connected to a differential receiver for subsequent processing.

Under ideal transmission/reception conditions, the signals imposed at the transmission end of the line will be exactly reproduced at the receiver. This will be achieved if the rise-time and fall-time (for LOW-to-HIGH and HIGH-to-LOW transitions, respectively) of the voltage on the cable is extremely well defined and 470/84/P/GB 2 consistent. In practice, this means that these rise- and fall-times should be short in relation to the duration of the individual pulses making up the digital signal.

As transmission lines become longer, with a concomitant increase in their rise-time, and signal rates higher, with a concomitant decrease in pulse-width, it becomes increasingly more difficult to ensure that the signal seen at the receiver correlates perfectly to that imposed at the transmitter end of the cable, and does not depend on the particular pattern of HIGHs and LOWs transmitted.

One approach to this problem is disclosed in US 5,892,717. This document discloses a system in which a pair of opposing diode devices are present at the receiver end of the transmission line. The diode devices are each coupled across the pair of conducting wires that make up the transmission line. This is said to clamp the difference in potential between the two transmission lines so that the signal amplitude seen at the receiver will not vary too significantly with the number of like pulses that are transmitted in succession. However, the low resistance of the diodes will result in a considerable increase in power consumption, especially during idle operation.

UART (Universal Asynchronous Receiver Transmitter) systems are widely used for serial communication. The advantages of UART systems are the simplicity of interconnection wiring and character transmission protocols. Standard 16550 UART devices can provide transmission rates of up to 115. 2 Kb/s. However through recent developments, some high performance UART devices exist that can achieve a maximum speed of 10 Mb/s. The UART technology uses an oversampling technique for data recovery and this technique requires a higher operating frequency than the actual data transmission rate. However oversampling methods are easier and more economical to implement when compared to designs using a clock recovery method, especially in PLID (Programmable Logic Device) implementations. Clock recovery methods normally require special data encoding to carry clock information and a PILL (Phase Lock Loop) to synchronize the receiver clock for data recovery.

For high performance UART systems that require extended distance, differential transmission interfaces like RS-422/485 are desirable. These standard devices can 470184/P/GB 3 accommodate data transmission rates of 10 Mb/s at distances of up to 1 Orn, or data transmission rates of 10OKb/s at distances of up to 4km. Due to technological advances, new RS-485 transceivers offer the potential to transmit at faster speeds.

Nevertheless, there is always a constraint of maximum data transmission rate versus maximum distance relative to the interface circuit configuration. As the signal propagates along the communication medium, signal quality deteriorates. Signal attenuation and skew increase as a function of distance and signal speed. With the straightforward framing method of the UART protocols, some characters produce an unbalanced 1 and 0 bit pattern. This unbalance bit stream has proved to be the main factor contributing to the signal skew as the distance increases.

There has now been devised an improvement to a serial communication system which overcomes or substantially mitigates the above-mentioned or other disadvantages of the prior art.

According to the invention, there is provided a circuit for the transmission of data, the circuit comprising a transmitter and receiver connected by a cable, wherein the outputs of the transmitter are connected to the cable via parallel RC circuits.

The circuit according to the invention is advantageous primarily in that the parallel RC circuits serve as passive circuit blocks, thereby eliminating pattern related jitter and allowing for reliable digital transmission of data. The circuit is particularly applicable to systems, eg UART protocols, which use a start bit, data bits and a terminating stop bit, at transmission rates as high as 44Mbits/s and at distances in excess of 100m. It is possible that the same circuit configuration could be used for even higher transmission rates and greater distances. The transmission line nonetheless does not suffer from excessive increases in power consumption. With the inclusion of an additional diode protection circuit it is possible to protect the circuit from fatal damage due to induced transient voltage pulses in excess of 100V for 100ms.

Because the circuit according to the invention enables reliable transmission of data over long distances, the cable may have length in excess of 10m, or in excess of 470/84/P/GB 4 30m, or even 1 00m. However, there will in general be a finite limit on the maximum length of cable that may be employed. This maximum cable length will depend inter alia on the data transmission rate, but may be of the order of 200m or somewhat lower, eg 180m or 150m or 130m.

The resistors and capacitors in the RC circuits will be chosen to suit the particular application. The capacitors typically have values in the range 0.1 to 100nF, more preferably 0.5 to 10nF The resistors typically have values of between I ohm and I 000ohm, more preferably values in the range 1 Oohm to 1 00ohm. One combination of values for the resistors and capacitors that has been found to be suitable is 50ohm and 1.0nF respectively. If the value of the resistance is too high, the signal amplitude may be excessively attenuated. If the capacitance is too high then the rise time of the transmission line may increase.

The cable is in the simplest case a pair of twisted wires. The cable is most conveniently a standard unshielded twisted pair (UTP) cable, eg a standard category 5 UTIP cable.

The transmitter and receiver are preferably differential interface devices, eg RS422 and RS-485 devices.

Suitable means are preferably provided to protect the system from transient voltages, eg excessive voltage injected into the circuit through noise. Zener diodes (which have relatively low capacitance) are preferably used for this purpose, where appropriate with current limiting resistors.

The circuit described above may be used as a communication interface to transfer information from one device to a second device, using digital circuits, wherein information in the format of 8 or 9 binary bits is converted by one said device to an encoded serial bit stream token and sent via a uni-directional connection to the second. The second device decodes this serial bit stream token and converts the data back to 8/9bit format. The second device may simultaneously send information 470184/PIGB in the reverse direction along a separate uni-directionai connection between the two devices.

The 819-bit parallel connection of the device may be interfaced to other digital circuits or to a microcomputer to provide further transfer of the information and control. The device encoderldecoder circuitry may split tokens into two basic types, viz 8-bit binary data tokens and 8-bit binary control tokens. Interlock control digital circuitry may be linked to the encoderldecoder to prevent the overwriting of information by the sending device prior to the receiving device transferring the information to other circuits.

Each device may use a different timing clock to provide signals of a common frequency. Each clock may have a small deviation (eg up to 1 %) from the common frequency. A circuit in the first interface may be used to sample the input from the second which operates at a minimum frequency of 1.5 times the bit rate of the serial data stream.

The communication interface may encodeldecode the serial bit stream token as a data token, consisting of one start bit, an optional data-type bit, an 8-bit binary data value, an optional parity bit and a minimum of one stop bit to terminate the data token. Also the bit stream may have control tokens consisting of one start bit, a control-type bit, between 3 to 8 data value, an optional parity bit and a minimum of one stop bit to terminate the control token.

The communication interface may contain a minimum of a reset, X-ON and XOFF control tokens, as well as additional control tokens including end-ofpacket, end-ofmessage and error tokens.

A network of digital systems using a communication interface as described above may have one or more interconnections between the communication interface which take place over a short distance (eg less then 0.3 metres). These short connections may be implemented via a single line one connect to the serial input and the other to the serial output.

470/84/P/GB 6 The invention will now be described in greater detail, by way of illustration only, with reference to the accompanying diagrams, in which Figure 1 is a circuit diagram of an embodiment with protection diodes; 5 Figure 2 shows the jitter observed with the circuit of Figure 1 in comparison with a conventional circuit; and Figure 3 is a circuit diagram of an embodiment without diode protection.

Test Setup The oversampling (OS) serial communication design and most of the test circuit were combined into the Altera ROKA device (EPFlOK10ATC100-2). The design was optimised for this family of CPLD (Complex Programmable Logic Device) devices, achieving the maximum operating frequency of 66 MHz. This offers a data transmission rate of 44Mb/s. An OS Link device implemented by Nottingham Trent University (see, for example, "A Message Controller for Distributed Processing Systems" by Kar Leong Wong, PhR Thesis, Nottingham Trent University, June 2000) was interfaced to the high performance RS- 485 transceiver from Analog Devices (ADM1485) to provide differential transmission along large lengths of twisted pair cable. This utilises 3 times oversampling and samples with both edges of the clock. Thus it only requires a sampling clock of 1.5 times of the transmission rate, ie operating with 30 MHz sampling frequency to achieve 20Mb/s data transmission. The twisted pair cable chosen was the CAT 5 UTP cable from Belden (SM1720A), of which separate line pairs were used to provide a full duplex connection.

The basic tests were executed by transmitting pseudo-random data bytes, and verifying the data byte at the receiving end for correct data recovery. A counter kept track of the number of correctly recovered data bytes. If a mismatch was found, an error was flagged and the count recorded. The tests were repeated for a number of different cable lengths to a maximum length of 100m.

470/84/P/GB 7 To measure the quality of the signal received, eye patterns were formed at the receiving end. These were obtained by using the infinite persistence display mode of the oscilloscope, triggered from the transmitting clock. The amplitude attenuation was measured at the input side of the receiver and the signal skew was measured at 5 the output of the receiver.

The first test configuration consists of the recommended set of requirements for differential transmission, that is, termination of both ends of the transmission line with 100ohm resistors. Tests with random data -were carried out to determine the maximum cable length over the range of data rates. The final tests and analysis were carried out at these maximum cable lengths so that the greatest effect on the signal quality was seen when modifications were made. The major modifications were aimed towards line balance improvement and transient spike protection. The combined enhanced circuit diagram is shown in Figure 1.

Diode Protection Transient voltages induced on a transmission medium can destroy unprotected digital circuits. A number of economical solutions were analysed for signal degradation and protection capability. Good galvanic isolation can be obtained by using a transformer but this requires an a.c. coupling of the circuit. TVS (Transient Voltage Suppressor) diodes are more commonly used, though they provide lower levels of protection.

High power TVS diodes are available on the market that can sustain peak pulse power of a few hundred to thousand wafts. However, these protection diodes possess a fairly large capacitance, which will effectively distort the signal quality especially at high speed with long distance transmission. A test was undertaken with TVS diodes from Fairchild (P6KE13CA). The result showed a totally closed eye pattern.

The use of lower power zener diodes (lower capacitance) in conjunction with a current limit resistor, R,, was used as an alternative solution, as shown in Figure 1. The BZX79xx series was used in this test. The effect of adding this protection only 470184/P/GB 8 incurred extra skew of 0.7ns. Surge tests indicated that this circuit provides protection against pulses in excess of 100V for 100ms. The typical value of R, is 50ohm.

Line Balance Improvements As the transmission line is DC-coupled at both ends, there is a charging of the line as one value is maintained over several bit intervals. To show how the unbalance data pattern can affect the skew at the receiving end, a series of tests were run with different unbalanced data patterns. Each selected data pattern was transmitted repetitively and the jifter measurement was recorded. The results indicate that for the basic circuit, minimum skew is recorded for the best data balance. As the imbalance of the data paftern increases the skew increases.

To improve the line balance effect, a parallel RC circuit was added to each output terminal as shown in Figure 1. The capacitor coupling, Ct", allows rapid rate of change in the signal while the resistor, RN, provides a lower voltage level to maintain the charge line at a constant value. With the enhanced interface circuit, the unbalance data paftern tests show that the skew is independent of data pattern. The magnitude of skew is also reduced to a value comparable with the minimum skew achieved in the basic circuit tests. However, the value or Rt,, and Ct., have to be carefully chosen. Larger values of R tend to attenuate the signal too much, while larger values of C incur longer rise times. Transmission line impedance matching must be considered also, to ensure optimum transmission characteristics.

The circuit of Figure 1 shows the RS-485 differential transmitter on the left. This is connected to the unshield twisted pair (UTP) cable via two separate parallel resistor capacitor configurations. The typical value of Rtx is 50ohm and Ctx is 1.0 nF. The UTP cable is standard CAT 5 cable. The termination resistor at the RS-485 receiver on the right of the circuit is a standard 100ohm (2 x 50ohm with a centre tap capacitor connected to ground).

470184/PIGB 9 Result & Conclusion

Figure 2 shows the overall jitter comparison of random data test results for basic configuration and full enhanced configuration. For the basic circuit, the jitter increases as the length of cable increases. It reaches the receiver capability limit (33%) at 70m. The performance drops significantly after 70m. For the enhanced circuit, the jitter remains constant for the lengths of cable up to 1 00m. Although the jitter is worse than the basic circuit at short distances, there is a significant improvement at lengths greater then 50m. At the length of 100m, the jitter is only 19%. This offers the potential of going beyond 100 m transmission distance. As the last phase of test, the enhanced circuit was tested for reliability. The test was run for hours without any errors, which gives a bit error rate of 3.16E-13, ie 3. 16 x 1013 _ the approximate number of bits tested during the 20-hour test run with no error found.

Finally, an embodiment without diode protection is shown in Figure 3. This is identical to the circuit of Figure 1 save that the Zener diodes Dtx and Drx and current limit resistor R, are omitted.

470184/P1GB

Claims (20)

Claims

1 A circuit for the transmission of data, the circuit comprising a transmitter and receiver connected by a cable, wherein the outputs of the transmitter are connected to the cable via parallel RC circuits.

2 A circuit as claimed in Claim 1, wherein said RC circuits comprise a capacitor of value 0.1 to 10OnF in parallel with a resistor of value 1.0 to 1000ohm.

3. A circuit as claimed in Claim 2, wherein the capacitor has a value of 0.5 to 1OnF

4. A circuit as claimed in Claim 2, wherein the resistor has a value of 10 to 100ohm.

5. A circuit as claimed in any preceding claim, wherein the cable comprises a pair of twisted wires.

6. A circuit as claimed in Claim 5, wherein the cable is a Category 5 unshielded twisted pair cable.

7. A circuit as claimed in any preceding claim, wherein the transmitter and the receiver are differential interface devices.

8. A circuit as claimed in Claim 7, wherein the transmitter and the receiver are RS-422 transceivers.

9. A circuit as claimed in Claim 7, wherein the transmitter and the receiver are RS-485 transceivers.

10. A circuit as claimed in any preceding claim, further comprising means for protecting the circuit from excessive transient voltage.

470184/PIGB

11. A circuit as claimed in Claim 10, wherein said means comprises Zener diodes.

12. A circuit as claimed in any preceding claim, wherein said cable has a length in excess of 10m.

13. A circuit as claimed in any preceding claim, wherein said cable has a length in excess of 30m.

14. A circuit as claimed in any preceding claim, wherein said cable has a length in excess of 100m.

15. A communication interface for the transfer of information from a first device to a second device, which interface comprises a circuit as claimed in any preceding claim, and wherein the information is converted by the transmitter to an encoded serial bit stream which is sent via the cable to the receiver, at which receiver the bit stream is converted back to its original format.

16. A communication interface as claimed in Claim 15, wherein the bit stream comprises data tokens and control tokens.

17. A communication interface as claimed in Claim 16, wherein each data token consists of a start bit, an optional data-type bit, an 8-bit binary value, an optional parity bit and a minimum of one stop bit to terminate the data token.

18. A communication interface as claimed in Claim 16, wherein each control token consists of a start bit, a control-type bit, 3 to 8 data values, an optional parity bit and a minimum of one stop bit to terminate the control token.

19. A circuit for the transmission of data, substantially as hereinbefore described and as illustrated in Figure 1.

20. A circuit for the transmission of data, substantially as hereinbefore described and as illustrated in Figure 3.