GB2361152A

GB2361152A - Identifying PN CODE in CDMA system

Info

Publication number: GB2361152A
Application number: GB0008244A
Authority: GB
Inventors: Menkang Peng
Original assignee: Telefonaktiebolaget LM Ericsson AB
Current assignee: Telefonaktiebolaget LM Ericsson AB
Priority date: 2000-04-04
Filing date: 2000-04-04
Publication date: 2001-10-10
Also published as: GB0008244D0

Abstract

Identifying a pseudo-noise (PN) code in a CDMA telecommunications system utilises a locally produced code which is divided into a number of portions. The portions are correlated with an incoming signal using a sliding correlator. A pair of registers is used to store consecutive local code portions to reduce the correlation time, and hence reduce the code acquisition time.

Description

2361152 TELECOMMUNICATIONS SYSTEMS is The present invention relates to

telecommunications systems and in particular to code division multiple access (CDMA) and wide band CDMA (WCDMA) systems using pseudo noise (PN) coding sequences.

DESCRIPTION OF THE RELATED ART

CDMA and W-MMA, telecommunication systems, such as described in 1IMMA f or wireless personal communications" (Prasad), Artech House Publishers 1996 and UWide band CDMA for third generation mobile communications" Artech House Publishers 1998, make use of a pilot signal channel to enable synchronisation of the receiver with an incoming transmitted signal. To achieve such synchronisation, it is necessary to search for the pilot signal having the highest signal strength.

For each communications link between stations, the forward CDMA signal consists of a pilot channel and several traffic (data) channels. These channels are spectrum spreaded by a pseudo noise (PN) code; the same PN code with the same timing is used for each channel in a link. The PN timing, or PN phase, must be acquired and synchronised before any traffic channel can be despreaded and data information obtained. The pilot channel carries no data except a repeating PN code and so acquisition and synchronisation of the pilot channel enables the timing of the PN code to be found for the data channels. The acquisition of PN timing can also be regarded as the acquisition of pilot signal. It is well-known that the PN timing can be acquired by correlating the incoming pilot signal with a locally generated PN code (the same code as in the incoming signal) in the receiver. The correlation has to be is carried out for all possible PN phases with a resolution of one chip (or half a chip as in most practical situations). The correlation with maximum value corresponds to the most likely PN timing.

Assuming that the correlation is carried out on the basis of one sample per chip of the pilot signal, i.e. the resolution of the correlator is one chip, and that the length of the pilot sequence is Lp chips in length, a total of Lp correlation results are needed to be produced for accurate pilot signal acquisition. Each of the results relates to a particular different phase of the pilot timing. The pilot signal is broadcast as a repeating pattern of "circles" of Lp chips length. Correlation is needed in order to determine the start point of a circle. The correlation which gives the largest correlation result identifies the phase of the pilot signal. In the following explanation it is assumed that each statistic should come from a total of N chips length correlation in order to meet certain detection probability and false alarm requirements. N is chosen on the basis of the signal to noise ratio of the pilot signal.

One approach for correlating a signal to identify a PN sequence having a length of Lp chips is to use a correlator of that length. The correlator receives the stream of chips as an input and the subsequent outputs produced as the pilot signal propoqates through the correlator provide the necessary statistical information.

However, providing a correlator of the same length as the PN circle Lp requires a undesirably large amount of hardware. Accordingly, one proposed method, such as that described in International Patent Application No. PCT/SE97/00429 (Publ. No. W097/36395), of reducing this hardware requirement is to use a short length correlator which is operated to provide several time is domain averages in order to acquire the pilot signal.

In such a scheme the input pilot signal is correlated with parts of length Ls of the locally produced pilot signal such that the result of each correlation is a output of Ls chips in length. Ls is naturally less than Lp. Therefore, a total of N/Ls sliding outputs need to be added together to produce one final statistic, which is equivalent to N chip correlation. The added sliding outputs must also relate to the same pilot signal phase.

Under some circumstances for example the IS95 standard, it can be possible to find a specific section of the PN code which can be loaded into the sliding correlator as locally generated PN code and has optimum performance in acquisition of PN under certain criteria. In this case, this specific single section of PN sequence will be loaded into the sliding correlator and kept unchanged throughout the correlation process. In such a case, input samples are fed into the sliding correlator continuously. After a full PN circle time (ignoring the initial Ls chip time for sliding in the initial data), a total of Lp sliding correlator outputs are produced, each of which is a Ls chip correlation and relates to one PN phase. At the (Lp+l) th chip, or the first output in the second circle, the sliding output will has the same PN phase as that at the lat chip, since just one full circle time passes by and the PN code in the sliding correlator is kept unchanged. Therefore the sliding output at (Lp+ 1)th chip, the first output in the second circle, can be added together with the output at the ist chip, the first output in the first circle. The output at the (Lp+2) th chip is added to that at the 2d chip, etc. Af ter a total of (N/Ls) circles, or (N/Ls)Lp chip time, all Lp final statistics will be obtained.

However in some situations, for example complex is codes using inner and outer PN sequences, it can be extremely difficult to find one single section of PN sequence, which can be loaded into the sliding correlator to produce optimum performance. For example in the Globalstar satellite communications CDMA system, the PN sequence is a combination of inner and outer PNs and the acquisition of inner PN has to be carried out with outer PN timing unknown. Under this kind of situation, no single optimum section of PN sequence can be found and multiple sections of PN sequence may have to be used.

It is therefore desirable to provide a system in which pilot signals can be acquired quickly, with a relatively low hardware requirement.

SUMMARY OF THE PRESENT INVENTION

According to one aspect of the present invention, there is provided a method of identifying a repeating N-bit pseudo-noise (PN) code in a code division multiple access telecommunications system, the method comprising:

a) defining a local code, and dividing the local code into a series of local code portions; b) receiving a channel signal; c) using a sliding correlator, correlating a first local code portion with a first N-bit section of the channel signal to produce a first set of correlation results representing respective phases; d) storing the first set of correlation results; e) using a sliding correlator, correlating the next local code portion with the next N-bit section of the channel signal to produce a further set of correlation results representing respective phases; f) combining the further set of correlation results with the stored set of correlation results, is such that the phase difference between the stored and further sets of results is zero to produce a combined set of correlation results; g) storing the combined set of correlation results; h) repeating steps e) to g) until all of the defined local code portions have been correlated with respective N-bit length section of the channel signal; and i) supplying the combined set of correlation results to a pseudo-noise code detector.

According to another aspect of the present invention there is provided a method of acquiring a pilot signal in a CDMA telecommuni cations system, the method comprising:

receiving input pilot signal comprising a repeating pilot code cycle; providing a pair of registers; defining a local pilot signal code; storing a first part of the local pilot signal code in one of the registers; correlating the input pilot signal with the contents of one register to produce first correlation results, whilst updating the other register by storing the next part of the local code therein; correlating the input pilot signal with the contents of the last updated register, whilst loading the next part of the local code into the other of the registers; and combining the correlation results from the correlation of the input signal with the parts of the local code.

According to another aspect of the present invention, there is provided a method of acquiring a repeating Lp-chip pseudo-noise (PN) code using a Lschip length sliding correlator in a code division is multiple access telecommunications system. Here Ls is less than Lp and Lp/Ls is an integer. The method is comprised of:

a) dividing the whole Lp-chip PN code into a series of Ls-chip length code sections; b) initialising a sliding correlator by loading the first section of the Ls-chip PN code into the sliding correlator's local PN register set A, then taking in Ls samples of the incoming signal sample into sliding correlator's sample registers; c) starting the sliding correlator, for every signal sample sliding-in, correlating the Ls samples in sample registers with the Ls codes in local PN register set A. In the mean time, loading sliding correlator's local PN register set B by the next (second) section of the Ls-chip PN code; d) storing each correlation output in RAM, after Lp incoming samples, a total of Lp correlation outputs are stored, each of which representing one PN phase; e) from the next incoming sample, correlating the Ls samples in sample registers with the Ls codes in local PN register set B, in the mean time, reloading sliding correlator's local PN register set A by the next (third) section of the Ls-chip PN code. If the current code in register set A is the last section of code, the "next" section should be the first section of the code; f) for each new correlation output produced, a stored old correlation output is read-out from RAM, both correlation must correspond to the same PN phase.

This is realised by a controlled circular shift addressing of RAM; g) the new correlation and the read-out old correlation are added together and then written back to the RAM at the same address as the old correlation; h) after Lp samples, switching back to use local is PN register set A to correlate with signal in sample registers, in the mean time, reloading sliding correlator's local PN register set B by the next (fourth) section of the Ls-chip PN code. If the current code in register set B is the last section of code, the "next" should be the first section of the code; i) repeating steps e) to h) until accumulated correlation length for each PN phase reaches N; j) supplying the final (accumulated) Lp correlation outputs, representing Lp PN phases, to peak detector to find out several most largest correlations, which relate to the most possible PN timings and become candidates for further verification;

Claims

k) verifying all candidates through a normal verification process, if successful, the real timing is claimed found and process finishes, otherwise go back to step b) again and begin a new search; BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram illustrating a system for acquiring a pilot signal; Figure 2 is a block diagram of a correlator unit of Figure 1 embodying the present invention; and Figure 3 is a flow chart illustrating steps in a method embodying the present invention. DETAILED DESCRIPTION OF THE-PREFERRED EMBODIMENT Figure 1 illustrates a system for acquiring a pilot signal in a CDMA telecommunications system, comprising an input (2), a correlator unit (4), a local code generator (6), summing means (8), storage means (10), an output unit (12), a detection unit (14), and a controller (16). The correlator unit (4) is connected to the input (2) for receiving an input pilot signal. is The correlator unit also receives a locally generated code from the code generator (6). A correlator output (5) is supplied to the adder (8) whose output is supplied to the output unit (12). The output unit supplies the correlation outputs to a storage means (10) and to a candidate detection unit (14). The storage unit (10) operates to feed back previous correlation results to the summing means (8) for combination with current correlation results. This will be described in more detail below. The candidate detection unit (14) operates to determine which of the correlation results identify the pilot signal. The candidate detection unit (14) takes Lp correlation outputs which relate to Lp PN timing phases from unit (12) and operates to find out several candidate timing phases. This is realised by comparing all Lp correlation outputs and pick out several most largest correlations, whose relating timings are candidates. The candidates are then output to verification unit (15) for verification. The verification unit (15) operates in line with usual verification strategies. For example, for each candidate timing, Nv number of independent N-chip length correlations can be carried out. Among them, if Ng (N9 < Nv) correlations are larger than a threshold values, then the corresponding candidate timing is declared as the "real,, timing and the PN timing is thus acquired and whole process ends. Otherwise, this candidate is dismissed. If all candidates are dismissed, the acquisition process fails. The whole above process will repeat for the next attempt to acquire the PN timing. Figure 2 illustrates one embodiment of the correlator unit (4) of Figure 1. The correlator unit (4) includes a sliding correlator (20), a first register A (22), a second register B (24) and a local -g- code divider (26). The sliding correlator receives, as a first input, the input pilot signal (2), and as a second input either the contents of register A (22) or is register B (24). The locally generated full circle (Lp-chip) PN code is supplied to the code divider (26) which divides the whole PN code into several equal length (Ls) parts for supply to the register set A and B in the sliding correlator. The length of each code part is the same length of the sliding correlator, which is Ls-chips. There are therefore a total of (Lp/Ls) local code parts. The operation of the system shown in Figures 1 and 2 will now be described with reference to Figure 3. At step A, register A (22) is loaded with the first part of the locally produced code (Ls chips from the Lp long code). The sliding correlator then correlates the incoming signal with the contents of register A, and at the same time register B (24) is loaded with the next part of the locally produced code. The results of the correlation are stored in the storage unit (10) via the summing means (8) and the output unit (12). The next input pilot signal cycle of Lp chip is correlated with the contents of register B, (i.e. the next part of the locally produced code) and, at the same time, register A is loaded with the third part of the locally produced code. The correlation results between the contents of register B and the input signal are added to the corresponding results from the first round of correlation. The results must be added together with the correct phase relationship since the results correspond to correlation with different parts of the locally produced code. One suitable way of achieving this is to use an addressable memory device for storing the results of the correlation. In such a case shifted addresses can then be used to obtain the correct information to supply to the adding means (8) The results of the addition are stored in the storage means for use in combining with the next set of results. In such a method, the sliding correlator continuously produces output values, and all of the outputs relating to the same phase of the input pilot signal can be continuously added together. This results in the total time needed to produce Lp final statistics being reduces to N/LsLp chips which is the same as that under fixed loaded PN. An example will now be described in order to aid understanding of the invention. This example is not to be seen as restrictive. Consider a CDMA system with a PN code of 1024-chip length, i.e., Lp =1024. One possible configuration is to let Ls=256. Thus the original PN code is divided into 4 parts. Assume N=2048, which is the overall correlation length required for the combined correlation for each timing phase. The locally derived code is also divided into 4 parts of 256 chips each. During an initialisation process, the initial 256 incoming signal samples are input into the sliding correlator's 256 sample registers. In the mean time, the first part code (256 chip) is loaded into register set A. After the initialisation process is completed, a sliding correlation process begins. Starting from the 1 new incoming signal sample and for every new signal sample coming in, the 256 samples buffered in sample registers are correlated with the 256 code in local PN register A and a correlation result is produced and stored in RAM. The 256 samples in sample registers are then shifted by one position. Assuming that the oldest sample is at position 1 and the second oldest sample at position 2 and so on, then the shift can be described as follow. First the oldest sample is shifted out of is position 1 and discarded. The second oldest is shifted to position 1 and becomes the new oldest sample, the third oldest sample is shifted to position 2 and becomes the new second oldest sample. This shift process continues for all 256 chips. Position 256 then becomes empty and is ready to take in a new incoming signal sample. It should be noted that only signal samples in sample register are shifted, and the PN code in local PN register set A is kept unchanged. This is the principal of sliding correlation. So after 1024 incoming samples, 1024 correlations are produced, which relate to 1024 possible PN timing phases. Assuming these 1024 correlations are stored in RAM address 1, 2,... 1 1024, starting from the first to the last correlations. During this correlation process the next 256 chips of the local PN co de are loaded into the register set B. For the next 1024 incoming samples, f rom 1025th to the 204 8th, the sliding correlator will correlate the samples in sample register with code in local PN register set B and then carried out the same shift. For the 1025 th incoming sample, the corresponding correlation output will be added with the previous correlation result stored in RAM address 769 (769 is obtained by 1024-256+1=769) and the summation will be written back to RAM address 769. This is the circular shifted addressing. For the 1026 th sample, the new correlation output will be added with the previous correlation result stored in RAM address 770 and the summation will be written back to RAM address 770. So are for other incoming samples. For the 204 8th sample, the new correlation output will be added with the previous correlation result stored in RAM address 768 and the summation will be written back to RAM address 768. During correlation with the contents of register set B, the next 256 chips of the local PN code are is loaded into register set A. For the next 1024 incoming samples, from 204 9th to 3072", the sliding correlator will correlate the samples in sample register with code in local PN register set A and then carried out the same shift. For the 2049th incoming sample, the corresponding correlation output will be added with the previous correlation result stored in RAM address 513 (because 1024-2x256+1=513) and the summation will be written back to RAM address 513. For the 3072 nd sample, the new correlation output will be added with the previous correlation result stored in RAM address 512 and the summation will be written back to RAM address 512. This process continues until 8192 nd sample is received and the above corresponding operation finished. Now in the 1024 RAM address, there are 1024 combined correlation results, each of them has an equivalent correlation length of (256x8)=2048 chips. Each of them also relates to one unique PN timing phase. They can be now supplied to candidate detection unit to find out several, say 3, candidates, which come from 3 largest correlation results. Each of the 3 candidates is later verified by a verification unit one by one. Among them, no more than one can pass verification successfully. If one of the candidates does pass verification successfully, the PN acquisition is declared as a success and the PN timing acquired can be passed for further usage. If none of the 3 candidates passes the verification process successfully, the acquisition is declared failure and new attempt may begin by going back to the initial stage. CLAIMS:

1. A method of identifying a repeating Lp-chip pseudonoise (PN) code in a code division multiple access telecommunications system, the method comprising:

a) defining a local code, and dividing the local code into a series of local code portions; b) loading a first register with a first local code portion; c) receiving a channel signal which includes an input code; d) using a sliding correlator, correlating the contents of the first register with a first Lp-chip length of the channel signal to produce Lp correlation results representing respective phases of the input code, during such correlation, loading a second register with a second local code portion; e) storing the Lp correlation results; f) using the sliding correlator, correlating the contents of the second register with the next Lp-chip length of the channel signal to produce a further Lp correlation results representing respective phases of the input code; g) combining the further correlation results with the stored correlation results, such that the phase difference between the stored and further results is zero; and h storing the combined correlation results; i) supplying the combined correlation result to a pseudo-noise (PN) detector.

2. A method as claimed in claim 1, wherein combining the further results and the stored results comprises circularly shifting the stored results by an offset amount equal to the size of the local code portion used for the corresponding further correlation.

3. A method as claimed in claim 1, wherein the i 1 i 1 stored results are stored in respective locations in a memory device, and the circular shifting of the stored results is achieved by offset addressing to the storage device.

is

4. A method as claimed in any one of the preceding claims, wherein the local code portions are of equal bit size.

5. A method as claimed in any one of the preceding claims, wherein the further and stored results are circularly combined.

6. A method as claimed in any one of the preceding claims, wherein the channel signal is a pilot channel signal.

7. A method as claimed in any one of the preceding claims, wherein the next local code portion is loaded into a register, for supply to the sliding correlator, during correlation of the current local code portion.

8. A method of acquiring a pilot signal in a CDMA telecommunications system, the method comprising:

receiving an input pilot signal comprising a repeating pilot code cycle; providing a pair of registers; defining a local pilot signal code; storing a first part of the local pilot signal code in one of the registers; correlating the input pilot signal with the contents of one register to produce first correlation results, whilst updating the other register by storing the next part of the local code therein; correlating the input pilot signal with the contents of the last updated register, whilst loading the next part of the local code into the other of the registers; combining the correlation results from the correlation of the input signal with the parts of the -is- local code; and repeating the correlating and.combining steps until the whole of the local pilot signal code is correlated with the input pilot signal.