GB2360649A

GB2360649A - A voltage divider generating bias voltages for an LCD driver

Info

Publication number: GB2360649A
Application number: GB0114839A
Authority: GB
Inventors: Jerry Hsu; Wesley Jehng
Original assignee: United Microelectronics Corp
Current assignee: United Microelectronics Corp
Priority date: 1997-02-05
Filing date: 1997-02-05
Publication date: 2001-09-26
Anticipated expiration: 2017-02-05
Also published as: GB0114838D0; GB2360648A; GB0114839D0; GB2360649B; GB2360648B

Abstract

A voltage divider comprises series connected pairs of high-value and low-value resistors. The divider nodes a,b,c,d,e provide bias voltages for an LCD driver 40. When the driver 40 is active, the output impedance of the bias voltages is lowered by closing the transistor switches SW connected across each of the high-value resistors. Hence large driving currents can be supplied to the LCD driver 40 even though the current flowing through the divider is normally low. A standby signal deactivates the current sink.

Description

2360649 APPARATUS AND METHOD FOR GENERATING BIAS VOLTAGES FOR LIQUID

CRYSTAL DISPLA

BACKGROUND OF THE INVENTION

Field of the Invention

The invention relates to a liquid crystal display (LCD), and more particularly, to an apparatus and method for generating bias voltages for an LM driver.

Description of Background Art

Liquid crystal displays (LCDs) are digital displays widely used in digital watches, calculators, handheld game machines, and various other electronic appliances. The circuit structure of a typical LCD device is shown in FIG. 1, in which an LM driver 10.in conjunction with a voltage divider 20 are used to drive an LM panel 30. In practice, the LC1) driver 10 and the voltage divider 20 are implemented in an integrated circuit (IC) as indicated by the dashed box 1. The voltage divider 20 consists of a number of resistors R that divide an external voltage Vcc into bias voltages Va, Vb, V, Vd, and V,. These bias voltages are applied to and drive the LM driver 10 to generate a plurality of LM driving signals, including c ommon signals, via the COM1 -CO" lines and segment signals via the SEGI-SEG40 lines.

In the voltage divider 20, the plurality of resistors R constitute a DC current path throughwhich a DC current 1d flows. These resistors are provided with high resistances, such as 1.00k.Q or 200kn so as to minimize the current Id flowing through the DC current path. A drawback to the use of high resistance resistors is that the resulting driving current used to actuate the LM driver for switching of the LM driving signals may be insufficient.

To cope with this problem, a conventional method is to provide a corresponding number of capacitors C connected externally via I/0 pins on the IC 1 to the voltage divider 20. These capacitors C are used for voltage stabilization of the circuit so as to supply sufficient actuating current I, to the LCD driver for switching of the LM driving signals.

ICs based on. the foregoing circuit architecture for generating bias voltages include MSM5238GS, MSM5259GS, and MSM5278 which are manufactured by the OKI Semiconductor Corporation. However, providing the externally connected capacitors has two drawbacks. First, for low-cost LM handheld game machines, the provision of these externally connected capacitors and the corresponding 110 pins significantly increases manufacturing cost; and second, the increased number of I/0 pins on the IC would cause the size of the chip to be larger than it would be otherwise.

Two methods have been used to eliminate the foregoing two drawbacks. The first method is to avoid using the capacitors and reduce the resistance values of the resistors R so as to provide a larger DC current Ij. However, this causes a large leakage current. For example, assuming in the circuit of FIG. 1 that R=100M and Vcc=5 volts, then Id =51(1 00kx 5)= 1 OgA_ However, if R is reduced to 15M, then Ii = 5VI(I Skú1x5) =67gA Since the IC needs only a small amount of current for operation, such a large current of 67pAw.ould cause much of the electrical power to be wasted. The second method is to provide built-in capacitors in the IC. However, this increases the area of the chip and such capacitors would be very low in capacitance, several o-rder.s.from the desired level.

It is therefore an object of the invention to provide a method and apparatus for generating bias voltages for an LCD driver which require no externally connected capacitors to dynamically supply sufficient actuating currents to the LCI) driver.

It is another object of the invention to provide a method and apparatus for generating bias voltages for an LCI) driver which are capable of supplying sufficient actuating current despite the fact that resistors having high resistance values are used in the voltage divider.

In accordance with the foregoing and other objects of the invention, a new and improved method and apparatus for generating bias voltages for an LCD driver is provided.

The invention is defined in the attached independent claims, to which reference should now be made. Further, preferred features may be found in the appended sub- claims.

An embodiment of the apparatus according to the invention includes a voltage divider including a plurality of serially connected first resistors forming a DC current path having a plurality of nodes, the voltages of each node serving as a bias voltage to the LCI) dil,er- to actuate the L'C'-D dr-iv"-er't'o'g-enera-te- a-p'l-u'r'a-l-it- y of LCD driving signals; a signal generator for generating a switching signal in synchronism with the LCD driving signals; and a switching circuit including a plurality of switching units each of which is connected across a corresponding resistor in the voltage divider, each of the switching units being closed to connect a second resistor across the correspondirig' first resistor when the LCD driving signals are being switched, and each of the switching units otherwise being open.

Another embodiment of the apparatus according to the invention includes a voltage divider including a plurality of serially connected resistors of a first resistance forming a DC current path having a plurality of nodes, the voltage of each node serving as a bias voltage to the LCD driver to actuate the LCD driver to generate a plurality of LCD driving signals; a signal generator for generating a switching signal in synchronism with the LCD driving signals; and a switching circuit including a plurality of transistor switching units each having an internal resistor of a second resistance, each of the transistor switching units being connected across a corresponding resistor in the voltage divider, each of the transistor switching units being closed so as to connect the internal resistor across the corresponding resistor in the voltage divider when the LCD driving signals are being switched, and each of the transistor switching units being otherwise open.

is A firther embodiment of the apparatus according to the invention includes a voltage divider including a plurality of pairs of serially connected first resistors and second resistors forming a DC current path having a plurality of nodes, the voltage of each node serving as a bias voltage to the LCD driver to actuate the LCD driver to generate a plurality of LCD driving signals; a signal generator for generating a switching signal in synchronism with the LCD driving signals; and a switching circuit consisting of a plurality of switching units each of which is connected across a corresponding second resistor in the voltage divider, each of the switching units being closed to short-circuit the second resistor when the LCD driving signals are being switched, and each of the switching units being open otherwise.

A method according to the invention comprises the following steps: generating a switching signal; applying a voltage to a voltage divider to set a bias voltage at each node of a plurality of nodes of the voltage divider, wherein the voltage divider includes a plurality of serially connected first resistors and wherein each node is located adjacent to, and at one end of each of the corresponding first resistors; opening and closing a pluralit of serially connected switching units in response to the switching signal, wherein each of the switching units includes a switch and a second resistor that have properties equivalent to those of every other switch and second resistor and wherein each of the switching units is connected in parallel with a corresponding one of the first resistors; and connecting each of the second resistors in parallel with the corresponding first resistor when the switching units are closed.

Another method according to the invention comprises the following steps:

generating a switching signal, applying a voltage to a voltage divider to set a bias voltage at each node of a plurality of nodes of the voltage divider, wherein the voltage divider includes a plurality of serially connected pairs of first and second resistors and a respective node at one end of each of said pairs of first and second resistors; opening and closing a plurality of serially connected switches in response to the switching signal, wherein each of the switches is connected in parallel with a corresponding one of the second resistors; and nullifying the second resistors when the switches are closed.

A further method according to the invention comprises the following steps:

generating a switching signal; applying a voltage to a voltage divider to set a bias voltage at each node of a plurality of nodes of the voltage divider, wherein the voltage divider includes a plurality of serially connected divider resistors and wherein each node is is located adjacent to, and at one end of each of the corresponding divider resistors; opening and closing a plurality of serially connected transistor switching units in response to the switching signal, wherein each of the hmmistor switching units includes a stor switch possessing an internal resistance, and wherein each of said plurality of transistor switching units is connected in parallel with a corresponding one of the divider resistors; and connecting each of the internal resistances in parallel with the corresponding divider resistor when the transistor switches are closed.

In general, a method of operation applicable to the invention includes the following steps: generating a switching signal; applying a voltage to a voltage divider to set a bias voltage at each node of a plurality of nodes of the voltage divider, wherein the voltage divider includes a plurality of serially connected variable resistors and wherein each node is located adjacent to, and at one end of each of the corresponding variable resistors; raising and lowering the resistance values of the variable resistors in response to the switching signal so as to simultaneously make the bias voltages deliver(drive) a dynamic current flowing through the voltage divider.

BRIEF DESCREPTION OF DRAWINGS The invention can be more fully understood by reading the subsequent detailed description of the preferred embodiments with reference to the accompanying drawings, wherein:

FIG. 1 is a schematic block diagram of a conventional circuit configuration for generating bias voltages for driving an LCI) driver; FIG. 2 is a schematic block diagram of a bias voltage generator according to the invention; FIG. 3 is a schematic circuit diagram of an embodiment of the bias voltage generator according to the invention; FIG. 4A is a schematic circuit diagram of another embodiment of the bias voltage generator according to the invention; FIG. 4B is a schematic diagram of a switching circuit utilized in the bias voltage generator of FIG. 4A; is FIG. 4C is an equivalent circuit of the switching circuit of FIG. 4B; FIG.. 5 is a schematic circuit diagram of a further embodiment of the bias voltage generator according to the invention; FIG. 6 is waveform diagrams of control signals used in the bias voltage generator according to the invention; and FIG. 7 is waveform diagrams of signals used to drive an LC1).

DETAILED.DESCRIPTION OF PREFERRED EMODMNTS

Referring to FIG. 2, there is shown a schematic block diagram of a bias voltage generator 50 according to the invention. The bias voltage generator 50 is coupled to an LCI) driver 40 used to drive an LCI) panel 30. The bias voltage generator 50 comprises a voltage divider 51 coupled to the LC1) driver 40, a switching circuit 53 coupled to the voltage divider 5 1, and a signal generator 55 which receives the system clock signal SYSCK to generate a switching signal LCDPULSE, which is provided to the switching circuit 53.

The signal generator also generates a CLK signal to the LCI) driver 40. The LCD driver 40 is used to generate a plurality of LCI) driving signals, including commonsignals to be provided via the COMI-C lines and segment signals to be provided via the SEGI- SEG40 lines, to the LC1) panel 30. These LC1) driving signals COMI-COAfl and SEG I -SEG40 are generated in synchronism under control by the WDPULSE and CLK signals.

It is an aspect of the invention that the switching circuit 53 is switched so as to lower the resistance between adjacent nodes in the voltage divider 51 in order provide adequate actuating current during switching of the COMI-CO&B and SEGI- SEG40 signals. The switching circuit 53 is switched oT at all other times so as to maintain the resistance between adjacent nodes in the voltage divider 51 at a large constant value so as to minimize the current Id flowing through the circuit path defined by the voltage divider.

Various exemplary embodiments for the circuit structure of the bias voltage generator 50 are described below.

First Exemplary Embodiment Referring to FIG. 3, there is shown a schematic circuit diagram of a first exemplary is embodiment -of the bias voltage generator 50 according to the invention. The voltage divider 5 1. consists of a plurality of 1 00M resistors c,omected at nodes a, b, c, d, e and coupled to an external voltage source Vcc. This arrangement allows the provision of bias voltages V,,. V,5, V,, Vd, and V,. at the nodes a, b, c, d, e for driving th e LCI) driver 40. A logic signal STA YDRY coupled via an inverter 52 to. the node e is used to control the bias voltages V, Vb, V, Vd, and V, in the manner indicated in the following table:

TABLE srAy,oBY =1, V, =logic 0 voltage srAY9Br =0, V, = logic 1 voltage V,, = 415 Vcc V. = VCC Vi, = 315 Vcc Vb = VCC V,, = 215 Vcc V, = VCC K, = 1/5 VCC V't = VCC The bias voltages V., Mb, E:, Vd, and V, are used to actuate the LCI) driver 40 to generate the LCI) driving signals COM1-COM8 and SEG I -SEG40.

The switching circuit 53 is composed of a plurality of switching units S,, Sb, S, S'j, and S, each of which consists of a switch SW and a serially connected 10M resistor.

Further, each switching unit is connected in parallel with a corresponding resistor in the voltage divider 51. The switches SW are shown in Fig. 3 in an open position.

The switching signal LWPME generated by the signal generator 55 is used to control switching of the switches SW in the switching circuit 53. When the switching signal WDPULSE is a logic 1, the switches SW are closed, thereby connecting the 1 01M resistors across the 100k.Q resistors, which elFectively reduces the equivalent resistance between two adjacent nodes to about 9.09k.O. This Cows larger actuating currents I, to be generated. These actuating currents 4 flow from the nodes a, b, c, d, e to the LC1) driver 40 to actuate the LC1) driver 40 to generate the LC1) driving signals COMI-COMS and SEG I -SEG40.

During the times the LC1) driving signals COMI-COMS and SEGI-SEG40 are not to be switched, the switching signal LMPULSE from the signal generator 55 is a logic 0, is which causes the switches SW in the switching circuit 53 to be opened. In this circumstance, the nodes a, b, c, ú e are connected only by the 100M resistors. The resistance between two adjacent nodes is therefore 1 00M. When ST,4 NDB y = 1, V, --0 and if Vcc=5 volts, then Id =5V/5 0OkQ= 1 OgA The STA NPB Y signal that controls the voltage V. of the node e is a logic 0 signal when the LC1) is in a standby mode and is a logic level 1 otherwise. Thus, when STA MP BY =0, it is inverted by the inverter 52 to a logic level 1, putting the voltage V, at Pcc. This allows the current I,, to be forced to null.

Second Exemplary Embodiment Referring to FIGs. 4AAC, there are shown diagrams depicting a second exemplary embodiment of the bias voltage generator 50 according to the invention. In this embodiment, elements that are identical in structure and function to those in the first exemplary embodiment are labeled with the same numerals and the description thereof will not be repeated.

The second exemplary embodiment differs from the previous one only in that the switching circuit 53 consists of a plurality of transistor switches SW each having an internal resistance R, as schernatically illustrated in FIG. 4C. Each transistor switch is connected in parallel with a corresponding 100k!Q resistor in the voltage divider 51.

Referring to FIG. 4B, the transistor switch SW is preferably a longchannel transmission gate 54 comprising an NMOS transistor Q1 having gate G1 controlled by 5. WDPULSE and a PMOS transistor Q2 having gate G2 controlled by WPPYLSE. The source S is coupled to Vcc and the drain D is coupled to node a.

When the LCD driving signals are to be switched, the signal generator 55 generates the signal WDPULSE=I, which. causes both the NMOS transistor QI and the PMOS transistor Q2 to be turned on. Since there is an equivalent low resistance Pv across the.

long-ch=el transmission gate 54, the equivalent resistance between Vcc and node a is less than Ri and the current I, increases to drive the LC1) driver 40..

Otherwise, the signal generator 55 generates the signal WDPULSE=O, which causes the current path through the NMOS transistor QI and PMOS transistor Q2 to be open-circuited. In this circumstance; the equivalent resistance between Vcc and node a is LS 1 00kfX thereby causing the current It to be low.

Third Exemplary Embodiment Referring to FIG. 5, there is shown a third exemplary embodiment of the bias voltage generator 50 according to the invention- In this embodiment, elements that are 0 identical in structure and function to those in the first exemplary embodiment are labeled with the same numerals and the description thereof will not be repeated.

The third exemplary embodiment differs from the previous ones in. that the voltage divider 51 consists of a plurality of pairs of 1 Ok.Q and 90kn resistors connected in series, and the switching circuit 53 consists of a plurality of corresponding switches SW, each being connected across a 90 kQ equivalent resistor When the LCD driving signals are to be switched, the signal generator 55 generates the signal WDPULSE=l, which causes the switches SW to be closed. Asacorisequence, the 90M resistors are nullified and the equivalent resistance between each pair of adjacent nodes is 10M. The tow I 0M resistance allows the bias voltage generator 50 to supply large actuating currents I, to the LC1) driver 40 to actuate the LCD driver 40 to generate the LCI) driving signals.

Otherwise, the signal generator 55 will generate the signal WDPULSE=O, which causes the switches SW to be open, thereby disconnecting the current path therethrough.

In this circumstance, the equivalent series resistance between each pair of adjacent nodes is 1 Oicn plus 90kn, which is equal to 1 0OkQ. The high 1 00kn resistance allows the current 1,, to be significantly reduced.

It should be noted that each of the three exemplary embodiments described herein includes some form of variable resistance which is switched between a lower resistance value and a higher resistance value in response to the switching signal LCI) pulse.

FIG. 6 shows the waveform diagrams of the signals CLK, COMI, COM2, WDPULSE, and DYM used in the bias voltage generator 50 according to the invention.

The CLK signal is generated by the signal generator 55 with timing based on the system clock signal SYSW. As shown, when the common signals COM1 and COAn are to be generated by the LCI) driver 40, the signal generator 55 will generate, in synchronism with the common signals, the switching signal WDPULSE signaL which consists of a train of pulses. This causes the voltage divider 51 to be switched to low resistance, thereby obtaining larger actuating currents 1, Furthermore, the voltage divider 51 in combination with the switching circuit 53 constitute a dynamic resistor DYNR During the time the signal generator 55 generates the WDPULSE signg.switches SW of the switching circuit 53 are closed, providing a current path and allowing the high resistance in the voltage divider 51 to be connected in parallel with the low resistance in the switching circuit 53, equivalently producing a low resistance Ra. For example, in the first exemplary embodiment, Ra--(100x10)1(100+ 10)=9.09kn.

Otherwise, the switching circuit 53 is open, which causes adjacent nodes to have a high resistance Rb, for example 1 00M. This allows the current 4, to be low.

The method of operation of the first exemplary embodiment of the invention includes the following steps: generating a switching signal LWPULSE, applying a voltage to a voltage divider 51 to set a bias voltage V., Vb, V, Vd, and V, at each node of a plurality of nodes a, b, c, d, e of the voltage divider 51, wherein the voltage divider 51 includes a plurality of serially connected first resistors (10OkQ) and wherein each node is located between a corresponding adjacent pair of the first resistors; opening and closing a plurality of serially connected switching units S,,, Sb, & Sj, and S, in response to the switching signal LWPULSE, wherein each of the switching units includes a switch SW and a second resistor (1 Okfl) and wherein each of the switching units S, Sb, S, Sd, and S.

is connected in parallel with a corresponding one of the first resistors; and connecting each of the second resistors in parallel with the corresponding first resistor when the switching units S,, Sb, S, Sd, and S, are closed.

The method of operation of the second exemplary embodiment of the invention includes the following steps: generating a switching signal WDPUL-SE, applying a voltage to a voltage divider 51 to set a bias voltage V,, Vb, V, Vj, and V. at each node of a plurality of nodes a, b, c, d, e of the voltage divider 51, wherein the voltage divider 51 includes a plurality of serially connected divider resistors (1 0OM) and wherein each node is located between a corresponding adjacent pair of the divider resistors; opening and closing a plurality of serially connected transistor switching units in response to the switching signal LCDPnSE, wherein each of the transistor switching units includes a transistor switch SW and an internal resistance, and wherein each of said plurality of is transistor switching units is connected in parallel with a corresponding one of the divider resistors; and connecting each of the internal resistances in parallel with the corresponding divider resistor when the transistor switches SW are closed.

The method of operation of the third exemplary embodiment of the invention includes the following steps: generating a switching signal WDPULSE, applying a voltage to a voltage divider 51 to set a bias voltage V,, Vb, V, Vd, and V, at each node of a plurality of nodes a, b, c, d, e of the voltage divider 51, wherein the voltage divider 51 includes a plurality of serially connected pairs of first and second resistors (1OkQ and 901d-2, respectively) and a respective node at one end of each said pair of first and second resistors; opening and closing a plurality of serially connected switches SW in response to the switching signal WDPULSE, wherein each of the switches SW is connected in parallel with a corresponding one of the second resistors; and nullifying the second resistors when the switches are closed.

FIG. 7 shows typical waveforms of the common signals COMI, COM2, and COM3 and segment signals SEGx used to drive the LCD. The LCI) driver 40 is driven by the bias voltages V,,, Vb, V,, Vd, and V,. at the nodes a, b, c, d, e. In accordance with the invention, the bias voltage generator is capable of dynamically providing a smaller 10- equivalent resistance between the nodes so as to minimize the occurrence of spike during switching of the LCD driving signals. At other times, the bias voltage generator is capable of providing a greater equivalent resistance between the nodes so as to lower leakage current through the resistors.

The invention has been described above with exemplary preferred embodiments.

However, it is to be understood that the scope of the invention is not be limited to the disclosed preferred embodiments. To the contrary, it is intended to cover various modifications and similar arrangements within the scope defined in the following appended claims. The scope of the claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Claims

CLAIMS:

1. An apparatus for generating bias voltages for an LCD driver, comprising:

a signal generator for generating a switching signal; a voltage divider, including a plurality of serially connected pairs of first and second resistors and a respective node at one end of each said pair of first and second resistors; a switching circuit, including a plurality of switches connected such that each said switch is connected in parallel with a corresponding one of the second resistors; wherein said switching circuit is responsive to the switching signal to open and close the switches, wherein the second resistors are nulfified when the switches are closed, whereby bias voltages are generated at the nodes when a is voltage is applied to said voltage divider.

2. An apparatus as claimed in claim 1, wherein the first resistor of each said pair of first and second resistors has a lesser resistance value thaii the corresponding second resistor of each said pair of first and second resistors.

3. An apparatus as claimed in claim 1, further comprising an LC1) driver, wherein the bias voltages enable the LCD driver to generate a plurality of LCD driving signals, wherein the LCD driving signals include a plurality of common signals and a plurality of segment signals.

4. An apparatus as claimed in claim 1, wherein said plurality of serially connected first and second resistors forms a DC current path which has a first end coupled to a voltage source and a second end responsive to a standby signal such that the DC current path has no electrical voltage difference between the first end and the second end when the standby signal has an electrical voltage equal to the voltage source.

5. An apparatus as claimed in claim 1, wherein each of the switches is closed when the switching signal is a logic 1 and open when the switching signal is a logic 0.

6. A method for generating bias voltages for an LCI) driver, comprising the steps of (a) generating a switching signal; (b) applying a voltage to a voltage divider to set a bias voltage at each node of a plurality of nodes of the voltage divider, wherein the voltage divider includes a plurality of serially connected pairs of first and second resistors and a respective node at one end of each of said pairs of first and second resistors; (c) opening and closing a plurality of switches in response to the switching signal, wherein each of the switches is connected in parallel with a corresponding one of the second resistors; and (d) nullifying the second resistors when the switches are closed.

7. A method as claimed in claim 6, wherein the first resistors have smaller resistance values than the second resistors.

is

8. A method as claimed in claim 6, wherein said step (c) comprises the steps of closing each of the switches when the switching signal is a logic 1 and opening each of the switches when the switching signal is a logic 0.

9. An apparatus andlor method for generating bias voltages for an LCD driver, the apparatus and/or method being substantially as herein described with reference to the accompanying drawings.