GB2357902A - A semiconductor device having fluorine doped silicon oxide films - Google Patents

A semiconductor device having fluorine doped silicon oxide films Download PDF

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GB2357902A
GB2357902A GB0108233A GB0108233A GB2357902A GB 2357902 A GB2357902 A GB 2357902A GB 0108233 A GB0108233 A GB 0108233A GB 0108233 A GB0108233 A GB 0108233A GB 2357902 A GB2357902 A GB 2357902A
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silicon oxide
oxide film
fluorine
doped silicon
film
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Tatsuya Usami
Hiraku Ishikawa
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NEC Corp
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NEC Corp
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    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02131—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being halogen doped silicon oxides, e.g. FSG
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    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02362—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment formation of intermediate layers, e.g. capping layers or diffusion barriers
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
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Abstract

A semiconductor device has a plurality of interconnections 201 formed on a semiconductor substrate. A first silicon oxide film 202 is formed on the interconnections. A first fluorine doped silicon oxide film 203 is formed on the first silicon oxide film 202. A second fluorine doped silicon oxide film 204 is formed on the first fluorine doped silicon oxide film 203 and has a flattened planar surface and is substantially non-hygroscopic. A second silicon oxide film 205 is formed on the second fluorine doped silicon oxide film 204. The first fluorine doped silicon oxide film may have a thickness of 5000 A, and the second fluorine doped silicon oxide film may have a thickness of 10,000 A. Alternatively, a semiconductor device (Figures 1a, 1b and 1c) comprises a plurality of interconnections 101 formed on a semiconductor substrate, and has a first fluorine doped silicon oxide film 102 filling up the spaces between the interconnections. A second fluorine doped silicon oxide film 103 is formed on the first fluorine doped silicon oxide film 102. The fluorine concentration of the first fluorine doped silicon oxide film 102 is 4 x 10<SP>21</SP> atoms/cc or more, and fluorine concentration of the second fluorine doped silicon oxide film 103 is less than 4 x 10<SP>21</SP> atoms/cc. The second fluorine doped silicon oxide film 103 has a flattened planar surface and is substantially non-hygroscopic.

Description

2357902 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAmE
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor 5' device and a method for manufacturing the same, and more specifically, it relates to a semiconductor d evice having an insulating film and an interfacial insulating film, and a method for manufacturing the same.
2. Description of the Related Art
10! In recent years, with regard to semiconductor integrated circuits, their miniaturization has been advanced, and particularly as for multilayer intercon nections in logic circuits, the above-mentioned tenden cy has been remarkably recognized. When intervals between metals of the multilayer interconnections are fine, a capacity between the adjacent interconnections increases, which leads to the deterioration of an electric signal speed and which also gives rise to a crosstalk (which is a phenomenon that another signal functions as a noise).
As one means for preventing the above-mentioned inconvenxence, there has been a technique of lowering a dielectric constant of an insulating film between metal layers, and nowadays, much attention has been paid to the change from a silicon oxide film formed by a con 2 ventional plasma CVD method (the dielectric constant 4.3) (hereinafter referred to as "the P-S'02 film") t( a fluorine doped plasma silicon oxide film (the dielectric constant.= 2.8 to 4.3) (hereinafter referrd to as "the p-SiOF film") When a fluorine concentration in the p-SiOF film is increased, its dielectric constant can be lowered-, but if the fluorine concentration is excessively increased, its moisture resistance deteriorates inconveniently. Therefore, at such a fluorine concentration that.the moisture resistance does not deteriorate, the dielectric constant cannot constant sufficiently be lowered (the dielectric about 3.3).
For the-sake of a solution of the above-mentioned problem, there is a technique of heightening the density of a plasma itself, and. for example, such a technique has been suggested in SSDM, p. 157 (1995).
This suggested technique can increase the fluorine concentration more than a conventional technique, but when the fluorine concentration is a certain level or more, the deterioration of the filin occurs. For this reason, the dielectric constant cannot remarkably be lowered.
In the case that this p-SiOF film is used as a device, it is essential to flatten this film, but if a 3 chemical machine polishing method (hereinafter referred to as 'TMP") is used as a method for flattening the p SiOF film, the above-mentioned problem of the moisture resistance takes place. In consequence, when the CMP is used, the further increase of the dielectric constant is unavoidable.
As described above, the employment of the CMP in a p-SiOF process has been actually difficult so far.
Howcver, on supposition from conventional examples, two Of experimental examples using the CMP will be described.
In one conventional example, a' p-SiOF film is directly formed-on a metal as shown in Fig. 3. For example, as described in Japanese Patent Application Laid7open No. 333919/1994, a first metal 301 is formed, and a p-SiOF film 302 having a dielectric constant of 3.0 and a fluorine concentrati on of 7 X 1021 atoms,Icc in a wafer surface is-then formed thereon by the use of three gases of SiF4-02 and Ar.in accordance with an ECR-CVD method. If the CMP is carried out to flatten this film, the-film absorbs water, so that the dielectric constant increases inconveniently.
In a worse cas-e, a large amount of introduced fluorine (F) whose bond is weak reacts with H20 to produce HF, so that Phenomenons such as the corrosion of the metal and the disolution of the metal takes 4 place. Here, reference will be made to a case where fluorine concentration i s lowered to about 1.0 x 1o21 atoms/cc.
After the CMP processing, the film is as shown in Fig. 3(B). Next, the film is coated with a photoresist, and align"ment exposure is then carried ou to pattern the photoresist. Afterward, an etching technique, i.e., a magnetron RIE technique using C F 4 8 CO and an Ar gas is utilized to form holes.
Furthermore, after the formation of TiN, blanket WVD is carried out to form a via metal 303 by a flow which is called etch back. Afterward, a continuous sputter.ing of a second metal 304 such as AlCu-TiN is done, and it is then patterned by the photoresist.
This serial operation is carried out once or more to form multilayer interconnections as shown in Fig. 3(c) A problem of this case is that when the fluorine concentration in the p-SiOF film is high, the film absorbs moisture during the CMP processing of the film and when the fluorine concentration in the film is lbw, the dielectric constant increases inconveniently.
In a next example, an Si02 film is sandwiched between upper and lower p-SiOF films to inhibit the hygroscopicity of the p-SiOF films. In Japanese Patent Application Laid-open No. 9372/1995, there has been described an SiOF film formed ina tetraethoxy orthosilicate system (hereinafter referred to as "the TEOS system"), and therefore, description will be made with reference to this technique. Fig. 4 shows its flow diagram.
According to the suggested method, after the formation of a first metal 401, a first p-Si02 film 402 is formed, and a TEOS sy'stem material with which a fluorine containing gas is mixed is then used to form a fluorine doped Si02 film (..a p-SiOF film 403).
Afterward, a second P-Si02 film 404 is further formed thereon.
Here, the plasma SiOF film is formed by a high density plasma CVD method which is advantageous for moisture resistance, particularly a plasma Si02 film high,density plasma CVD method.
In a. conventional example, a parallel plate type pl asma CVD has been used, but in.this example, it is assumed that a 1.aminated film'ls formed by-the high density plasma CVD method.
Here, a fluorine concentration in the SiOF film is 7 X 1021 atoms/cc. After the first-metal 401 has been formed, the continuous growth of S'02/S'OF/S'02 is carried out by the high density plasma CVD method, whereby a constitution shown in Fig. 4(a) or Fig. 4(a)l is obtained. In the case that the p-SiOF film 403 which is an intermediate layer is thick as shown in 6 Fig. 4(a), the p-SiOF film 403 is exposed as in Fig.
4 (b), af ter the CMP processing has been made Although the p-SiOF film has already been sandwiched between tle P-Si02 films in order to control the hygroscopicity of the p-SiOF, the pSiOF film 403 is exposed, and as a result, the film absorbs water during the CMP processing. In consequence, the dielectric constant of the film increases inconveniently.
In order to avoid the above-mentionGd inconveni; ent constitution, the p-SiOF film 403 can be thinly formed film 404 can be thickly formed as and the second S'02 in Fig'. 4 (a)', and in this case, the p-SiOF film 403 iB not exposed after the CMP processing, as shown in Fig., 4(b)l. In such a case, however, the P-Si02 film invades the adjacent metal layer, so that the increase of the dielectric constantoccurs inconveniently.
Afterward, as in the above-mentioned experimental example 1, the via hole formation, the via metal formation and the second metal formation are done in this order, so that multilayer interconnections are formed as in Fig. 4(c) or Fig. 4(c)'.
Fig. 5 shows a relation between a fluorine content in the fluorine-doped silicon oxide film and the dielectric constant in the case that the high density 2-5 plasma CVD is used, and Fig. 6 shows a relation betweer the fluorine content in the fluorine doped silicon 7 oxide film and the hygroscopicity in the case that the high density plasma CVD is used (Semiconductor Integrated Circuit Symposium Manuscript in 1995, p.
45). These drawings show examples of tendencies of the relation between the.fluorine content in the silicon oxide film and the dielectric constant and the relation between the fluorine content and the hygroscopicit.y.
The values of the fluorine content and these charac'-eris.tics depend slightly on a selected dev,-.c.e sometimes, and so they are not always constant, but these drawings indicate the tendencies of the influence of the.fluorine content in the silicon oxide film o n the dielectric constant and the hygroscopicity.
The first problem is that in both of the experimental examples 1 and 2, the dielectric constant increases. the via holes become,abnormal,and metal corrosion occurs, when the p-SiOF film having the low dielectric constant is subjected to the CMP processing.
This reason is that the p-SiOF film having the low dielectric constant absorbs water when exposed to water, so that the dielectric constant increases and the resistance of the via holes become abnormal, and the absorbed water reacts with fluorine to bring about the metal corrosion.
The second problem is that when the p-SiOF film which is the intermediate of the Si02/SiOF/SiO2 structure is thinly formed so as to solve the first problem in the experimental example 2, the dielectric constant between the metallic layers increases. This reason is that a ratio of P-$i02 occupied between the metallic layer is high.
Objects of at least the preferred inients of the present invention are tol prevent the increase of a capacity be layers at the- tim of a high integration particularly in a multilayer interconnection.,t-.ructure of a semiconductor integrate circuit (the realization oflowering a low dielectric constant) and to improve a reliability such as the increase prevention of a via hole resistance.
SUMMARY OF THE INVENTION
In one aspect, the present invention is directed to a semiconductor device which comprises a plurality of interconnections formed on a semiconductor substrate, a first fluorine doped silicon oxide film for filling up spaces between the plurality of interconnections, and a-second fluorine doped silicon oxide film which is formed on the first fluorine doped silicon oxide film and which has a flattened surface and which is free from hygroscopicity.
In another aspect the invention provides a semiconductor device which comprises a plurality of interconnections formed on a semiconductor substrate, a first silicon oxide film formed on the interconnections, a first fluorine doped silicon oxide film formed on the first silicon oxide film, a second fluorine doped silicon oxide film which is formed on the first fluorine doped silicon oxide film and which has a flattened surface and which is free from hygroscopicity, and a second silicon oxide film formed on the second fluorine doped silicon oxide film.
The dielectric constant of the first fluorine doped silicon oxide film may be 13 or less.
The dielectric constant of the second fluorine doped silicon oxide film may be in excess of 3.3.
The fluorine concentration of the first fluorine doped silicone oxide may be 4.0 x 10 atomslcc or more.
The fluorine concentration of the second fluorine doped silicon oxide may be less than 4.0 x 1CP1 atoms/cc.
In a further aspect the invention provides a method for manufacturing a semiconductor device which comprises a step of forming interconnections on a semiconductor substrate, a step of forming a first fluorine doped silicon oxide film, a step of forming a second fluorine doped silicon oxide film, a step of forming a second fluorine doped silicon oxide film which is free from hygroscopicity, and a step of carrying out chemical machine polishing only on the surface of the second fluorine doped silicon oxide film to flatten the surface.
Yet another aspect of the invention provides a method for manufacturing a semiconductor device which comprises a step of forming interconnections on a semiconductor substrate, a step of forming a first silicon oxide film, a step of forming a first fluorine doped silicon oxide film, a step of forming a second fluorine doped silicon oxide film which is free from hygroscopicity, a step of carrying out chemical machine polishing only on the surface of the second fluorine doped silicon oxide film to flatten the surface, and a step of forming a second silicon oxide film.
The first silicon oxide film and the second silicon oxide film may be plasma silicon oxide films.
The first fluorine doped silicon oxide film and the second fluorine dcped silicon oxide film may be high density plasma silicon oxide films, prefer, bly continuously formed.
This application is based on application No.
Heisei 8-140003/1,996 filed June 3, 1996 in Japan,. A cop3 p.f that application is filed herewith as. tbe priority dmnmt forming 'part of this application, the contents thereof being inoorporated herein by referenog.
BRIEF DESCRIPTION OF THE DRAWINGS
For a more complete understanding of this inventi'on, reference may be had to t.he Lol lowing detailed description (which is by way of ale only) with reference to the acompa.
dr-awinp in which:
F ig. 1 is a process flow diagram of a first e. xample.of the present'invention, Fig. 2 is a process.flow diagram of a second example of the present invention, Fig. is a process flow diagram of a first experimental example of a conventional technique, Fig. 4 is a process flow diagram of a second experimental example of the conventional technique, Fig. 5 shows a tendency between a fluorine content in a fluorine doped silicon oxide film and a dielectric constant, and Fig. 6 shows a tendency between the fluorine content in the fluorine doped silicon oxide film and hygroscopicity.
Symbols used in Figs. 1 to 6 represent the following members.
101... First.metal 102... Fii:st p-SiOF film 103... Second p-SiOF film 104... Via metal 105... Second metal.
201 First metal' 202... First-p-Si02 film 203... First p-SiOF-film 204... Second p-SiOF film 205... Second p-Si02 film 206.... Via.metal 207... Second metal 301... First metal 302 p-SiOF film 303... Via metal is 304 Second.meta1 401 First-metal 402 First p-Si02 film 403... p-SiOF film 404.... Second P-S'02 film 405... Via metal 406... Second metal DESMPTIM OF 11E PREFERRED EMBODE.CM A semiconductor device and a method for manufactu ring the semiconductor device of the present invention are characterized by carrying out a serial operation once or more which comprises astep of forming a first fluorine doped plasma silicon oxide, film having a high fluorine concentration on first metallic interconnections formed on a semiconductor 12 substrate surface., a step of forming a second fluorine doped plasma silicon oxide film having a low fluorine concentration, a step of carrying out chemical machin( polishing only on the second fluorine doped plasma silicon oxide film, a step of.making a hole at a desired position, a step of filling the hole with a metal, and a step of forming second metallic interconnections (Fig. 1). Furthermore, it can be presume, that adhesive properties in an interface ere poor or a reaction occurs inconveniently, depending or a kind of metal or a kind of plasma SiOF film. In this case, the present invention is characterized carrying out a serial operation once or more which comprises a step offorming a first plasma silicon oxide film on is. already formed first metallic interconnections, formirg a first p-SiOF film, forming a second pm-SiOF film, and then carrying out a CMP processing only on the second pSiOF film, a step of forming a second p-Si02 thereor.
a step of making a hole at a desired position, a ste p of filling the hole with a metal, and a step of forming.
second metallic interconnections (Fig. 2).
In the present invention, in order to decrease a capacity between the interconnections, at least.spaces between the interconnections are filled up with the fluorine doped silicon oxide film whose a dielectric constant is at least lower than the silicon oxide filn, ( 7 13 and on its surface, there is formed the fluorine doped silicon oxide film which is free from hygroscopicity and which has the high dielectric constant. In consequence, even if a CMP processing is employed, the increase of the dielectric constant by a hygroscopic phenomenon does not occur. Furthermore, even in a subsequent via hole formation step, the fluorine doped silicon oxide film which is the upper layer scarcely exert the hygroscop-'-city, so that the defect of via hole resistance increase does not take place.
Next, the present invention will be described in more detail with reference to drawings.
Referring to Fig. 1,-a first embodiment of the present invention.will be described. As shown in Fig.
15. 1(a), a first p-SiOF film 102 having a thickness of 5000 wasformed on a first metal 101 by a bias ECR-CVD method, and a-second pSiOF film 103 having a thickness of 10000 was further formed thereon. Here, the second p-SiOF film 103 had a fluorine-concentration of less than 4.0 X 1021 atoms/cc, and the first pSiOF film 102 which was formed under the film 103 had, in its wafer surface, a fluorine concentration of 4.0 X 102l atoms/cc which was high than the second.p-SiOF f ilm This plasma SiOF/SiO2 laminate structure is preferably grown in a continuou - s manner, because burying properties are good. However, in the case that 1 1 i i i a problem regarding an operating efficiency of a high density plasma CVD method or another problem is present, these films may be separately grown.
Afterward, a CMP processing was carried out to polish the second p-SiOF film alone as much as about 4000 A as shown in Fig. 1(b). It was confirmed by our 1 experiments that the second plasma SiOF film did not absorb moisture at this fluorine concentration. After ward, a photoresist was appl--'ed onto this film 103, i followed by alignment and exposure to pattern the photoresist. Next, holes were made through the two p SiOF films by a magnetron RIE technique using C4F8, CO and Ar gases.
Furthermore,. a barrier layer of TiN was formed, and a tungsten member was then formed by a blanket WCVE method to accomplish etch back, thereby forming a via metal 104.
Afterward, a continuous sputtering of a second metal 105 of,-for example, AlCu-TiN was carried out, and this metal was patterned through a photoresist.
This serial procedure was carried out once or more to form multilayer interconnections as shown in Fig. 1(c).
According, to the above-mentioned process flow, a capacity between the metal laye. rs could be decreased and the flattening of the film could be accomplished, whereby the multilayer interconnections could be - attained. In this connection, dielectric constants of the first fluorine doped silicon oxide film and the second fluorine doped silicon oxide film in this embod iment were 3.0 and 3.5, respectively.
Next, a second embodiment will be described in detail with reference to Fig. 2.
In the first embodiment, the p-SiOF film is directly formed on the metal, but when adhesive properties between the metal and the p-SiOF film are poor or a reaction of the metal and the p-SiOF occurs inconveniently, depending on the kind of metal or the kind of SiOF film, it is desirable to use the following second embodiment.
AS shown in Fig. 2(a), a first p.Si02 film 202 having a thickness of 1000 A, a first p-SiOF film 203 having a thickness of 4000 A and a second p-SiOF film 204 having a thickness of 10000 AO were grownon a first metal 201 by a bias ECR-CVD met-hod.
A fluorine concentration of the second.p-SiOF film 204 was less than 4.0 X 1021.atoms/cc, and a fluorine concentration of the first p-SiOF film 203 formed thereunder was 4.0 X 1021 atoms/cc or more in a part or all of its wafer surface.
Afterward, a CMP processing was carried out to polish the second plasma p-SiOF film 204 alone as much- as about 4000 It was confirmed by our experiments G_ - 16 that the second plasma SiOF film did not absorb moisture at this fluorine concentration.
on this film, a second p-Si02 film 205 was grown as thick as about 2000 A [Fig. 2(b)].
Afterward, a photoresist was applied onto this film 205, followed by alignment and exposure to patter the photoresist. Next, holes were made through the laminate film of SiO by a 2/twO SiOF f'lms/S'02 magnetl-.Dn RIE technique using C4F8, CO and Ar gases.
Furthermore, as in the first embodiment, a TiN film wa formed, and a blanket W-CVD was then formed to accomplish etch back, thereby forming a via metal 206.
Afterward, a continuous sputtering of a second metal 207 of, for example, AlCu-TiN was carried out, is and this metal was patterned through a photoresist.
This serial procedure was carried out once or more to form multilayer interconnections as shown in Fig. 2(c) The second embodiment has just been described above, but in the first and second embodiments, the continuous sputtering is used for the first metal and the second metal, but as an additive for Al, there may be used Si, Pd or Ti, in addition to. Cu. Moreover, in place of Al, there may be used Cu or Ag. Moreover, Tit is used to prevent reflection, but Ti, TiW, Cr ow Si may be used. Additionally, as the via metal, W-CVD/Tit is used, but W of the via may be replaced with Ag, Cu or Al. As the barrier metal, Ti, TiW, Si and Cr may be used singl y or in a combination of two or more thereof.
Examples of the usable gas for forming the p-SiOF film include SiH4+02+Ar+CF4, SiH4+02+Ar+C2F6, SiH4+02+AX+NF3, SiF4+02+AX, SiF4+SiH4+0 2+Ar, TEOS+02+Ar+CF4, TEOS+02+Ar+C2F6, TEOS+02+Ar+NF 3, TEFS (fluorotriethoxysilane; the same shall apply hereinafter)+02+Ar, TEFS+SiH4+02+Ar and TEOS+SiF4+AX+02,;,nd these gas mixtures from which Ar is omitted may also be used. For the improvement of burying properties, Ar may be replaced with Xe, and the kinds of-gases which are used in the first layer and the second layer may be replaced with each other. For example, SiF4 +Ax+0 2 may be used for the first layer, 151 and SiF4+SiH4+Ar+02 may be used for the second layer.
Furthermore, the p-SiOF is preferably formed by any one of a CVD method of a parallel plate using a frequency of 13.56 MHz, a CVD method of a parallel plate using two frequencies of 13.56 MHz and 400 MHz, a bias ECR-CVD method using a high frequency of 2.45 GHz and a bias of 13.56 MHz, an ICP-CVD method of 2.45 GHz and 13.56 MHz,. and a helicon CVD method, but high density plasma CVD methods such as the bias ECR-WD method, the KPCVD method and the helicon DVD method are more preferable.
Moreover, in order to completely eliminate the 18 hygroscopicity of'the SiOF film after the CMP, a heat treatment at 300 to 4500C may be additionally carried out after the CMP. This treatment may be done in an atmosphere of one or a combination of 02, N2, H2, He o:
q air, or in vacuo.
The thicknesses of S'02 and SiOF are conveniently set for the description of the embodiments, but if the second SiOF alone is processed by the CMP processing, i combination of different t:-,j-cknesses may be obtained.
The second p-SiOF film may be formed in the form of a multi-layer film, provided that a fluorine concentration is in the range of less than 4.0 X 1021 atoms/cc. In addition, if the fluorine concentration is 4.0 X 1021 atoms/cc or more in a part of the wafer of the first p-SiOF layer instead of all of the wafer, the merit of the present invention can be obtained, and therefore such an.embodiment is also covered in the s.cope of the present invention.
Furthermore, the fluorine concentration of the 21 second.p-SiOF film is limited to less than 4-0 X 10 atoms/cc, but the film having-a concentration of this value or more can be used only in a region from which all of the second p-SiOF film is removed.
According to the method of the present invention, a dielectric constant of th-e first fluorine doped silicon oxide film is 3.3 or less, preferably 3.2 or 19 - less,.and its lower limit is 2.8, preferably 2.9. moreover, a dielectric constant of the second fluorine doped silicon oxide film is more than 3.3, preferably 3.4 or more, and its upper limit is 4.1, preferably 3.9.
According to the method of the present invention, a fluorine concentration of the first fluorine doped silicone oxide film is 4 X 1021 atoms/cc or more, preferably 6 X 1021 atoms/cc or more. and its.upper 10, limit is 1.0 X 1022 atoms/cc, preferably 8 X 1021 atoms/cc.
Moreover, a fluorine.concentration of the second fluorine doped silicone oxide film is less than 4 X 1021 atoms/cc", preferably.less than 2 X 1021 atoms/cc, and its lower limit is 1.0 X 1020 atoms/cc.
In this embodiment,.the dielectric constant of the first fluorine doped silicon oxide film is 3.0, and that of the second fluorine doped silicon oxide film is 3.5.
Furthermore, in the first and second embodiments, the etch back is carried out after the blanket WCVD, but a metal CMP may be done. In addition, a selected W-CVD may be done. Moreover, an 02 plasma processing may be carried out for the'improvement of wettability before the CMP of the p-SiOF film and the CMP of the metal.
Furthermore, the lamination of p-SiOF in /P-S'02 the second embodiment is preferably carried out in a continuous growth manner for the improvement of the burying properties particularly in the case of the bias high density plasma CVD method.
The effects of the present invention are as fol.lows.
A first effect of the present invention is that ever when pSiOF films are subjected to a CMP processing, a low dielectric constant film between metal layers can be formed, because the p-SiOF films themselves have moisture resistance. This reason is that the two or more p-SiOF films are formed.and the fluorine concentration of an upper layer which is exposed to a CMP processing is regulated to less than 21 4.0 X 10 atoms/cc to maintain the moisture resistance.
A second effect of the present invention is that structure is formed, a even when an S'02/SiOF/S'02 relatively small capacity between the metal layers is obtained. This reason is that a two SiOF layers/Si02 structure is formed and the CMP processing is then carried out, followed.by the formation of Si02, and therefore, moisture does not invade the film between the metal layers in which the SiO layer as an upper I 2 layer is oriented in an X direction.
21 - Each feature disclosed in this specification (which term includes the claims) and/or shown in the drawings may be incorporated in the invention independently of other disclosed and/or illustrated features.
The text of the abstract filed herewith is repeated here as part of the specification.
objects of at least the preferred embodiments of the present invention are to prevent the increase of a capa city between layers at the time of a high integration in a multilayer interconnection structure and to prevent the increase of a via hole resistance, and a semiconductor device and a method for manufacturing the semiconductor device of the present invention comprises a step of forming a first fluorine doped plasma silicon oxide film is having a relatively high fluorine concentration on first metallic interconnections formed on a semiconductor substrate surface, a step of forming a second fluorine doped plasma silicon oxide film having a relatively low fluorine concentration, a step of carrying out chemical machine polishing only on the second fluorine doped plasma silicon oxide film, a step of making a hole at a desired position, a step of filling the hole with a metal, and a step of forming second metallic interconnections, whereby the above objects can be achieved.

Claims (12)

22 CLAIMS:
1. A semiconductor device which comprises a plurality of interconnections formed on a semiconductor substrate, a first silicon oxide film formed on the interconnections, a first fluorine-doped silicon oxide film formed on the first silicon oxide film, a second fluorine-doped silicon oxide film formed on the first fluorine-doped silicon oxide film and having a flattened planar surface and being::ubstantially non-hygroscopic, and a second silicon oxide film formed on the second fluorine-doped silicon oxide film.
2. A semiconductor device according to Claim 1, wherein said secondfluorine doped silicon oxide film hsis a thickness approximately twice the thickness of said first fluorine-doped silicon oxide film.
3. A semiconductor device according to Claim 2, wherein said first film has a thickness of approximately 5000 A, and said second film has a thickness of approximately 10000 A.
4. The semiconductor device according to any one of Claims 1 to 3, wherein a fluorine concentration of t. first fluorine-doped silicon oxide is 4.0 X 1021 atoms/c or more.
5. The semiconductor device according to any one 23 of Claims 1 to 3, wherein a fluorine concentration of the second fluorine-doped silicon oxide is less than 4.0 X 1021 atoms/cc.
6. A semiconductor device which comprises a plurality of interconnections formed on a semiconductor substrate, a first fluorine-doped silicon oxide film filling up space between the interconnections, and a second fluorinedoped silicon oxide film formed on the first fluorine-doped silicon oxide f--11m, wherein a fluorine concentration of the first fluorine-doped silicon oxide film is 4.0 x 1021 atoms/cc or more, and a fluorine concentration of the second fluorine-doped silicon oxide film is less than 4.0 x 1021 atoms/cc, the second fluorine-doped silicon oxide film having a flattened planar surface and being substantially nonhygroscopic.
7. A method for manufacturing a semiconductor device, the method comprising the steps of: forming interconnections on a semiconductor substrate. forming a first silicon oxide film; forming a first fluorinedoped silicon oxide film; forming a second fluorine-doped silicon oxide film which is substantially non-hygroscopic; carrying out chemical machine polishing only on the surface of the second fluorine-doped silicon oxide film to flatten the surface; and, forming a second silicon oxide film.
24
8. The method for manufacturing a semiconductor device according to Claim 7, wherein said second fluorine-doped silicon oxide film is approximately twic as thick as said first fluorine-doped silicon oxide fil,
9. The method for manufacturing a semiconductor device according to Claim 8, wherein said first fluorin( doped silicon oxide film has a thickness of approximate.' 5000 A, and said second fluorine-doped silicon oxide fi^ hab a thickness of approximately 10000
10. The method for manufacturing a semiconductor device according to any one of Claims 7 to 9, wherein tl first silicon oxide film and the second silicon oxide film are plasma silicon oxide films.
11. The method for manufacturing a semiconductor device according to any one of Claims 7 to 9, wherein tt first fluorine-doped silicon oxide film and the second fluorine-doped silicon oxide film are high-density plasn a silicon oxide films.
12. The method for manufacturing a semiconductor device according to any one of Claims 7 to 9, wherein th first fluorine-doped silicon oxide film and the second fluorine-doped silicon oxide film are high-density plasm silicon oxide films continuously formed.
GB0108233A 1996-06-03 1997-06-03 Semiconductor device and method for manufacturing same Expired - Fee Related GB2357902B (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0469543A2 (en) * 1990-07-31 1992-02-05 Gold Star Co. Ltd Multiple interrupt handling circuit
US5429995A (en) * 1992-07-17 1995-07-04 Kabushiki Kaisha Toshiba Method of manufacturing silicon oxide film containing fluorine

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0469543A2 (en) * 1990-07-31 1992-02-05 Gold Star Co. Ltd Multiple interrupt handling circuit
US5429995A (en) * 1992-07-17 1995-07-04 Kabushiki Kaisha Toshiba Method of manufacturing silicon oxide film containing fluorine

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