GB2352535A

GB2352535A - Micro PCI interface

Info

Publication number: GB2352535A
Application number: GB9908573A
Authority: GB
Inventors: Haght Nicholas Oliver Van
Original assignee: HAGHT NICHOLAS OLIVER VAN
Current assignee: HAGHT NICHOLAS OLIVER VAN
Priority date: 1999-04-16
Filing date: 1999-04-16
Publication date: 2001-01-31
Anticipated expiration: 2019-04-16
Also published as: GB9908573D0; GB2352535B

Abstract

A micro PCI interface 1 provides means to interface computer bus signals, available at a platform independent bus or bus connector 2, to an electronic device or system 7. The interface is designed such that is uses less than the standard number of PCI host bus signals specified in the PCI bus specification. Also, implementation of a PCI interface is possible in a low pin count electronic device.

Description

The invention described herein relates to a micro pedpheral component

interconnect (PCI) interface.

The PCI bus specification provides an important advance in bus design for personal computers and workstations over established bus standards such as the industry standard architecture (ISA), extension to industry standard architecture (EISA) and micro channel architecture (MCA). Some of the significant improvements include processor independence, low power consumption, high transfer rates and auto-configuration.

Notwithstanding the merits of the PCI bus, a designer is nonetheless presented with a complex specification for both PCI interface and circuit board layout for add-on board and/or motherboard designs and, in most cases, this may be further complicated by the need to employ an electronic device with a high pin count in which to implement an interface.

The present invention seeks to provide a micro PCI interface, employable as a prototype platform for the rapid prototyping of PCI add-on board and/or motherboard designs, using an electronic device with a low pin count.

According to the present invention, there is provided a micro PCI interface, comprising a single electronic device and containing means to interface computer bus signals available at a personal computer, workstation or other similar platf orm's expansion bus, to electronic applications, by any application specific integrated circuit, programmable logic device, programmable logic controller, memory or other similar integrated circuit with respect to functionality, complexity, design or any combination thereof, operating as the controller for f he micro PCI interface.

A specific embodiment of the invention will now be described by way of example with reference to the accompanying drawing in which:- Figure I Illustrates the invention in block diagram form.

Referring to the drawing, the micro PCI interface is provided in the form of a single PCI target controller, as shown in drawing I / 1, Figure 1, which is electrically compliant with the PCI bus specification. The controller I is attached to the host bus signals 2 by means of the address and data bus 3, command/byfe enable signals 4, and PCI control signals 5 and 6. An application circuit 7 is attached to the controller I by means of the user data bus 8 and user control signals 9.

The controller 1 provides all the signal buffering between any application circuit 7 and host bus signals 2 and, enables valid transactions between a host computer and application for a PCI target or controller I employing an interface to the address and data bus 3 sized down from the minimum standard 32-bit width, but not restricted thereto. This affords a practical minimum of 23 host bus signals for an 8-bit PCI target interface implementing back-to-back transfers. By way of example, the micro PCI interface can be realised using a programmable logic device with a low pin count, such as a 44-pin J-Iead plastic leaded chip carder (PLCC), when an 8-bit PCI target interface is employed. In comparison, the minimum specification for a 32-bit PCI target interface is 47 host bus signals, and taking info account the number of user, power and ground signals required, a programmable logic device containing a total of at least 100 pins would be necessary for such an implementation.

Data transfers initiated by a host computer are synchronised with the transaction state machine 10. This controls latching of the AD[ I bus 3 and C/BE[] signals 4 at the beginning of a transaction via modules 11 and 12 to capture address and command data respectively. During a host boof or configuration phase, addresses are decoded by the configuration look- up table (LUT) 13 and configuration datG, via the data multiplexer 14 and fristate buffer 15 are returned to the AD[] bus 3 in order to validate the target device or controller I and ensure a listing in a PCI device table generated by a host computer's PCI basic input/output system (BIOS). In addition, the base address register 16 is interrogated and automatically configured with a base address by a host computer.

For subsequent transactions that are not part of a configuration phase, an address latched by module 11 and successfully decoded by the decoder logic 17, enables f he transaction state machine 10 towards the end of a transaction either, to latch data in module 11 and make this available via trii-state buffer 18 for wrife accesses or, enable data multiplexer 14 and tristate buffer 15 for read accesses.

Claims

A micro PCI interface, comprising a single electronic device which contains means to interface computer bus signals, available at a platform independent expansion bus or bus connector, to an electronic device, system or systems, by any application specific integrated circuit, programmable logic device, programmable logic controller, memory or other similar integraf ed circuit with respect to functionality, complexity, design or combination thereof, operating as ar, electrically compliant PCI controller or device for the micro PCI interface.
2. A micro PCI interface as claimed in Claim 1, wherein design means are employed to realise a PCI interface in an electronic device utilising less than the standard number PCI host bus signals specified in the PCI bus specification.
3. A micro PCI interface as claimed in Claim 2, wherein design means are employed to facilitate a PCI address and data bus sized down from the minimum standard 32-bit width, but not restricted thereto.
4. A micro PCI interface as claimed in Claim 3, wherein design means allow the implementation of a PCI interface in a low pin count electronic device.
5. A micro PCI interlace substantially as described herein, with reference to Figure 1 of the accompanying drawing.