GB2352373A - Extracting data from a coded signal by measuring pulse duration - Google Patents

Abstract

The present invention demodulates a coded signal, such as a frequency modulated (FM) signal by measuring the duration of pulses of the coded signal using a high frequency logic clock signal. An edge detector (100, Fig. 2) generates an edge pulse whenever a transition in the coded signal occurs. A time counter (12, Fig. 2) counts the cycles of the high frequency logic clock between the occurrence of two subsequent edge pulses. Then a window comparator (16, Fig. 2) compares the cycle counts with predefined count ranges and generates the time result signal, e.g. 1t, 2t, 3t or >3t. A decoder state machine (20, Fig. 2) post-connected to said comparator samples the time results at every edge pulse, generates a data clock with the decoded data bit (0 or 1) and indicates a frame start signal. The present invention provides demodulation apparatus which is less expensive than a PLL.

Description

2352373 PLL SUBSTITUTION BY TIME MEASURM4ENT The invention relates

generally to method and system of decoding schemes applied to coded serial communication data.

The present invention has a broad field of application, which includes any modern computer system covered with decoding serial communication data. In particular, it can be advantageously applied to biphase encoded schemes.

Generally, the present invention is applicable in any situation in which a complex circuit having the functionality of a Phase Locked Loop circuit (PLL) is used to decode frequency modulated data and the carrier frequency is low compared to any signal present at the decoding site and having a frequency being considerably higher than the carrier frequency.

Thus, the inventional concepts are applicable in a large range of computer systems from a single stand-alone PC, or any computing device being even smaller than a PC to larger systems.

The present invention has a special field of application in a mainframe systems and even more particularly in a high-end system of inter-connected high-performance integrated system clusters in which each cluster comprises a plurality of central electronic complexes further referred to herein as CEC, i.e., some arrangement of high performance mainframe computer and its associated environment.

The present invention will be described with particular respect to such high-end systems as the characterising features of it are particularly needed today preferably in such systems, although its scope is as indicated above.

In such systems the application work is distributed all over the plurality of CECs in multiple clusters. For achieving a good performance the clusters are connected via high-speed optical fibre cables.

Especially in highly sophisticated applications running in such systems having a great need for system stability and reliability like banking applications and similar a proper operation of such a clustered 2 application needs a precisely synchronised and reliably supplied time information in order to have the same time base everywhere in the plurality of clusters. Said time information is often communicated serially with a relatively low frequency of e.g., 16 Mhz whereas at any location in such a high-end system signals having a frequency of several hundred Mhz are present, independently of said time information transmission.

Such a system is described with its requirements concerning the time facility in IBM Journal Of Research and Development, Vol.36, No.4, July 1992, p. 658. Here is expressed that such a strict requirement of system availability implies that the possibility to maintain a plurality of distributed, time sources in each CEC, for example, is excluded. Thus, one central time information supplier is needed for the whole system.

As, however, some degree of time supplier failure safety is required in that prior art system at least two redundant time information suppliers, further exemplarily referred to herein as Sysplex Timers (ST) as they are called in IBM S/390 systems are required. Each ST is in turn connected with an external absolute time source further referred to as ETS, such as Global Positioning System (GPS) time source or the like. Said two STs are connected with the system via particular, dedicated high speed cables. Such a type of system is depicted in fig. 1 where two clusters are depicted, each with a respective ST. To a given time only one of said time sources supplies the plurality of CECs with time information. Time information is synchronised between the two time sources with a dedicated time information line, again. On a failure in said active' time source the other, i.e., stand-by time source replaces the operation of the first.

As can be seen already from the figure a plurality of fibre optic cables transmitting time information serially is required for maintaining such a prior art system. Even in modern systems said time information is often transmitted with 16 Mhz only, i.e., a relatively low frequency, as mentioned above.

At each terminal of such a cable at the input to each CEC a phasedlocked-loop circuit (PLL) is connected in order to demodulate the carrier frequency from of the transmission process in order to extract therewith the 16 Mhz clock signal from the transmitted signal.

Such PLLs are circuits which do not offer the highest safety against failure. Further, they have negative influence on overall system costs.

3 Finally, as it could be desirable in future high end systems to closely integrate a plurality of elements having a PLL functionality on only one chip, conventional PLLs represent regions on the chip which are too large and not calm enough and dist urb the neighbouring regions in said chip. This is particularly disadvantageous in regions in which a further high quality PLL is implemented, for example, to generate a high frequency system clock.

The present invention accordingly provides, in a first aspect, a method for demodulating data from a carrier signal in which said data is coded with characteristic pulse durations determined by respective signal transitions, the method being characterised by the steps of resolving times when subsequent signal transitions of the coded data signal occur, measuring a duration between subsequent of said signal transitions each, associating a measured value with each of said measured durations, associating a decoded data value with each of said measured values which fits best to a respective measured value, providing said decoded data value for further processing.

The present invention accordingly provides, in a first aspect, a method and system for substituting such a PLL circuit by a circuit easily to be realised in a small extent of digital logic.

The present invention provides, in a second aspect, such a method and system to substitute such a PLL in the above mentioned system clusters at locations where it is necessary to restrict chip area otherwise wasted and excited mechanically by prior art PLLs.

The basic idea comprised of the present invention is to omit the PLL for extracting the carrier signal from the coded data signal as a preparing step for obtaining therewith the lower frequency coded data signal from its carrier, but instead, to measure the duration of pulses encoding the data information with aid of a much higher frequency signal which is always present in modern systems as a logic clock independent of the coded data signal.

The decoding procedure is advantageously done by counting the duration of said low frequency pulses in units of logic clock pulses, i.e. , units of the high frequency pulses and associating the count with the particular information coded in the low frequency signal.

4 in particular, the "frame-start" signal of a prior art serial transmission which is three pulses long is associated with a particular admissible range of values, and so it is done with the data=O-signal (two pulses long), the data=l-signal (one pulse long), and the "No-signal" respectively, with specific values each for the admissible range.

In a short summarised form this is done exemplarily by an edge detector which generates an edge pulse whenever a transition in the coded signal, e.g., from level 0 to level 1 or vice versa, occurs. A time counter is connected to said detector which counts the cycles of the high frequency logic clock - compared to the coded signal frequency - between the occurrence of two subsequent edge pulses. Then, a window comparator compares the cycle counts to fit in predefined count ranges or not, and generates the time result signals, e.g., 1t, 2t, 3t, or > 3t. The valid is count ranges are permanently stored in window registers. A decoder state machine post-connected to said window comparator samples the time results at every edge pulse, generates a data clock with the decoded data bit (0 or 1), and indicates a frame start signal or, if the link is broken, activates the output "No-signal". Thus, decoding was successful.

The main advantage of the inventional method and system is that it can be implemented advantageously in micro-coded form for execution by any micro-processor.

Further, the inventional method and system are independent of carrier frequency. It can be adjusted to cover nearly any desired serial transmission rate as the sole requirement would be to adjust the bit size of respective bit locations in the aforementioned time counter, window comparator and window registers.

The inventional concept is applicable to distributed systems having a central clock supply and to possible future systems having distributed clock sources, i.e. in the CECs where they are needed. The sole requirement is the presence of a high frequency signal compared to the frequency of the signal to be decoded.

A preferred embodiment of the present invention is now illustrated by way of example only, with reference to the accompanying drawings in which:

Fig. I is a schematic representation of two prior art inter-connected high-performance integrated system clusters, Fig. 2 is a schematic representation of the implementation of a PLL 5 substitution circuit according to the invention,

Fig. 3 is a schematic representation of some signals relevant during the inventional method, and Fig. 4 is a schematic representation of the control flow of the inventional method showing its essential steps.

With general reference to the introductory part of the underlying description and with special reference now to Fig. 1 two prior art integrated system clusters 10, 12 are depicted each comprising amongst other four CECs 14 (00..03,10..13) interconnected via respective high speed data lines 16.

Two Sysplex Timers, one preferred one 20, and one alternate one 22 are able to deliver time information to both clusters 10, 12 via respective time information transferring cables 18.

They are each connected to the same absolute external time source ETS like GPS or a caesium clock or the like in order to read the correct absolute time with adequate accuracy. There are provided two Sysplex Timers for reasons of operation failure safety.

Said connection is managed by PC stations 24, 26, respectively.

Further, the Sysplex Timers synchronise each other via two lines 28, 30.

Further lines are depicted to other users of the external timing reference (ETR) which are not described explicitly.

At a given time only one of said time suppliers supplies the plurality of CECs with the time, i.e., clock information having a relatively low frequency of e.g., 16 Mhz.

With special reference now to Fig. 2 showing schematically an illustrative implementation of the inventional method, and Fig. 4 showing in turn the most essential elements of an exemplary control flow, a preferred embodiment of hte present invention will be described next below.

6 The coded signal is input into an edge detector 10, step 110. The edge detector captures any signal transition represented by a level change in the coded signal, step 120. The edge pulse is then input into a time counter 12 arranged for counting up, step 130, an event which resets the counter to a value of 10, ready to begin counting. A second permanent input for the time counter 12 is the high-frequency logic clock having a frequency which is advantageously at least 10 times higher than the carrier frequency of the coded signal. Thus, the time counter counts the clock pulses of the high frequency logic clock beginning with the occurrence of the edge pulse, step 140, until the next edge pulse is input into the time counter, initiated by edge detector 10. Thus, the duration of a pulse of the coded signal is measured in units of the logic clock's pulses.

The maximum value, i.e, the end count of the time counter 12 is is forwarded to a window comparator 16 via respective connection lines 18, step 150. Said maximum count value is processed, step 160 to step 200, in the window comparator and it is'determined to which of the predetermined identification values it matches best. Said identification values are the decoded values each. They can simply be calculated by the determination, how many logic clock pulses will fit into the duration of the coded signal frame-start, data=O, and data=1 signal, or "no-signal", respectively.

To do this, for each of the potential measured count values a register is provided, and a logic circuit compares said register value with the best matching predetermined value representing one of the above four signals, steps 160 to 190.

Preferably, there is provided a range delimited by a minimum value for the time I t and a maximum value for the time 1 t, and so on for the other potential values of 2 t, 3 t and >3 t. A simple logic realises the proper association between the 'measured' time count and the best-fit, value, representing the decoded part of the signal.

The result value is input into a decoder state machine 20, step 210, connected to the window comparator 16 which comprises a logic circuit performing some plausibility tests on the data received from the window comparator 16, step 220. For example, the decoder state machine could output an error signal when a data=O or a data=l-signal follows directly to a no signal, value, what corresponds to > 3 t, as between them should be any value corresponding to 'frame-start'.

7 In general, the decoder state machine 20 generates an output which is able to identify the characteristic coding in the coded signal, i.e. it outputs the data clock signal, a frame- start signal, serial data and the idle signal, i.e. "no- signal", step 230. 5 In case the data are not plausible some reasonable prior art actions may be taken such as outputting a respective message and waiting for the next data to be received.

The complete procedure just described above is advantageously microprocessor-controlled. Thus, there is no need for further, dedicated hardware or logic comparable to that one required for a prior art PLL.

In Fig. 3 a schematic representation of the signals relevant during is the above described procedure is given. In the upper line the coded signal coding first a frame-start, then a data=O and then a data=1 signal is shown, as it appears in prior art serial transmission technology. The carrier frequency is denoted as corresponding to a period of 1 t.

For the purpose of completeness a PLL output is supplemented in the second line for comparison just showing the carrier signal. This corresponds to prior art.

In the third line the edge pulse at the output of said edge detector 10 is given. The specific duration of I t, 2 t, 3 t, respectively, between subsequent pulses can clearly be seen.

In the fourth line the signal of the logic clock is given. For a better intelligibility its frequency is depicted smaller than in reality.

However, it is obvious that the specific pulses of the coded signal can easily be counted in units of the logic clock pulse duration. Good results can be achieved when the logic clock frequency is at least 10 times larger than the carrier frequency of the coded signal.

The data clock is depicted in the last line, as it is output from the decoder state machine 20. The specific code of decoded data can be retrieved easily from that signal, as it is qualified with the attributes frame-start', data=O and data=l.

8 CLA124S 1. A method for demodulating data from a carrier signal in which said data is coded with characteristic pulse durations determined by respective signal transitions, the method being characterised by the steps of resolving times when subsequent signal transitions of the coded data signal occur, measuring a duration between subsequent of said signal transitions is each, associating a measured value with each of said measured durations, associating a decoded data value with each of said measured values which fits best to a respective measured value, providing said decoded data value for further processing.

2. A method as claimed in claim 1, wherein said step of measuring a duration between subsequent of said signal transitions comprises the step of between the start time and the end time of said duration counting pulses of a reference signal having a much higher frequency compared to that one of the coded signal.

3. A method as claimed in claim 2, wherein said steps are performed in digital circuits.

4. A method as claimed in claim 3, wherein said steps are coded in micro-code.

5. A circuit for demodulating data from a carriersignal in which said data is coded with characteristic pulse durations determined by respective signal transitions, 9 the circuit being characterised by having means for resolving times when subsequent signal transitions of the coded data signal occur, measuring a duration between subsequent of said signal transitions each, associating a measured value with each of said measured durations, associating a decoded data value with each of said measured values which fits best to a respective measured value, outputting said decoded data value.

6. A circuit as claimed in claim 5, wherein said means for measuring a duration between subsequent of said signal transitions comprises counting means for counting pulses of a reference signal having a much higher frequency compared to that one of the coded signal between the start time and the end time of said duration.

7. A circuit as claimed in claim 5, wherein said means are digital circuits.

B. A circuit as claimed in claim 5, wherein the logic required for performing the steps according to claim 1 or claim 2 are coded in micro-code.

9. A computer system comprising a circuit as claimed in any of claims 5 to 8.

10. A computer system adapted to perform the method as claimed in claims 1 to 4.