GB2349555A - Delay lock loops - Google Patents

Delay lock loops Download PDF

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Publication number
GB2349555A
GB2349555A GB9909827A GB9909827A GB2349555A GB 2349555 A GB2349555 A GB 2349555A GB 9909827 A GB9909827 A GB 9909827A GB 9909827 A GB9909827 A GB 9909827A GB 2349555 A GB2349555 A GB 2349555A
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United Kingdom
Prior art keywords
signals
code
late
early
despread
Prior art date
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Withdrawn
Application number
GB9909827A
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GB9909827D0 (en
Inventor
Anthony Peter Hulbert
Peter Chambers
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Roke Manor Research Ltd
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Roke Manor Research Ltd
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Filing date
Publication date
Application filed by Roke Manor Research Ltd filed Critical Roke Manor Research Ltd
Priority to GB9909827A priority Critical patent/GB2349555A/en
Publication of GB9909827D0 publication Critical patent/GB9909827D0/en
Priority to KR1020000022822A priority patent/KR20010007030A/en
Priority to CN00108151A priority patent/CN1272724A/en
Publication of GB2349555A publication Critical patent/GB2349555A/en
Withdrawn legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J13/00Code division multiplex systems
    • H04J13/10Code generation
    • H04J13/12Generation of orthogonal codes
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69Spread spectrum techniques
    • H04B1/707Spread spectrum techniques using direct sequence modulation
    • H04B1/7073Synchronisation aspects
    • H04B1/7085Synchronisation aspects using a code tracking loop, e.g. a delay-locked loop
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/0016Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/002Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation
    • H04L7/0029Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation interpolation of received data signal

Abstract

Described herein is a method and apparatus for providing improved delay lock loops. In Code Division Multiple Access (CDMA) systems using orthogonal codes, the energy values measured at the 'Early' and 'Late' positions respectively increase and decrease as the timing moves from the 'Prompt' position to these positions due to the degree of orthogonality of other codes present in the signal. By despreading the 'Early' and 'Late' signals with respect to an 'Absent Code', taken from the set of orthogonal codes for the CDMA system, which is never transmitted, an improved loop is provided. An 'Early-Late' data lock loop (100) comprises a 'Wanted Code' generator (36) for providing a first code for despreading a 'Prompt' signal (44) derived from an input data signal (40), and an 'Absent Code' generator (110) for providing a second code for despreading 'Early' and 'Late' signals (42, 46). The despread signals (48', 50, 52') are fed to respective accumulation units (22, 24, 26), and energy values for the 'Early' and 'Late' signals are fed to energy measuring units (28, 30). Outputs (60', 62') from the energy measuring units (28, 30) are compared in comparator (32') to provide a timing error signal (64') for controlling an interpolator (38) receiving the input data signal (40). In a modification (fig.3 not shown), the early, late signals are additionally despread by the wanted code signals.

Description

IMPROVEMENTS IN OR RELATING TO DELAY LOCK LOOPS The present invention relates to improvements in or relating to delay lock loops, and is more particularly, although not exclusively concerned with delay lock loops for use in a mobile telecommunications system.
In a digital demodulator, it is a requirement to align the sample timing of the received data symbols to coincide with the peaks of the responses.
This provides the maximum'eye'opening and therefore the optimum performance. In a direct sequence spread spectrum receiver, this can be done using a so-called'Early-Late'delay lock loop.
An'Early-Late'delay lock loop operates by measuring the despread energy at positions either side of a nominally'Prompt'position. A distance of 1/2 chip is most frequently adopted for measuring these despread energy values. Ideally, when the timing is accurate, these energy values will be equal. When the timing moves towards, say, the'Late'position, the energy value measured here will increase and the energy value at the'Early'position will decrease. The difference between these two energy values gives rise to a classical'S'curve.
Whilst the above approach is suitable for most spread spectrum systems, in a Code Division Multiple Access (CDMA) system using orthogonal codes, problems can arise. In such a CDMA system using orthogonal codes, the energy values measured at the'Early'and'Late' positions do not consist only of the signal or, indeed, of signal plus noise.
There is also a component from the orthogonal codes which at 1/2 chip away will not be orthogonal to the wanted code sequence. The degree of orthogonality loss will be a direct function of the timing offset. As the timing moves towards the'Late'position, the energy value here will decrease reflecting the fact that the interfering codes are becoming more orthogonal.
Conversely, the energy value in the'Early'position will increase, reflecting the fact that interfering codes there are becoming less orthogonal. This effect is in direct opposition to the normal effect discussed above which is utilised.
Furthermore, under certain conditions, which can easily arise for mobile terminals close to a base station in a telecommunications system, these effects may cancel out completely-eliminating the'S'curve or even inverting it.
It is therefore an object of the present invention to provide an arrangement in which one particular code is chosen as a basis for despreading which overcomes the problems mentioned above.
In accordance with one aspect of the present invention, there is provided a method of deriving a timing error signal from one or more processed correlations of an'Absent Code'taken from a set of orthogonal codes for a code division multiple access system.
In accordance with another aspect of the present invention, there is provided a method of providing timing error signal from a received data signal, the method comprising the steps of :- receiving a data signal; forming'Early'and'Late'signals from the received data signal; despreading the'Early'and'Late'signals using at least one generated code ; accumulating the despread'Early'and'Late'signals ; measuring despread energy values for the'Early'and Late'signals; and comparing the measured despread energy values to provide a timing error correction signal; characterised in that the method further comprises the step of despreading the'Early'and'Late'signals with an'Absent Code', taken from a set of orthogonal codes for a code division multiple access system, which is never transmitted.
The method further comprises despreading the'Early'and'Late' signals with the'Wanted Code' ; accumulating the despread signals; measuring the despread energy values for these signals; for the'Early'and 'Late'signals, comparing the despread signals produced using the'Wanted Code'and the'Absent Code'to provide the timing error correction signal.
In a preferred embodiment, the despread signals produced for the 'Early'signals using the'Wanted Code'and the'Absent Code'are compared to produce an'Early'error signal, and the despread signals produced for 'Late'signals using the'Wanted Code'and the'Absent Code'are compared to produce a'Late'error signal, the'Early'and'Late'error signals being compared to provide the timing error correction signal.
In accordance with a further aspect of the present invention, there is provided apparatus for providing a timing error signal from a received data signal, the apparatus comprising: means for receiving a data signal; means for forming'Early'and'Late'signals from the received data signal; generating means for generating at least one code; despreading means for despreading the'Early'and'Late'signals using said least one generated code; accumulation means for accumulating the despread'Early'and'Late' signals; measuring means for measuring despread energy values for the 'Early'and Late'signals; and comparison means for comparing the measured despread energy values to provide a timing error correction signal; characterised in that the means for generating said at least one code comprises first means for generating a'Wanted Code'and second means for generating an'Absent Code', taken from the set of orthogonal codes for a code division multiple access system, which is never transmitted, and in that the despreading means despreads the'Early'and'Late'signals with the 'Absent Code'.
The apparatus further comprises means for despreading the'Early' and'Late'signals with the'Wanted Code' ; accumulation means for accumulating the despread signals; measuring means for measuring the despread energy values for these signals; and for the'Early'and'Late' signals, comparison means for comparing the despread signals produced using the'Wanted Code'and the'Absent Code'to provide the timing error correction signal.
In a preferred embodiment of the present invention, the comparison means comprises first comparison means for comparing the'Early'signals despread using the'Wanted Code'and the'Absent Code'to produce an 'Early'error signal, second comparison means for comparing the'Late' signals despread using the'Wanted Code'and the'Absent Code'to produce a'Late'error signal, and third comparison means for comparing the'Early' and'Late'error signals to provide the timing error correction signal.
The terms'Early'and'Late'are well known terms in the art and no further explanation need be given here.
The term'Wanted Code'refers to the code which is to be extracted from a signal, and the term'Absent Code'refers to a code which forms part of the set of orthogonal codes for a CDMA system is never transmitted.
For a better understanding of the present invention, reference will now be made, by way of example only, to the accompanying drawings in which: Figure 1 illustrates a conventional'Early-Late'data lock loop; Figure 2 illustrates one embodiment of an'Early-Late'data lock loop in accordance with the present invention; and Figure 3 illustrates a second embodiment of an'Early-Late'data lock loop in accordance with the present invention.
Referring initially to Figure 1, a conventional'Early-Late'data lock loop 10 is shown. The loop 10 comprises a filter 12, a three-stage shift register 14, three combining units 16,18,20, three accumulation units 22,24, 26, a pair of energy measuring units 28,30, a comparator 32, a loop filter 34, a'Wanted Code'generator 36, and an interpolator 38. As shown, the filter 12 is connected to receive an input signal 40 comprising a complex baseband signal which is sampled twice per chip and filtered prior to being fed through the interpolator 38. The interpolator 38 has its timing controlled by the loop 10. After being fed through to the interpolator 38 from the filter 12, the signal is then fed to the three-stage shift register 14 which provides samples 42, 44,46 which are nominally,'Early','Prompt'and'Late'with respect to the correct timing. These three signals 42,44,46 are independently despread in units 16, 18,20 by multiplication by the'Wanted Code'produced by generator 36 as shown. Despread signals 48,50,52 are then fed to accumulation units 22,24,26 respectively. The accumulated outputs 54,56 for'Early'and'Late'values respectively are fed to energy measuring units 28,30 respectively where the energy is computed by taking the modulus squared. Accumulated output 58 corresponding to the'Prompt'value is fed out directly. Energy output signals 60,62 are then fed to a comparator 32 where they are subtracted to produce a timing error signal 64 which has zero mean when the error is zero. This timing error signal 64 is fed to a loop filter 34, the output 66 of which controls the interpolator 38.
In accordance with the present invention, there is one particular code which is never transmitted and this code is used as the basis for the despreading of the signals for the'Early'and'Late'positions. In this way, only the components of orthogonal interference will influence the resultant 'S'curve. Thus the'S'curve will always be inverted. This can be compensated by reversing the connections on the comparator 32. An'Early- Late'data lock loop 100 in accordance with one embodiment of the present invention is illustrated in Figure 2. Figure 2 is similar to Figure 1 and identical components are similarly referenced.
The data lock loop 100 shown in Figure 2 has an additional code generator 110 which generates the'Absent Code'which is never transmitted.
In this embodiment, the'Wanted Code'generator 36 is connected to unit 18, which receives the'Prompt'signal 44, for despreading. The'Absent Code' generator 110 is connected to units 16,20, which respectively receive the 'Early'and'Late'signals 42,46, for despreading. Despread signals 48', 50, 52'are fed to respective accumulation units 22,24,26 as before and the energy values for the'Early'and'Late'are determined in energy measuring units 28,30. Signal 58 from accumulation unit 24 is output directly, and signals 60', 62'from the energy units 28,30 are fed to comparator 32'where the inputs are inverted to provide timing error signal 64'. As before timing error signal 64'is filtered by loop filter 34 to provide control signal 66'for interpolator 38.
In the embodiment described with reference to Figure 2, use is made only of the effects of the orthogonal interference. In a second embodiment of the present invention, the correlation of the'Absent Code'can be used to generate energy values corresponding to the effects of varying loss of orthogonality. These energy values can then be subtracted from correlations of the'Wanted Code'only-leaving only the effect due to the'Wanted Code'. This is illustrated in Figure 3. Components described above with reference to Figures 1 and 2 are similarly referenced.
In Figure 3, a data lock loop 200 is shown where further units 210, 212 are provided connected to receive respective signals 42,46 and the 'Wanted Code'from generator 36 to produce despread signals 214,216 respectively. Despread signals 214,216 are fed to accumulation units 218, 220 and then to respective energy measuring units 222,224. As shown, energy value 60'from unit 28 and energy value 226 from unit 222 are fed to a comparator 230 which provides an output signal 232. Energy value 62' from unit 30 and energy value 228 from unit 224 are fed to comparator 32' which provides an output signal 234. Output signals 232,234 are then fed to a further comparator 236 which provides timing error signal 64"for interpolator 38 via loop filter 34.
Although the present invention has been described with reference to specific implementations of timing error detection using the'Absent Code' correlation, it will readily be appreciated that other implementations of timing error detection may also make use of the'Absent Code'correlation.

Claims (9)

  1. CLAIMS: 1. A method of deriving a timing error signal from one or more processed correlations of an'Absent Code'.
  2. 2. A method of providing a timing error signal from a received data signal, the method comprising the steps of :- receiving a data signal; forming'Early'and'Late'signals from the received data signal; despreading the'Early'and'Late'signals using at least one generated code; accumulating the despread'Early'and'Late'signals ; measuring despread energy values for the'Early'and Late'signals; and comparing the measured despread energy values to provide a timing error correction signal for the interpolator; characterised in that the method further comprises the step of despreading the'Early'and'Late'signals with an'Absent Code', taken from the set of orthogonal codes for a code division multiple access system, which is never transmitted.
  3. 3. A method according to claim 2, further comprising despreading the 'Early'and'Late'signals with the'Wanted Code' ; accumulating the despread signals; measuring the despread energy values for these signals; for the'Early'and'Late'signals, comparing the despread signals produced using the'Wanted Code'and the'Absent Code'to provide the timing error correction signal.
  4. 4. A method according to claim 3, wherein the despread signals produced for the'Early'signals using the'Wanted Code'and the'Absent Code'are compared to produce an'Early'error signal, and the despread signals produced for'Late'signals using the'Wanted Code'and the'Absent Code'are compared to produce a'Late'error signal, the'Early'and'Late' error signals being compared to provide the timing error correction signal.
  5. 5. Apparatus for providing a timing error signal from a received data signal, the apparatus comprising: means for receiving a data signal; means for forming'Early'and'Late'signals from the received data signal; generating means for generating at least one code; despreading means for despreading the'Early'and'Late'signals using said least one generated code; accumulation means for accumulating the despread'Early'and'Late' signals; measuring means for measuring despread energy values for the 'Early'and Late'signals; and comparison means for comparing the measured despread energy values to provide a timing error correction signal; characterised in that the means for generating said at least one code comprises first means for generating a'Wanted Code'and second means for generating an'Absent Code', taken from the set of orthogonal codes in a code division multiple access system, which is never transmitted, and in that the despreading means despreads the'Early'and'Late'signals with the 'Absent Code'.
  6. 6. Apparatus according to claim 5, further comprising means for despreading the'Early'and'Late'signals with the'Wanted Code' ; accumulation means for accumulating the despread signals; measuring means for measuring the despread energy values for these signals; and for the 'Early'and'Late'signals, comparison means for comparing the despread signals produced using the'Wanted Code'and the'Absent Code'to provide the timing error correction signal.
  7. 7. A method according to claim 6, wherein the comparison means comprises first comparison means for comparing the'Early'signals despread using the'Wanted Code'and the'Absent Code'to produce an'Early'error signal, second comparison means for comparing the'Late'signals despread using the'Wanted Code'and the'Absent Code'to produce a'Late'error signal, and third comparison means for comparing the'Early'and'Late' error signals to provide the timing error correction signal.
  8. 8. A method substantially as hereinbefore described with reference to Figures 2 and 3 of the accompanying drawings.
  9. 9. Apparatus substantially as hereinbefore described with reference to Figures 2 and 3 of the accompanying drawings.
GB9909827A 1999-04-29 1999-04-29 Delay lock loops Withdrawn GB2349555A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
GB9909827A GB2349555A (en) 1999-04-29 1999-04-29 Delay lock loops
KR1020000022822A KR20010007030A (en) 1999-04-29 2000-04-28 Improvements in or relating to delay lock loops
CN00108151A CN1272724A (en) 1999-04-29 2000-04-29 Improvement of delay locking ring or related to delay locking ring

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Application Number Priority Date Filing Date Title
GB9909827A GB2349555A (en) 1999-04-29 1999-04-29 Delay lock loops

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GB9909827D0 GB9909827D0 (en) 1999-06-23
GB2349555A true GB2349555A (en) 2000-11-01

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2371725A (en) * 2001-01-24 2002-07-31 Ubinetics Ltd A rake receiver wherein each finger has a DLL and at least one has early and late correlators connected via a controllable bandwidth filter to a subtractor
WO2002098010A1 (en) * 2001-05-30 2002-12-05 Koninklijke Philips Electronics N.V. Varying early-late spacing in a delay locked loop
EP1433266A1 (en) * 2001-10-01 2004-06-30 Interdigital Technology Corporation Code tracking loop with automatic power normalization
EP1638216A2 (en) * 2001-10-01 2006-03-22 Interdigital Technology Corporation Code tracking loop with automatic power normalization

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5029181A (en) * 1989-07-17 1991-07-02 Kyocera Corporation Automatic calibration device for direct spectrum spread receiver
US5590160A (en) * 1992-12-30 1996-12-31 Nokia Mobile Phones Ltd. Symbol and frame synchronization in both a TDMA system and a CDMA
US5659573A (en) * 1994-10-04 1997-08-19 Motorola, Inc. Method and apparatus for coherent reception in a spread-spectrum receiver

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5029181A (en) * 1989-07-17 1991-07-02 Kyocera Corporation Automatic calibration device for direct spectrum spread receiver
US5590160A (en) * 1992-12-30 1996-12-31 Nokia Mobile Phones Ltd. Symbol and frame synchronization in both a TDMA system and a CDMA
US5659573A (en) * 1994-10-04 1997-08-19 Motorola, Inc. Method and apparatus for coherent reception in a spread-spectrum receiver

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2371725A (en) * 2001-01-24 2002-07-31 Ubinetics Ltd A rake receiver wherein each finger has a DLL and at least one has early and late correlators connected via a controllable bandwidth filter to a subtractor
WO2002098010A1 (en) * 2001-05-30 2002-12-05 Koninklijke Philips Electronics N.V. Varying early-late spacing in a delay locked loop
US6970499B2 (en) 2001-05-30 2005-11-29 Koninklijke Philips Electronics N.V. Varying early-late spacing in a delay locked loop
US7580489B2 (en) 2001-05-30 2009-08-25 Nxp B.V. Varying early-late spacing in a delay locked loop
EP1433266A1 (en) * 2001-10-01 2004-06-30 Interdigital Technology Corporation Code tracking loop with automatic power normalization
EP1433266A4 (en) * 2001-10-01 2005-02-02 Interdigital Tech Corp Code tracking loop with automatic power normalization
US7010020B2 (en) 2001-10-01 2006-03-07 Interdigital Technology Corp Code tracking loop with automatic power normalization
EP1638216A2 (en) * 2001-10-01 2006-03-22 Interdigital Technology Corporation Code tracking loop with automatic power normalization
EP1638216A3 (en) * 2001-10-01 2007-04-25 Interdigital Technology Corporation Code tracking loop with automatic power normalization
US7529292B2 (en) 2001-10-01 2009-05-05 Interdigital Technology Corporation Code tracking loop with automatic power normalization
EP2056485A1 (en) * 2001-10-01 2009-05-06 Interdigital Technology Corporation User equipment with code tracking loop with automatic power normalization
TWI381660B (en) * 2001-10-01 2013-01-01 Interdigital Tech Corp Code tracking loop with automatic power normalization

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Publication number Publication date
GB9909827D0 (en) 1999-06-23
CN1272724A (en) 2000-11-08
KR20010007030A (en) 2001-01-26

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