GB2347803A

GB2347803A - Digital-to-analogue conversion circuits

Info

Publication number: GB2347803A
Application number: GB9905775A
Authority: GB
Inventors: William Mark Graham; Nigel Robert Kirkwood; Timothy Paul Stretch; Ondrej Tlaskal; Colin Waugh
Original assignee: Racal Research Ltd
Current assignee: Racal Research Ltd
Priority date: 1999-03-12
Filing date: 1999-03-12
Publication date: 2000-09-13
Anticipated expiration: 2019-03-12
Also published as: GB9905775D0; GB2347803B

Abstract

A digital-to-analogue conversion circuit has a wave-shaping circuit 12 generating a return-to-zero (RTZ) analogue reference signal and a synchronisation logic circuit 13. The synchronisation logic circuit 13 synchronises a digital input signal and the RTZ analogue reference signal so that transitions between discrete binary levels in the digital input signal occur when the RTZ analogue reference signal is zero. The synchronised signals are combined in a DAC 10 to produce an analogue output.

Description

DIGITAL-TO-ANALOGUE CONVERSION CIRCUITS This invention relates to digital-to-analogue conversion (DAC) circuits.

In many applications requiring high precision, a DAC circuit should exhibit high linearity and low noise. It is also important that the effects of clock jitter, datadependent errors and interference from other sources of noise be minimised.

In such applications it is customary to use a DAC having no more than two threshold levels because of the inherent linearity of the device. In many cases, a DAC having a single threshold is used, the DAC output being representative of the digital bit stream forming the input data signal.

In order to reduce data-dependent errors it is customary to arrange that the DAC output returns to zero at the end of each sampling cycle. To this end, a return-to-zero (RTZ) reference signal is supplied to one input of a digital-to-analogue converter which switches the polarity of the signal according to the input data signal supplied to another input of the converter via switching logic. Although this arrangement is effective to reduce errors caused by uneven rise and fall times of the transitions between discrete levels in the input data signal and by memory effects due to capacitance in the converter, the effect of clock jitter may nevertheless still be present; moreover, charge recombination effects caused by saturation or depletion of a p-n junction in the switching logic may also contribute to the jitter. With a view to alleviating this problem the inventor has found that it is beneficial to use an analogue RTZ reference signal.

Accordingly, the invention provides a digital-to-analogue conversion (DAC) circuit for processing a digital input signal that switches between first and second discrete levels, comprising analogue reference means for generating a periodic, return-to-zero (RTZ) analogue reference signal, synchronisation means for synchronising the digital input signal and the RTZ analogue reference signal so that the transitions between said first and second discrete levels occur while the RTZ analogue reference signal is at zero, and combining means for combining the synchronized RTZ analogue reference and digital input signals to produce an output signal corresponding to the digital input signal.

In a preferred embodiment, the analogue reference means comprises means for generating a periodic reference signal and wave-shaping means for deriving a RTZ signal from said periodic reference signal, and the analogue reference means may further comprise multiplier means for deriving said RTZ analogue reference signal from the output of said wave-shaping means.

Embodiments of the invention are now described, by way of example only, with reference to the accompanying drawings, of which: Figure 1 is a block circuit diagram showing a digital-to-analogue conversion circuit according to the invention, and Figure 2 shows a wave-shaping circuit used in the conversion circuit of Figure 1.

Referring now to Figure 1, the digital-to-analogue conversion (DAC) circuit includes a digital-to-analogue converter 10 having a first input terminal 11, a second input terminal I2 and an output terminal 0. The DAC circuit also includes a source 11 of a low noise, periodic input signal S, which, in this embodiment, has a sinusoidal waveform, and a wave-shaping circuit 12 arranged to process the input signal S, in order to generate a return-to-zero (RTZ) reference signal Sz which is supplied to the first input terminal I 1 of converter 10. It will be appreciated that the RTZ reference signal Sz is an analogue signal.

A digital input signal SD representing input data is supplied to the second input terminal I2 of converter 10 via a synchronisation logic circuit 13. The digital input signal SD consists of a digital bit stream which switches between discrete binary levels. The synchronisation logic circuit 13 is arranged to synchronise the digital input signal Sp and the RTZ reference signal Sz so that the transitions between the discrete binary levels in the digital bit stream always occur while the RTZ reference signal is at zero. To this end, the synchronisation logic circuit 13, which may take the form of a register for example, receives a timing reference signal SR derived from the input signal S, by means of a phase-shifting circuit 14 connected between source 11 and the synchronisation logic circuit 13.

The analogue output signal So produced at the output terminal 0 of converter 10 corresponds to the digital input signal and is formed as the product of the synchronised signals SZ, SD supplied to the first and second input terminals 11, I2 respectively. Because the transitions between the discrete binary levels in the digital input signal SD occur while the RTZ reference signal Sz is at zero, and, more importantly, because the RTZ reference signal is an analogue signal (and therefore does not involve any switching between discrete levels, as would be the case with a digital reference signal) the output signal So will not suffer the effect of any clock jitter which may be present in the digital input signal, nor will the output signal So suffer from significant charge recombination effects caused by switching between the binary levels.

In this embodiment of the invention, the wave-shaping circuit 12 consists of a returnto-zero (RTZ) circuit 12'having an input connected to source 11 and a multiplier circuit 12"connected between the output of the RTZ circuit 12'and the first input terminal I1 of converter 10.

The RTZ circuit 12'converts the sinusoidal input signal S, into a return-to-zero signal. This can be accomplished by applying a suitable d. c offset to the input signal S, and/or by rectifying the input signal. The d. c offset may be adjusted to match the amplitude of the sinusoidal input signal S,; alternatively, the amplitude of the input signal S, may be adjusted, e. g. using a variable gain amplifier in order to match the amplitude to a fixed d. c offset. The multiplier circuit 12"performs a squaring operation on the RTZ signal produced by RTZ circuit 12'. The squaring operation has two distinct advantages; firstly, it increases the width of the regions over which the RTZ signal is zero and secondly, it reduces any zero offset error that may be present in the RTZ signal. A zero offset error could arise if there is a mismatch between the amplitude of the sinusoidal input signal S, and an applied d. c offset. A rectified input signal could also exhibit a zero offset error, particularly at high frequencies; however, in general, a rectified input signal will have a lower zero offset error over a wider range of input amplitude than can be achieved by the application of a d. c offset, and moreover, can be generated without adjusting the amplitude of the input signal.

An example of a suitable RTZ circuit 12'is shown in Figure 2. This circuit has a differential configuration designed to minimise interference from common mode sources of noise. The current I,, in Figure 2 is set to provide a d. c offset which could, if desired, be adjusted using an optional current source C. It is also possible to rectify the input signal by setting I2 less than I3.

A suitable multiplier circuit 12"providing the afore-mentioned squaring operation is a standard transconductance multiplier circuit. In this case, both inputs to the transconductance multiplier circuit need to be connected to the RTZ circuit 12'. It is also desirable to minimise the bias current applied to the multiplier circuit to ensure that the peak amplitude of the squared output is not significantly attenuated-the circuitry to achieve this could form part of the RTZ circuit 12'.

A transconductance multiplier circuit could also be used to perform the function of converter 10. In this case, one of the inputs to the transconductance multiplier circuit (corresponding to terminal I1 in Figure 1) would be connected to the output of multiplier circuit 12"and another input to the transconductance multiplier circuit (corresponding to terminal I2 in Figure 1) would be connected to the output of the synchronisation logic circuit 13.

The described digital-to-analogue conversion circuit exhibits high linearity and low noise and provides a high precision, high speed operation. The conversion circuit finds numerous applications in circuit requiring high precision processing of digital signals; in one such application the conversion circuit is used in the feedback loop of a Sigma-Delta analogue-to-digital conversion circuit. In these applications, a system clock signal may be derived independently from the same low noise, periodic input signal S, used to generate the reference signals for the DAC circuit of the present invention.

Claims

CLAIMS 1. A digital-to-analogue conversion (DAC) circuit for processing a digital input signal that switches between first and second discrete levels, comprising analogue reference means for generating a periodic, return-to-zero (RTZ) analogue reference signal, synchronisation means for synchronising the digital input signal and the RTZ analogue reference signal so that the transitions between said first and second discrete levels occur while the RTZ analogue reference signal is at zero, and combining means for combining the synchronized RTZ analogue reference and digital input signals to produce an output signal corresponding to the digital input signal.
2. A circuit as claimed in claim 1 wherein the combining means is a digital-to analogue converter having respective inputs for said synchronised signals.
3. A circuit as claimed in claim 1 wherein the combining means is a transconductance multiplier circuit having respective inputs for said synchronised signals.
4. A circuit as claimed in any one of claims 1 to 3 wherein said analogue reference means comprises means for generating a periodic reference signal and wave-shaping means for deriving a RTZ signal from the periodic reference signal.
5. A circuit as claimed in claim 4 wherein said analogue reference means further comprises multiplier means for deriving said RTZ analogue reference signal from the output of said wave-shaping means.
6. A circuit as claimed in claim 5 wherein said multiplier means is a transconductance multiplier circuit.
7. A circuit as claimed in claim 5 or claim 6 wherein said RTZ analogue reference signal derived from the multiplier means is the square of the output of the wave-shaping means.
8. A circuit as claimed in any one of claims 2 to 7 wherein said periodic reference signal has a sinusoidal waveform.
9. A circuit as claimed in any one of claims 2 to 8 wherein said wave-shaping means is arranged to apply to said periodic reference signal a d. c offset matched to the amplitude of the periodic reference signal.
10. A circuit as claimed in any one of claims 2 to 8 wherein said wave-shaping means is arranged to apply gain to said periodic reference signal to match the periodic reference signal to a d. c offset.
11. A circuit as claimed in any one of claims 2 to 10 wherein said wave-shaping means is arranged to rectify the periodic reference signal.
12. A circuit as claimed in any one of claims 2 to 11 including phase-shifting means for deriving from said periodic reference signal a timing reference signal for the synchronisation means.
13. A Sigma-Delta analogue-to-digital conversion circuit having a feedback loop incorporating a DAC circuit as claimed in any one of claims 1 to 12.
14. A digital-to-analogue conversion circuit substantially as herein described with reference to the accompanying drawings.