GB2347777A - Electronic device with multiple substrate materials - Google Patents

Abstract

A electronic device 10 consists of a plurality of stacked interconnecting systems 12, 14, 16 wherein each interconnect system has a substrate of a different material. Each system comprises a substrate carrying circuit elements 18, 28 and having a plurality of connections 24 extending from the upper surface of the substrate to an opposing lower surface. Further connecting tracks 26 are provided between adjacent substrates. Given examples of substrate materials are silicon wafer, glass, ceramic, thin oxide, polymer or printed circuit board. The device may be an addressable matrix with display or detector elements.

Description

Electronic Devices Field of the Invention This invention relates to electronic devices comprising a plurality of circuit elements located on a substrate and in particular, but not exclusively, to devices comprising an array of the same or similar elements located on and/or above a substrate, such as for example matrix addressable devices. The invention also relates to methods for producing such devices and to equipment incorporating such devices.

Examples of matrix addressable devices include active or passive matrix flat panel display devices, imaging devices, microsystem arrays, micromechanical systems, etc.

In this Specification, the terms"upper"and"lower" refer to a device when arrange with the array of circuit elements in a generally horizontal plane and facing upwards.

The term"circuit element"refers to elements with a passive or active function, such as electrodes, light emitting or light sensing elements, optoelectronic elements, micromechanical elements, Radio frequency (RF) elements, various kinds of transducers, or any combination thereof.

The term telectronic deviceŒs used in a broad sense as meaning any device which operates on electronic principles and is intended to embrace devices such as optoelectronic devices, electromechanical devices, radiation sensitive devices, etc.

Background of the Invention Conventionally, devices such as flat panel displays are produced on glass or silicon substrates. This is because these materials are very convenient to use, the surfaces are very smooth and rigid and active elements like transistors can be defined directly under pixels. Contact pads are defined near the edge of the substrate (see Figure 1 of the accompanying drawings). The dey ce is then connecte to the drive electronics using the contact pads. One of the drawbacks of this arrangement is that a significant fraction of the surface area of the substrate is not utilise by the active elements. Therefore the effective display area is reduced by that fraction. Another drawback is that the drive electronics for devices such as a matrix addressable device is accommodated on a separate substrate with interconnecting wires between the drive electronics and the substrate containing the active elements.

There is an increasing demand for devices with higher packaging density, maximum espace utilisation, higher reliability, higher switching speed and mechanical stability. Accordingly, it is an aim of this invention to provide devices, associated methods and equipment which provide improvements in at least some of these fields.

Summarv of the Invention In one aspect, this invention provides an electronic device comprising : an upper generally planar interconnect system forming a substrate for carrying a plurality of upper circuit elements and including a plurality of connecting means connecte to said circuit elements and providing an electrical path to the lower surface of said upper interconnect system, and a lower generally planar interconnect system provided adjacent the lower surface of said upper interconnect system and including a plurality of connecting means electrically connecte to the connecting means of said upper interconnect system and providing an electrical path to the lower surface of said interconnect system, wherein said upper and lower interconnect systems are different.

Examples of interconnect systems include : silicon wafer systems glass systems ceramic systems thin oxide systems (MTO) polymer systems, and printed circuit board systems (PCB).

As technology avances, further systems may develop and so we refer herein to such systems collectively as "interconnect systems".

It should be noted that a silicon wafer is not conventionally regarde as an interconnect system, but in the present invention it may serve as such, by supporting connecting means such as interconnect tracks and vias. All of said systems with the exception of silicon wafer may be either a single or multilayer system ; silicon wafer is always a single layer system.

An interconnect system is characterised by being generally made up of one or more layers of the same material.

Preferred embodiments of the invention overcome at least some of the drawbacks noted with existing devices by using a combination of materials and techniques where a first interconnect system defines a substrate on which the circuit elements are defined and inclues a plurality of connecting means which pass the signal to the lower side of the interconnect system. Instead of the device having contact pads around the edge which connect to a separate board containing the associated processing electronics, in the preferred embodiments the connecting means are used to connect to a second (lower) interconnect system which is attache directly by means of bonding (e. g. chemical, electrochemical etc) or physical attachment to the first interconnect system to provide a hybrid arrangement.

Thus the preferred embodiments allow a composite or modular arrangement where the interconnects are routed in an overall downward direction from the circuit elements on the upper surface of the first substrate means down to the drive or processing electronic circuits which are electrically connecte and may be physically attache to the lower surface of the lowermost interconnect system. Using this concept, almost the entire surface area of the substrate defined by the uppermost interconnect system can be reserved for defining active elements.

Preferably, each of said upper and lower interconnect systems comprises a single or a multiple layer structure of layers of material.

In addition, the device may include one or more further interconnect systems stacked below the lower interconnect system, with the further interconnect systems including respective connecting means for co-operation with the connector means in the other interconnect system to pass electrical signals from the circuit elements to the underlying substrate means, in an overall direction substantially out of the plane of the device.

Preferably, the lower or lowermost interconnect system inclues means for connection to one or more active circuit means for processing signals from, or passing signals to, the circuit elements on the upper interconnect system. For example, the lower or lowermost interconnect system may have attache thereto one or more electronic circuits for processing signals passed to or from the circuit elements on the upper interconnect system.

The connecting means may comprise interconnecting tracks extending generally within the plane of the associated interconnect system, with via means extending from one side of an interconnect system (or a constituent layer) to the other.

In one arrangement, said upper circuit elements make up an addressable matrix device.

The addressable matrix device may take many forms but in one arrangement the upper circuit elements may comprise detector pixels. In another arrangement, said upper circuit elements may comprise display pixels.

The use of the hybrid technology of this invention allows the different interconnect systems to compliment each other with each being selected according to the particular function it is to perform. Thus for example, in one embodiment, a display is provided on a multi-layer ceramic substrate with the drive circuit mounted at the back of the ceramic. In this particular embodiment, a hybrid arrangement is provided which comprises an upper interconnect system defining a substrate of, for example, multi-layer thin oxide (MTO) on which are fabricated active light producing elements. The lower interconnect system in this embodiment could for example be a single layer ceramic system including conductive tracks and interconnect vias.

The single layer ceramic system may be provided with driver electronics circuits on the underside thereof. Both the upper and lower interconnect systems would include interconnected connection means which pass signals from the driver electronics to the display pixels. This particular arrangement has several advantages. The device may employ high conductivity interconnect metals such as copper, aluminium or gold which may be used in conjunction with the multi-layer thin oxide, instead of molybdenum or titanium or tungsten which typically are used for multi-layer co-fired ceramics. In a conventional arrangement using multi-layer ceramics such as aluminium oxide, the co-firing temperature is typically in the region of 1200 C and this exclues the use of copper, aluminium or gold as interconnect metals, due to their low melting temperature. Certain displays require special ceramics such as that referred to as"zero shrink" to ensure that the interconnect tracks and vias are not dislocated during co-firing. The hybrid arrangement of the preferred embodiment described above would not require this because a multi layer ceramic is not used. Accordingly, this may provide a significant reduction in the manufacturing cost of the display.

Furthermore the vias defined in a multi-layer thin oxide system can have a significantly reduced diameter (5 to 10 microns) as compare to multi-layer ceramic substrats where the via diameter is typically of the order of 50 to 100 microns. This is because, in multi-layer structures, the minimum diameter achievable is usually of the same order as the thickness of the layer. In multi-layer ceramic materials, the minimum layer thickness is of the order of at least 50 microns and typically 100 microns. However, in multi-layer thin oxide systems it is possible to achieve several layers of interconnects in a few microns'thickness leading to an increased packing density for conductors. In addition, the much reduced conductor track widths achievable in this manner allow an increase in the definition of the display because a track width of typically up to 10 microns in multi-layer thin oxides is achievable compare to the 100 microns typical track width in multiple layer ceramic materials. Accordingly the pixel size in a device in which the tracks are laid down in the multi-layer thin oxide can be significantly reduced, giving a higher definition display. The use of a multi-layer thin oxide as the upper substrate means that standard optical lithography and semiconductor processing techniques can be used to define pixellated structures on the substrate.

Furthermore, a field emission display comprising a ceramic substrate and a glass faceplate requires a high vacuum seal between the glass (faceplate) and the ceramic substrate. However, on a microscopic scale, the ceramic structure is relatively rough, and high vacuum sealing is far easier to achieve at a glass/silicon dioxide or glass/glass interface than on a glass/ceramic substrate. In addition, an FED requires the shape and location of the microtips to be extremely precisely defined. In a hybrid arrangement in accordance with the present invention, where the microtips are defined on a MTO e-e or glass surface rather than on a ceramic surface, this is easier to achieve because of the greater surface smoothness and reduced surface defects of oxide or glass surfaces compare to ceramics.

In general, it is difficult to produce ceramic substrats which are"defect-free". Various types of defects are created when ceramic powders are mixed and sintered. The resulting surface is far from ideal to produce high-quality devices directly on the surface, especially devices where active elements are very sensitive to surface quality such as field emission cathodes in FE displays. In such a situation, a preferred embodiment of the invention would use the ceramic layer only as a single layer interconnect for connecting the drive electronics at the back and to act as a support. The front face of the ceramic may be coated with an MTO interconnect system (consisting of tracks and vias) using standard semiconductor processing. In another embodiment a single or a multilayer glass interconnect system consisting of tracks and vias may be attache to a single layer ceramic plate, with the drive electronics at the back. The active elements (i. e. the field emission cathodes) can be defined on the glass surface or the MTO which has a much better surface than a ceramic.

Depending on the circuit requirements, the driver electronics for the circuit elements can be mounted directly on the back of the ceramic interconnect system or a further interconnect system (for example a PCB) may be stacked beneath the ceramic and the electronics may be mounted at the back of the PCB.

In another embodiment, to provide an electroluminescent (EL) display such as light emitting polymers (LEPs) a multilayer polymer (e. g. multi-layer polyimide) or a multi-layer thin oxide may be used in a hybrid arrangement with a ceramic or glass interconnect system. Thus a substrate formed by an interconnect system made of one or more polyimide layers supporting a high density of conducting tracks can be used on top of a single or multi-layer ceramic interconnect system, giving a high density of signal lines running through a material of very low dielectric constant.

In this way, the delay in the propagation of signals can be reduced considerably.

With the exception of high vacuum sealing, which is not required for EL displays, all the avantages identifie for field emission displays apply for both light emitting polymer displays and electroluminescent displays in general.

In other embodiments, a multi-layer polymer interconnect system may be used directly on a multi-layer PCB. Electroluminescent displays require very low power to operate and therefore the heat generated is small compare to other types of displays. As a result the polyimide is unlikely to degrade significantly during operation.

The hybrid arrangement of the invention may also be used for other devices such as liquid crystal displays (LCDs), plasma display panels (PDPs) and vacuum fluorescent displays (VFDs) etc, and any combination thereof, resulting in highly compact and high definition displays.

Furthermore, the hybrid architecture may also be used for imaging devices such as charge coupled devices (CCDs) which have a plurality of pixellated arrays of sensing elements which will benefit very significantly from the hybrid arrangement. Again the architecture will mean that these devices will be more compact, with faster response times and less expensive to produce.

Still further, the hybrid arrangement may be used for any light emitting or light sensing devices, optoelectronic devices, micromechanical devices, RF devices, various kinds of transducers etc. or any combination thereof which can be fabricated on a glass, silicon or ceramic substrate and where a significant number of connections are required to be made to active elements, including light producing, light sensing, radiation detection, etc.

In another aspect, this invention provides a method of producing an electronic device which comprises the steps of: 1. providing an upper generally planar substrate means 2. forming a plurality of circuit elements thereon 3. providing a plurality of connecting means passing between said circuit elements and the lower surface of said upper substrate means.

4. providing a lower generally planar substrate means 5. providing a plurality of connection means electrically connecte to the connecting means of said upper substrate means and passing to the lower surface of said substrate means, wherein said first and second substrate means comprise different interconnect systems (as herein defined).

The invention also extends to electronic equipment incorporating an electronic device as described above.

Whilst the invention has been described above, it extends to any inventive combination of the features set out above or in the following description.

The invention may be performed in various ways and, by way of example only, various embodiments thereof will now be described by way of example only, reference being made to the accompanying drawings, in which : Figure 1 is a schematic view of a prior art flat panel display device ; Figure 2 is a cross-sectional view through a hybrid interconnect system in accordance with this invention ; Figure 3 is an exploded view of a passive matrix electroluminescent device in accordance with this invention, and Figure 4 is a exploded view, similar to Figure 3, but showing an active matrix electroluminescent device.

Referring initially to Figure 2, there is shown a display or an imaging device 10 in accordance with this invention. In this example, the device comprises three stacked interconnect systems, namely a two-layer thin oxide (MTO) interconnect system 12, a single layer ceramic interconnect system 14 and a two-layer PCB interconnect system 16. The upper MTO interconnect system has formed thereon and in conjunction with the above layer an array of circuit elements, here in the form of column electrodes 18 which form in conjunction with row electrodes 20 an X-Y addressing grid. On top of the upper substrate formed by the upper interconnect system is a display/imaging layer 22.

Each of the systems 12, 14 and 16 comprises an interconnect system made up of filled vias 24 and conductive tracks 26 to provide the required interconnect topology between the active circuit elements 18 on the upper surface of the upper substrate 12 and a number of driver chips 28 provided on the lower surface of the lower system 16.

Referring now to Figure 3, there is shown schematically a passive electroluminescent display 30. The display is built up on a hybrid interconnect structure comprising a multi-layer thin oxide substrate 32 as the upper layer and a ceramic or glass single layer system 34. Each of these systems is provided with interconnects and filled vias in a similar manner as shown in Figure 2, to provide the required interconnects between a driver chip 36 attache to the lower surface of the lower substrate 34 and the column electrodes 40 of which only two are shown. From the column electrodes 40 upwards, the structure is fairly conventional.

Accordingly the structure comprises a transparent face plate 42 (e. g. of glass), transparent row electrodes 44 (e. g. of indium tin oxide (ITO)) a first insulator layer 46, a phosphor layer 48, and a second insulator layer 50.

Referring now to Figure 4, the active matrix electroluminescent device is again built up on a hybrid structure, here comprising an upper substrate 52 of silicon wafer, silicon on insulator (SOI) or polysilicon and a lower system 54 of ceramic or glass. As previously, a driver chip 56 is shown attache to the lower surface of the lower system 54 and the required interconnect topology between the driver chips 56 and a number of switch transistors 58 is provided by vias and tracks 60, 62 respectively. Stacked above khis, from the top layer down, are a transparent sealing plate 64, transparent electrodes 66, a first insulator layer, a phosphor layer 70, a further insulator layer 72.

The design and manufacture of suitable interconnect systems as described above is well within the competence of one skilled in the art, suitable guidance being obtainable from publications such as"Microelectronic Materials", CRM Grovenor, IOP Publishing Ltd 1989, and"Handbook of Polymer Coatings for Electronics", J. J. Licari, L. A. Hughes, Noyes Publications 1990, the entire contents of which are incorporated herein by reference.

The embodiments described above each comprises a hybrid arrangement of two or more interconnect systems, where an interconnect system is defined as a single or multi-layer arrangement of conductive tracks or vias in a particular material. Several distinct interconnect systems have been described above. In all devices the circuit elements are generally defined on the upper surface of the top system and the driver electronics is electrically connecte and may be physically attache to the back of the lower system.

Claims (8)

1. Claims 1. An electronic device comprising : an upper generally planar substrate means carrying a plurality of upper limit elements and including a plurality of connecting means connecte to said circuit elements and passing to the lower surface of said upper substrate means, and a lower generally planar substrate means provided adjacent the lower surface of said upper substrate means and including a plurality of connecting means electrically connecte to the connecting means of said upper substrate means and passing to the lower surface of said lower substrate means, characterised in that said first and second substrate means comprise different interconnect systems (as herein defined).
2. 2. An electronic device according to Claim 1, wherein the or each of said upper and lower substrate means comprises a multiple layer structure of layers of material.
3. 3. An electronic device according to Claim 1 or Claim 2, which inclues one or more further substrate means stacked below said lower substrate means, said further substrate means including respective connecting means for co-operation with the connector means in the other substrate means to pass electrical signals from the circuit elements to the underlying substrate means, in an overall direction substantially out of the plane of the device.
4. 4. An electronic device according to any preceding Claim, wherein the lower or lowermost substrate means inclues means for connection to one or more active circuit means for processing signals from or passing signals to the circuit elements on the upper substrate means.
5. 5. An electronic device according to any preceding Claim, wherein said connecting means comprise one or more of : interconnecting track portions extending generally within the plane of the associated substrate means, and via means extending in a direction generally through the plane of the associates substrate means.
6. 6. An electronic device according to any of the preceding Claim. wherein aid upper circuit elements make up an addressable matrix device.
7. 7. An electronic device according to any of the preceding Claims, wherein said upper circuit elements comprise detector pixels.
8. 8. An electronic device according to any of the preceding Claims, wherein said upper circuit elements comprise display pixels.