GB2347304A - Multitrunk ATM termination device with inverse multiplexing - Google Patents

Abstract

A termination device (fig 1) for connection to a group of TDM (time division multiplexed) trunks is capable of sending cells over one or more links (10<SB>0</SB>-10<SB>7</SB>) either individually or as part of an inverse multiplexed group. The device includes a Utopia interface (1) for receiving an incoming cell stream, a buffer (2) for storing incoming cells at specific memory locations identified by pointers obtained from a queue of available pointers, a round robin scheduler (5) for sequentially assigning cells to links forming an IMA group or individually in the UNI mode, and a pointer queue for each channel address, the pointer queue indicating the location of the next cell to be transmitted for each virtual channel. An adaptive shaper (4) determines when a stuff cell is inserted and a per link output circuit places cells on the links, which can operate in CTC or ITC mode. The device can operate in mixed mode where up to four IMA and/or up to eight UNI channels can be supported concurrently. The links assigned to the IMA or UNI channels is programmable. A termination device (fig 2) for receiving cells streams from individual links or a plurality of links forming an IMA group is also disclosed. The device comprises an input circuit (30<SB>0</SB>-30<SB>7</SB>) for receiving cells from each link, a cell delineation circuit (31<SB>0</SB>-31<SB>7</SB>), means for separating control cells from user cells and a buffer memory (38) for storing incoming cells of an IMA group. An inverse schedule (39) is provided for arranging incoming IMA cells into the correct order. A controller is provided to direct IMA cells to said memory or to an output circuit should the device be operating in the UNI mode.

Description

2347304 MULTITRUNK ATM TERNINATION DEVICE This invention relates to

asynchronoas data communi ations and in particular to a device designed for sending ATN4 or like cells over transmission links, for example T 1 or E I trunks..

Reference is made throughout this specification to cells. These cells are typically

ATM cells, which are small packets of fixed size having a payload of 48 bytes and a header of five bytes.

In order to meet the increasing bandwidth demands of ATM (Asynchronous Transfer Mode) a technique is known that combines a number of slower TDM fmks, such as T I and E I links, into an aggregate channel of higher bandwidth. A tectui ique for do ing this is known as Inverse Multiplexing for ATM (WA) and is described in the ATM Forum standard AF-PHY-0086.000.

ATM cells are subject to variable delays over the different links, and a protocol must be established to reconstruct the original cell stream at the receiving end. In accordance with the ATM Fortim standard, an IMA Frame -is defined and special cells, defined as IMA Control Protocol cells (ICP), are trai3smitted once per WA frame.

When a a-ansmitter is preparing to send ATM cells over an IMA channel, it must identify a group ofNphysical links that are to make up the channel. It then assigns a Link Identifier (LID) to each link and transmits this to the far cad in 1CP cells. This is a logical link -identifier between 0 and 3 1, witich is different from the physical identity ofthe lilk The ATM cell% are then twumitted over the identified links in a cyclic fashion in ascending order based on the LM assigned to each physical link. The receiver assembles the incoming cells according to the asccndwg order based on the link 1D.

The IMA protocol defines an IMA frame that -is defined as M consecutive cells on each link- The DfA fi=es are transmitted simultaneously on each link. An ICP cell is sent on each link once per DvIA frame. An offset number identifies the position of the JCP cell, which can be different for each link. If there are no ATM layer cells to be sent in an UAA k:arne, filler cells arc trammittcd to maintain a continuous stre= of cells at the physical layer- While the need for aggregate bandwidth is sometimes present, that is not always the case, arid sometimes it is desirable to set Lip a standard UNTI (User Network rnterface) mode on each link.

An object of the invention is an efficient and cost-effective device capable of 5 providing both an DAA and a UNI (User Network [ntcrface) protocol interface.

According to the present invention a termination device is a termiDation device for connection to a group of TDM (time division multiplexed) links comprising an interface circuit for receiving an incoming cell stream forming one or more virtual channels; a buffer memory for storing incoming cells at memory locations identified by pointers; a pointer queue for each virtual channel, said pointer queue i-Idicating the memory locations of queued cells in each channel; a control unit for interrogating the pointer queue and assigning the next incoming cell to the next free memory location for the associated channel; a scheduler selectively operable to sequentially assign cells from each queue in said buffer memory either to individuat links or to a group of Links forming an inverse multiplexed group,- and a per link output circuit for placing cells from said memory locations on said lbik-s to foun outgoing virutat channels- The interface circuit is preferably provides a Utopia level 2 interface for connection to an ATM adaptation layer device. The links are physical links in the PDH (Plesiochronous Digital Merarchy) network transporting the data, for example TI or El trunks- Depending upon whether the device -is in UNI mode or IMA mode, a channel will consist of a single link or a group of physical links having an aggregate baudwidth equal to the sum of the bandwidth of the individual links. In IMA mode, the round robin scheduler distributes successive ATM cells as determined by their address pointers to successive physical links in ascending order based on their link ID numbers. In UNT mode, the successive ATM cells are passed directly to the outgoing link associated with their chanael.

The -input circuit preferably includes filtering Rinctions. An address is assigncd to each channel, which can eitber be an MA ch=nel consisting of a group of physical finks or a UNI channel consisting of a single linkThere can be eight LN[ links and up to 4 TMA groups, so that 12 Utopia addresses are provided.

The invention also provides a termination device for connection to a group of TDM (time division multiplexed) links and capable of receiving streams of cells forming a virtual cbannel over one or more of said trunks, said celi streams aniving on said individual links or on a plurality of said links forming an inverse multiplexed (IMA) group, comprising a per link input circuit fbr receiving incomin cell streams on said links; a per link cell delineation circuit for delineating mcoming cells; a per Iiak means for segregating control cells from user cells; a per group rate recovery block to generate the IDCR (B4A Data Cell Rate); a buffer memory for storing incoming cells of an IMA group at specific memory locations; a per group inverse schcduler controlled by the IODCR and for arranging incoming cells of an DAA group in the correct order', an output circuit for outputting cells to a receiving device through an interface; and a memory controller selectively operable to direct incoming cells to said memory in an inverse multiplexing mode or to said output circuit in a UNI mode.

The invention WI'll now be described in more detail, by way of example only, with reference to the accompanying drawings, in which.

Figure I is a block diagram of a termination device for sending ATM cells over one or more Uunks; and Figure 2 is a block diagram of a termination device for receiving ATM cells from one o r more trunks.

The tmnsn-dt and receive blocIcs are independent and work independently to provide support for WA options such as the asymmetric operations and independent clocking modes.

The transmit device shown in Figure I bas Utopia level 2 interface I and eight outgoing PCM TI trunks 100 - 107- As is well Imown in the art, Tl trunks provide digital physical links operating at 1-54M bits/sec. In ATN4 model the ATM adaptation layer (AAL) takes incoming data segments into to fixed size packets, calJed cells, of 53 bytes each. The transmitting device is capable of assigning ATM cell streams from the ATM adaptation layer to individual trunks or to WA channels forn-led by aggregating the individual tunks.

lucoming channels in the Utopia interface are assigned addressees, which are user programmable. The interface complies with the Utopia specification level 2 for an 8-bit interface. The Utopia interface does not require a buffer since the incoming cells are stored in buffer memory block 2 in a manner to be described. The buffer block 2 providing the internal transmit memory comprises 4096 bytes of mercory divided into 64 blocks of 64 bytes each. Each block can store one ATM cell, which is actually only 52 bytes long, since the header contains one byte forming the Error Check Sequnce (ECS) which is not storedvith the rest of the cell, but rather is generated when the cell is transmitted. The remaining 12 bytes -in each block are used for memory location pointers.

Cell control unit I I feeds the incoming ATM cells to the buffer block 2 at the next free memory location, which is identified by a pointer. Each Utopia address, i.e. each channel, wbether it be a single UNT channel or an aggregate D4A channel, has a pointer queue associated with it In addition, there is a queue for unused or free pointers.

For each Utopia address, the control unit I I interrogates the pointer queue, idcntifies die next free pointer for that address, and then places the next incoming ATM cell into the memory location identified by that pointer. The number of ATM cells that can be assigned to any Utopia queue is programmable between 0 and 15.

The pointer queuc indicates the location in. the memory where thLe next ATM cell received at the Utopia interface -is located. If the device is operating in the UNII mode, then the pointer indicates the location of the next cell to be sent on the physical link 100 10'r In IMA mode, the round robin scheduler 5 moves the pointer fToni the Utopia pointer queue to the appropriate PCM link pointer queue so as to feed the next cell to the appropriate outgoing physical link in accordance with the MA scheduler. This will be the next sequential logical link in ascending order.

In addition to determining which cell is to be trarismitted on which physical link, 2-5 the round robin scheduler 5 also determines when it is time to send an ICP cell or a user cell. It will be recalled that the ICP cells are transmitted once per WA fi-ame with a given offset that may vary from link to link. lfno user cells are ready to be transn-dtted a filler cell - is sent instead. When a cell has been transmitted, its associated pointer 'is returned to the free pointer queue.

The level of the mansmi't queue for each link that is part of an MA group is monitored and compared to the level of one fink, designated a reference link, of the same WA group. When a specific difference value is reach4 a stuff cell is inserted in the queae of the link to compensate for the difference in the clock speed of each link. When a stuff cell is tansmitted, the round-robin scheduler handles the ICP cells by controlling the link stuff cell indication bits and inserting the additional ICP cell as reqecL This is determined by an adaptive shaper block 4, which determines when a staff cell is to be inserted. Two different algorithms can be selected: onc to support the Common Transmit Clock mode which defines a fixed rate of stuffing events; and an adaptive algoritbm to support the Independent Transmit Clock mode where each link can operate with their own independent clock frequencies.

IDCR (114A Data Cell Rate) generator 4 couuts the total number of ATM cells (rC.P and stuff cells excluded), that are transmitted over a reference link during a specified time interval. This time interval is based on the sYstern clock and is ffilly progra-mrnable. The interval deterwines the accuracy of the Il)CR.

The IIDCR generator 4 controls the round-robin scheduler 5 and instructs it when to accept new ATM user cells from the Utopia interface 1, as required to minin-dze cell delay variation (CDI./).

When there is room available in the transn-dt buffer 2, which is in the form of a FIFO, a new user CCU can be accepted from the Utopia interface 1. The size of the FIFO In the warismit buffer 2 effects the CDV (cell delay variation). The cells from the buffer 2 are output through ICP cell modifier unit 20 to the per link- ftwsmit PCM block 3, which includes a parallel to serial converter for placing the cells on the outgoing ILiks as a serial bit stream.

The ICP cell modifaer unit 20, modifies the content of some bytes of the ICP cells that are unique for each link--as required by the RAA protocol. The use of the ICP CCU modifier enables the definition of a common ICP cell for an WA group that is modified as required and minimizes the on-chip storage space and provides flexibility to adapt to future changes.

The content of the ICP cells, the Mler cell, and the idle cell is fully programmable through a microprocessor (not shown) connected to in-ilcroprocessor interface 15.

In UNI mode, the IDCR generator and the ICP cell modifier are by-passed since no IDCR calculation is required, and no ICP or stuff calls are inserted. When a particular PCM link 10() to 107 is ready to accept anotimr cell, if no cell is waiting in the tninsmit buffer 2, an idle cell is sent. The transmit buffer 2 can accept up to 15 ATM cells per 5 link. It is fully programmable.

The transmit blocks 3 pmvide flexibility in PCM format and allow various clocking and framing modes- Eacb PCM link opemtes independently to support the ITC clocking mode, asymmetric operation and concurrent operation of up to four 34A groups and up to eight links in UNr mode.

A mechanism to detect the presence of a clock has been added. The user can find out if a clock is present on any of the eigbt receive clocks, eight transmit clocks, or four PLL REF clock signals- There are various options in the wansuiit unit that are programmable, such as the scrambling mode )n block 20, the use of the ATM cosec value to add to the HEC eader calculation, and the use of various counters and filters- The receive unit, shown in Figure 2, comprises a per Liak PCM receive block 300 to 30-7, a per link cell delineation unit 3 10 to 317, and ICP cell processing unit 320 to 327, and IMA state machine 330 to 337. The ICP processing unit segregates the ICP cells and passes the link information to link information registers 34 and select ed ATM cells to the ICP Cell baffer with changes 35. The outputs of the link information register 34 and the cell buffer 35 are passed on to microprocessor interface 36 for forwarding to the extemal microprocessor-(not: shown) for validation and processing.

The cell delineation units 3 10 to 317 look at the incoming data on a byte-by-byte basis and try to achieve ATM cell delineation- The ICP processing unit 320 to 327 verifies the vaUdity of an incoming ICP cell and reports a problem when a violation occurs. It also handles the stuff cells based on information contained in the ICP cells. Through programming registers (not shown) the user has fall control over the conditions where it can accept or reject an incoming stuffincg, cell. The user can also select wbich of the first or second ICP cells is dropped when a stuff event occurs.

The 34A state machine is implemented in accordance with the IMA specifications on a per link basis.

When the receive RvIA process is enabled, the valid ATM ceUs that are received are Ed to RAM controller 37 for the ATM cells to be stored in the external RAM 38.

The DfA Data Cell Rate (IDCR) calculation is carried out in rate recovery unit 40 by counting the total number of ATM cells (ICP and stuff cells excluded) received over the reference link during a specific time intervaL This time interval is based on the system clock and is programmable. The interval will determine the stability of the IDCR and a default value will be determined from simulation results. The RX IDCR is the basis fbT the ATM cell to be transferred to the Utopia f/F and is used as well to control the Inverse" round-robin scheduler 39 The external static memory 38 is used to store the received ATM cells from each link and to absorb various transmit delays between links that are part of the same EqA group. The external memory configuration is limited to six combinations- This is required to control the generation of the address and is limited to reduce the load on each signal connected between the device and the external memory devices.

The use of the memory is flexible and two different mapping methods can be selected: the entire niernory can be divided 18 blocks of the same size (1 block is assigned to eacb link)- This is refiermd as direct addressing mode. Alternatively, the entire memory is divided in 256 blocks and the uumber of blocks assigned to each link is progmmmable. This is referred to as pointer addressing mode. The later method utilizes chains of pointers that are assigued to each PCM link- The total number of ATM cells that can be stored is limited by the memory configuration. The delay betweec the Links that is allowed is progrararn able and the user has to ensure that he is riot exceeding the size of the memory. The maximum delay is programmable and can be either in increments of 1 cell when direct addressing mode is used or in increments of 16 ATM cells as a minimum when pointer addressing mode is used The selected implementation to re-sequence the ATM cell strearn uses "aligned" read pointers and "floating" write pointers as descri-bed ja Appendix B.5 of the DtA specification- The amount of delay is programmable through the use of internal pointers.

The difference between the read and write pointers provides all the required information about differeritial delays between links of an TNI-AA register also keeps track of the maximum delay between the link with the least delay and the Link with the most delay. This is updated for every B4A frarne. An error condition is reported if dus 5 value exceeds the prograrnmed maximum delay value.

The round robin scheduler is controlling the read pointers for each group or link and moves the ATM cells from external memory to the intemal Utopia RX FlPO 41. The ICP cell and filler cells are dropped before they are put -in the Utopia RX FIFO.

The ro and robin scheduler automatically handles the order by using the LD:) 10 information, The Utopia -interface 42 is between the RX FIFO 41 and a Utopia bus. One address for each link- (in LM mode) and 1 address for each RAA group (in BIA mode) are supported. No underflow condition can exist and an overflow is recorded as an error condition when detected. In BAA mode, this buffer is set to 4 cells and in UNI mode, it is 15 set to 2 cells- In UNTI mode, most of the receive fUnctional blocks are bypassed. The cell is received by the PCM block, then it is passed to the Cell Delineation block and then goes to the RX FIFO, if the cell. is good (1-eno error). The idle and errored cells are discardedThe received cells are not stored in the external static memory and no external memory is 20 required. There is no calculation of the IDCR or delay between links.

The current implementation supports concurrently up to four D-1A groups and up to eight UNT links. Each UAA group has its own rate recovery block 40, RX scLLeduler block 39 to support concurrent RAA group operation, both of which rnin CDV- Each B&A group and each UNT link has its own RX Utopia FIFO 41 which provides for 25 concurrent operation of RAA channels and UNI channels.

The use of buffer memories and pointers provides for flexibility and delivers support for IVA with minimal additional cost, both 114A and UNI modes can operate at the sarne time in the same device without additional cost.

The pointers are also a key element 'in the stuff cell timing on. the transmit side and 30 in the implementation of the round-robin scheduter, On the receive sid--, the pointers are used to implement there-sequencer and calculate the various delays between the links. The pointers provide flexibility in the aniount of delay each WA group can accon-unodate. The method of determining the IDCR -is simple and programmable. It integTates the data rate through the PCM reference link by using the system clock to count 5 the number of cells transmitted during a time interval.

The schedulers automatically handle the insertion of user cells, filler cells, 1CP cells, and staff cells in MA mode and the user or idle cells in UNI mode. The 1CP cell modifier provides for a flex ible use of a common ICP cell for each NA group and provides the flexibility to assign any PCM link to any RvIA group. The flexible cell hnntiler on the receive side detects and processes the 1CP cells and the stafCcells based on parameters selected by the user or ignores the ICP cells when configured in Un modeThe transmit and receive schedulers automatically handle the LID of the Links.

On the transmit side, the user has the option to select the value of M (the number of cells in an 114A fi-anie), the reference link number, the size of the FIFO, the transinit clock- mode and the narnber of links. In the receive side, the receive blocks can operate, with four different values o FM and the user can specify the reference timing link or the circuit can extract the information from the incoming 1CP cells- The receiver block extracts the operational values from the received 1CP cell and makes it available to the user for validation through registers and through the RX ICP cell buffeLs. Once the 134A process is enabled, the receive block monitors the SCCT field of the ICP cell and signals the user when a new 1CP cell arrives that requires processing.

The PCM modes allow. direct connection to most exist-Ing TI/El framers. The transmit and receive blocks are independent to support simultaneous T I and E I operatioa inside the same device and to support asymmetrical operation. The transmit clock can be selected from any of the eight receive clocks or from any of four external references. The device can be configured to operate In CTC or ITC mode under software control without any support from extemal circuitry. A circuit is also provided to detect the presence of clock and synchronization signals to assist during diagnostics.

A significant advantage of the invention -is that the device can be used in mixed mode whereby sorne of the links are in TMA mode and other Links are in UNI mode. This offers complete flexibility to the user.

The device as described is capable of permitting links with bigger or shorter delays to be added without disruption. It can support, for example, up to 4 independent PAA groups. The number of physical links assigned to an LMA group can be programmable, for example, between I and 8.

There are also test modes that provide access to the internal and external memory in most of the blocks from the microprocessor interface.

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Claims (17)

Claims:

1. A termination device for connection to a group of TaM (time division. multiplexed) links comprisingan interface circuit for receiving an incoming ceU stream forming one or more virtW channels; a buffer memory for storing incoming cells at memory locations identified by pointers; a pointer queue for eacb virtual channel, said pointer queue indicating the memory locations of queued cells in each channel; a control unit for interrogating the pointer queue and assigning the next incoming cell to the next free memory location for tbLe associated channel; a scheduler selectively operable to sequentially assign cells &om each queue in said buffer memory either to individual links or to a group of links forming an -inverse multiplexed group,-) and a per link output circuit for placiD cells from said memory locations on said links to form outgoing virtual channels.

2. A terrn=-tion device as claimed in claim 1, wberein said scheduler is a round robin scheduler.

3- A tem-iination device as claimed in claim 1, wherein said scheduler also determines assigns filler cells and control cells to said outgoing virtual channels.

4- A termination device as claimed in any one of claims I to 32, wherein said buffer memory comprises a FIFO.

S. A temiination device as claimed in claim 4, farther comprising an MA data cell rate (IDCR) generator for controlling said scheduler to request new user ceUs from said input c4rLdt to minimize cell delay variation.

6. A tennination device as claimed in claim. 5, wheremi said JDCR generator counts the number of cells transmitted over a reference link during a predetermined time interval.

7. A termination device as claimed in claim 6, wherein said IDCR generator detem-Lines said time interval from a system clock.

0

S. A termination device as claimed in claim 1, wherein said interface circuit provides Utopia compliant interfiace.

9. A termination device as claimed in claim 1, wherein said per link output circuit includes a parallel to ser W, converter for placing said cells on said links as a serial bit stream.

10- A termination device as claimed in claim 3, further comprising a control cell modifying circuit upstream of said output circuit to modify said control cells in accordance with the inverse multiplexing protocol.

11. A termination device for connection to a group of TDM (time division multiplexed) links and capable ofreceiving streams of cells fora-iing a virtual channel over one or more of said tnus, said cell streams arriving on said individual links or on a plurality of said links fo=1ing an inverse multiplexed (MA) group, compnisinga per I i rLIc input circuit for receiving incoming cell streams on said links; a per link cell delineation circuit for delineating incoming cells; a per link means for segregating contro I cells from user cells; a per group rate recovery block to generate the MC.R (2vfA Data Cell Rate); a bui-Ter memory for storing incoming calls of an EqA group at specific mernory locations; a per group inverse scbeduler controlled by the IDCR and for arranging incoming cells of an EIAA group in the correct order-, an output circuit for outputting cells to a receiving device through an interface; and a memory controller selectively operable to direct incoming cells to said memory in an inverse multiplexing mode or to said output circuit in a UK mode.

12- A termination device as claimed in claim 11, wherein said iriterface is a Utopia interface.

13- A termination. device as claimed in clairn 11, wherein said buffer memory -is operable in a first mode wherein the buffer memory is divided into a plurality of blocks assigned to respective links, and a second mode wherein the buffer memory is divided into a larger number of blocks, varying numbers of blocks can be assigned to each Enk under program control.

14. A termination device as claimed in claim 11, wherein the user can program a guardband to mi'n further recovery disruption when a link is added to an existing DAA group thereby opti m izng the recombiner delay.

15. A tennination device as claimed in claim I I dia can interface to cxistiog T1 or El framers through a versatile PCM intcrface-

16. A termination device as claimed in claim 10that can accept a programmable amount of differential delay for each operational RAA group.

17. A termination device substantially as hereinbefore described with reference to the accompanying drawings.