GB2347258A - Matrix array bistable devices - Google Patents

Abstract

An addressing scheme for a matrix array bistable device, such as a ferroelectric liquid crystal device which exhibits a t V minimum, utilises a strobe waveform comprising first and second time slots in which the voltage is non-zero and the polarity of the voltage is the same. Furthermore the voltage in the first time slot and the voltage in the first time slot of each data signal are selected such that the resultant of the select data signal and the strobe signal in the first time slot is of a lower voltage than, and produces a greater switching torque than, the resultant of the non-selected data signal and the strobe signal in the first time slot, so as to cause switching in one case and no switching in the other case. This enables the optimum torque to be approached for each time slot of the addressing scheme for much lower data voltage levels than those required in prior art addressing schemes, and in turn enables faster line address times to be achieved together with lower power dissipation and higher contrast ratio.

Description

"Matrix Array Bistable Devices" This invention relates to matrix array bistable devices, having particular, but not exclusive, application to high information content ferroelectric liquid crystal (FLC) display and spatial light modulator devices.

Such devices typically comprise a layer of chiral tilted smectic ferroelectric material contained between two cell walls carrying two sets of electrodes which typically cross one another to form an x-y matrix of addressable elements or pixels at the electrode intersections. One or both of the cell walls is arranged to be transparent so that the liquid crystal material may act to modulate incident light.

One such device is the surface stabilised ferroelectric liquid crystal (SSFLC) device of Clark and Lagerwall (US Patent No. 4367924) which can be switched between different molecular orientations by electrical pulses of appropriate polarity.

Such devices operating in the chiral smectic C phase (denoted SmC*) are of particular interest because of their speed of operation and memory characteristics. In the SmC* phase the liquid crystal molecules (or more properly the director n which represents the average direction of the long molecular axes) may rotate about the smectic layer normal in a conical manner in response to an applied electric field. Furthermore the device is arranged to have planar homogeneous alignment on one or both of the internal surfaces of the device and the liquid crystal material is chosen to have a smectic A phase at temperatures higher than the operating temperatures.

During the manufacturing process, the device is cooled through chiral nematic and smectic A phases to give suitable alignment of the smectic layers at the operating temperatures of the ferroelectric phase. The presence of the chiral nematic phase aids the formation of uniformly aligned smectic layers if the chiral pitch is sufficiently high above the smectic transition, in accordance with the teaching of Bradshaw and Raynes (US Patent No. 5061047). Following this procedure, the combined effects of the aligned layers and molecular director leads to optical bistability. When electrical pulses of appropriate polarity, amplitude and duration are applied to appropriate electrodes of such a device, the director profile will be in one of two states corresponding approximately to director orientations on opposite sides of the cone of possible orientations. These states may be distinguished optically, for example when the device is viewed between crossed polarisers. This bistability results from the combined effects of surface anchoring and the smectic layer geometry.

It is the memory characteristics of the device that are of particular importance in multiplexed FLC displays since it enables the image to remain in the desired state between addressing cycles of the liquid display. Moreover, the applied electric field couples to the spontaneous polarisation of the ferroelectric liquid crystal material enabling pulse latching times of ten microseconds duration or faster. Simply reversing the polarity of the applied signal allows the opposite state to be latched.

In its preferred implementation the invention is concerned with the provision of drive signals which may be used to address the pixels of a ferroelectric liquid crystal display. Many such addressing schemes have been described in the literature, including two-slot, two-field schemes by Harada et al (SID 85 Digest,"An application of Chiral Smectic C Liquid Crystal to a Multiplexed Large-Area Display", paper 8.4, pp 131-134) and two-slot schemes of Saunders et. al. (European Patent Publication No. 0306203) and described by Surguy et al (Ferroelectrics, 1991, Vol 122 pp 63-79,"The JOERS Alvey Ferrroelectric Liquid Crystal Multiplexing Scheme"). In such addressing schemes, the liquid crystal display has first and second sets of driving electrodes usually arranged orthogonal to one another and defining a matrix of pixels within the liquid crystal layer with the electrodes on opposite sides of layer.

The most common type of addressing scheme uses a sequence of strobe signals applied to the first set of electrodes of the display (for example the row electrodes) whilst the relevant data signals are applied to the second set of electrodes (for example the column electrodes). Each strobe signal applied to the first set of electrodes is designed to include a portion, termed the strobe, which defines which of the rows is being addressed at any instant. Furthermore each data signal applied to the second set of electrodes (the columns) is usually of one of two types, one of which is designed to induce switching into the other state (denoted S for select data) and the other of which is designed not to induce switching (denoted NS for non-select). The data waveform must be DC compensated within each line address or discrimination period, with the result that it is often a simple bipolar pulse. The strobe and data signals combine to form a resultant voltage waveform across each pixel of the addressed row to give the desired image. The duration of the data signals which combine with the strobe signal to discriminate between pixels to be latched into a new state and those that are intended to remain unchanged is termed the line-address-time. Once a row of the display has been written in this way, the strobe signal is applied to another row of the display and the data signals are changed correspondingly.

Following the teaching of Hughes and Raynes (British Patent No. 2262831), the strobe waveform for one row may extend into the following row or rows to complete the latching process (in those pixels of the previously addressed line at which the data was arranged to cause switching). Each frame may be divided into two fields in which each row is addressed with strobe pulses of opposite polarity. In one field, the pixels that receive the select data signal (and resultant) are switched into one state (for example black) whereas, in the other field, the same data signal becomes the non-select signal and does not effect switching. Pixels which received non-select data in the one field receive select data in the other field and are switched into the opposite state (for example white). Alternatively, each frame may consist of a single field where each row is blanked into one state (usually black) ahead of the applied strobe waveform.

The performance of the addressing scheme is related to the shape of both the strobe and data waveforms. Many schemes are based on two-slot data waveforms in which the two slots (duration T) have equal amplitude but opposite polarity to ensure DC compensation. One data wave form is then (+Vd,-Vd) and the other data wave form is (-Vd, +Vd). In the prior art addressing scheme of Harada, et. al. (ibid.), the strobe signal also comprises two pulses of equal magnitude Vs and opposite polarity. In a second prior art addressing scheme (Ayliffe British Patent No. 2146473, Ayliffe and Davey British Patent No. 2173336 and Ross British Patent No. 2173629) the first slot of the strobe signal is zero volts and the second slot is Vs. This is sometimes referred to as the monopulse addressing scheme. It is significantly faster than the earlier addressing scheme because the Vs pulse acts on the ferroelectric liquid crystal material in a largely relaxed state. Hughes described a further modification of this scheme in US Patent No.

5398042 in which the first slot of the strobe signal is not zero, but is a voltage pulse which acts to slow or speed up both the S and NS resultants. This movement of the operating window is useful for operating at different temperatures.

The monopulse addressing scheme has particular advantage when applied to ferroelectric liquid crystal materials which exhibit a minimum in the response timevoltage characteristic, as described in Surguy et. al. (ibid.). Such a TV minimum occurs due to the effect of the dielectric torques (dominated by the dielectric biaxiality & ) acting to oppose the switching torque from the ferroelectric polarisation Ps, thereby acting to slow the switching process. When operated about such a minimum, the device operates in"inverted mode" (that is it is the lower voltage part of the resultant that aids switching, rather than higher voltage part of the resultant). Other addressing schemes have been designed to operate with such materials, including the DRAMA schemes (British Patent Publication No. 9526270.5) which have three or more slots to allow shaping of the S and NS resultants, thereby improving the speed of the select waveform and giving wide operating ranges. Various other advantages result, including low power, low pixel pattern dependence and high contrast, as discussed in Jones et al., Asia Display 98, pp. 967-970,"Addressing TVmin Ferroelectric Liquid Crystal Displays".

Again DC balancing is maintained in each line address time of the data using schemes such as (+/Vd, ~I+ Vd, 0) and (T/2Vd,-/+Vd,-/+Vd), etc.

It is an object of the invention to provide an improved addressing scheme having particular application to the addressing of ferroelectric liquid crystal devices which exhibit a fiv minimum.

According to the present invention, there is provided a matrix array bistable device comprising an addressable matrix of elements switchable between first and second states, first and second sets of electrodes crossing one another at the locations of the elements, data drive means for applying data signals to the first set of electrodes, each data signal including first and second time intervals within a discriminating period and being of one of two types, that is either a select data signal or a non-select data signal, and strobe drive means for applying strobe signals to the electrodes of the second set of electrodes in succession so as to switch those elements to which the select data signals are applied from the first state to the second state under the effect of the resultant of the data and strobe signals applied to said elements during the discriminating period and so as not to switch those elements to which the non-select data signals are applied, characterised in that each strobe signal comprises first and second time intervals within the discriminating period in which the voltage is non-zero and the polarity of the voltage is the same, and the voltage in the first time interval of each strobe signal and the voltage in the first time interval of each data signal are selected such that the resultant of the select data signal and the strobe signal in the first time interval is of a lower voltage than, and produces a greater switching torque than, the resultant of the non-select data signal and the strobe signal in the first time interval.

A preferred implementation of the invention provides a novel approach to addressing of ferroelectric liquid crystal devices which exhibit a TV minimum. As with the DRAMA addressing schemes described above, this invention uses the fact that, in addressing of such devices, very high voltages (defined with respect to d. Ps/ & .) of a polarity which tends to induce switching can have a reduced, sometimes zero, switching torque as compared with some lower voltages. Where this invention differs from the prior art is that the first slot of the strobe waveform is higher than that required to maximise the switching torque at the outset of the line address time. Thus discrimination between the select and non-select data waveforms results from the data voltage lowering the resultant voltage to cause switching in the one case, and increasing the resultant voltage to a level to provide a lower switching torque in the other case.

This enables the optimum torque to be approached for each slot of the addressing scheme (including the first slot) for much lower data voltage levels than those required in the prior art addressing schemes described above. This in turn enables faster line address times to be achieved together with lower power dissipation and higher contrast ratio than is normally possible using the prior art addressing schemes.

The invention also provides a drive circuit for a matrix array bistable device comprising an addressable matrix of elements switchable between first and second states and first and second sets of electrodes crossing one another at the locations of the elements, the circuit comprising data drive means for applying data signals to the first set of electrodes, each data signal including first and second time intervals within a discriminating period and being of one of two types, that is either a select data signal or a non-select data signal, and strobe drive means for applying strobe signals to the electrodes of the second set of electrodes in succession so as to switch those elements to which the select data signals are applied from the first state to the second state under the effect of the resultant of the data and strobe signals applied to said elements during the discriminating period and so as not to switch those elements to which the non-select data signals are applied, characterised in that each strobe signal comprises first and second time intervals within the discriminating period in which the voltage is non-zero and the polarity of the voltage is the same, and the voltage in the first time interval of each strobe signal and the voltage in the first time interval of each data signal are selected such that the resultant of the select data signal and the strobe signal in the first time interval is of a lower voltage than, and produces a greater switching torque than, the resultant of the non-select data signal and the strobe signal in the first time interval.

In order that the invention may be more fully understood, reference will now be made, by way of example, to the accompanying drawings, in which: Figure 1 is a block diagram of a drive circuit used in a FLC display; Figure 2 is a diagrammatic vertical section through a FLC display; Figure 3 is a graph of voltage against switching line for a FLC material exhibiting a FLC material exhibiting a TV minimum; Figure 4 shows the strobe, data and corresponding resultant waveforms for a first prior art addressing scheme in which a bipolar strobe waveform is used; Figures 5a and 5b show the strobe, data and corresponding resultant waveforms for two forms of a second prior art addressing scheme in which a monopulse strobe waveform is used, Figures 5c and 5d showing variants of such an addressing scheme; Figure 6 illustrates a basic principle of line-at-a-time addressing in which the row waveform includes a suitable blanking pulse ahead of the strobe pulse; Figure 7 shows theoretical plots of the voltages which give maximum and zero torque for different orientations of the director about the smectic C cone, calculated for a typical FLC material; Figures 8a and 8b are graphs similar to that of Figure 3 showing the operating ranges for different pixel patterns, Figure 8a showing the results obtained using the addressing scheme of Figure 5a, and Figure 8b showing the results obtained using the DRAMA addressing scheme; Figure 9 shows the strobe, data and corresponding resultant waveforms for a basic two-slot addressing scheme in accordance with the invention; Figure 10 shows the strobe, data and corresponding resultant waveforms for a further addressing scheme in accordance with the invention in which the second slot of the strobe waveform has higher amplitude than (but the same polarity as) the first slot; Figures 11 la and l lob show the strobe, data and corresponding resultant waveforms for a three-slot addressing scheme in accordance with the invention in which the last slot has the same voltage in both the N and NS data waveforms. Figure 11 a showing the preferred embodiment of the present invention in which the voltage is increased successively in the second and third slots of the strobe waveform, and Figure l lb showing an example in which the voltage in the second slot of the strobe waveform is reduced; Figures 12a, 12b and 12c are graphs similar to that of Figure 3 showing the operating ranges for different pixel patterns, Figures 12a and 12b showing the results obtained with a three-slot addressing scheme in accordance with the invention, and Figure 12c showing the results obtained using a four-slot addressing scheme in accordance with the invention; and Figure 13 is a plot illustrating a step in a design process which may be used in designing an addressing scheme in accordance with the invention.

The FLC display 1 shown in Figures 1 and 2 comprises a layer 7 of ferroelectric liquid crystal material in the smectic phase contained between two glass substrates 2 and 3 arranged parallel to one another and sealed at their edges by strips 4. Oppositely facing sets of electrodes 5 and 6 of transparent tin oxide are applied to inwardly directed faces of the substrates 2 and 3 and are in the form of electrode tracks arranged in rows and columns which cross one another to define an x-y matrix of addressable pixels within the liquid crystal layer 7 at the electrode intersections. The pixels are addressable by the application of suitable strobe and data signals to the intersecting electrode tracks. As is well known, the sets of electrodes may take other forms in other types of display to which the invention is applicable. For example the electrodes may be in the form of radial and curved tracks in a rO display, or in the form of segments in an alphanumeric display.

Polarisers 8 and 9 are applied to the outer surfaces of the glass substrates 2 and 3, and in addition a thin polymer alignment layer (not shown), for example a polyamide alignment layer, is applied to the inwardly directed face of each set of electrodes 5, 6 and is rubbed in a required rubbing direction in the manufacturing process in order to impart a preferred surface alignment direction to the molecules of the liquid crystal layer 7, the rubbing directions of the two alignment layers being parallel or antiparallel to one another.

The switching of the pixels of the display 1 is controlled by row and column drivers 10 and 11, a data waveform generator 13 for supplying S and NS data signals to the column driver 11 so as to apply such signals in parallel to the column electrode tracks, and a strobe waveform generator 12 for supplying strobe signals to the row driver 10 so as to apply strobe signals to the row electrode tracks sequentially on a line- by-line basis. If required, a blanking waveform generator 15 may be provided for supplying blanking pulses to the row driver 10 so as to apply blanking pulses to the row electrode tracks sequentially on a line-by-line basis in advance of the strobe pulses. As is well known, application of a blanking pulse to a row electrode track sets all the pixels along the row to the same state (usually black) irrespective of the data waveform applied to the column electrode tracks, and a subsequent strobe pulse applied to the row electrode track causes switching of selected pixels to the opposite state (usually white) according to which pixels are controlled by S data signals applied to the corresponding column electrode tracks. Overall control of timing and display format is provided by a control logic unit 14. It will be understood that the sequential application of the strobe signals to the row electrode tracks on a line-by-line basis may be such that the rows are addressed in any convenient order, that is not necessarily with adjacent rows being addressed one after the other across the display.

Figure 3 is a plot of the line-address-time (l. a. t.) against peak strobe voltage for a commercial FLC material SCE8 at a temperature of 25 C and aligned in the C2U alignment state measured with alternating pulses of opposite polarity, of duration T and amplitude V separated by periods of 100 1. It will be seen that the material exhibits a TV minimum due to the effect of the dielectric torques acting to oppose the switching torque from the ferroelectric polarisation. When operated about such a minimum, the material may be operated in the inverted mode in which switching is effected by the lower voltage part of the resultant, rather than by the higher voltage part of the resultant as is the case in use of conventional bipolar addressing schemes.

Figure 4 illustrates the prior art bipolar addressing scheme of Harada et al. (ibid.) utilising two-slot data waveforms comprising first and second time intervals or slots of equal duration-c and equal amplitude Vd but opposite polarity to ensure DC compensation, and the strobe waveform also has two slots of equal duration T and equal amplitude Vs but opposite polarity. As may be seen in Figure 4, the select data waveform is of the form (+Vd,-Vd) and the non-select data waveform is of the form (-Vd, +Vd), so that the select resultant waveform S is of the form (-Vs-Vd, +Vs+Vd) and the non-select resultant waveform NS is of the form (+Vs-Vd,-Vs+Vd). It will be appreciated that, in this case, the device is not usually operated in the inverted mode.

Figures 5a and 5b show two forms of an alternative prior art addressing scheme, termed a monopulse addressing scheme, which uses a FLC material exhibiting a IV minimum and which is operated in the inverted mode. Figure 5a shows the basic JOERS Alvey addressing scheme in which the strobe waveform comprises two slots of equal duration T, but in which the voltage in the first slot is zero whereas the voltage in the second slot is Vs. In this case the non-select data waveform is of the form (+Vd, -Vd) and the select data waveform is of the form (-Vd, +Vd), so that the non-select resultant waveform NS is of the form (-Vd, +Vs+Vd) and the select resultant waveform S is of the form (+Vd, +Vs-Vd). The zero voltage in the first slot of the strobe waveform means that the select resultant waveform S includes a pre-pulse of amplitude Vd in the first slot. By a suitable choice of the FLC material and the device structure and operation of the device about (and above) the TV minimum, the provision of such a pre-pulse can be particularly advantageous. In particular the device can be caused to operate in the inverted mode in which latching occurs for the lower voltage Vs-Vd but not for the higher voltage Vs+Vd. Furthermore the provision of the monopulse st. obe waveform means that most of the switching occurs during the second of the two slots of the select resultant waveform S of magnitude Vs-Vd. This voltage is preceded by a prepulse of magnitude +Vd which acts in the same direction as the switching pulse, thereby assisting latching and leading to a fast response time. In the case of the non-select resultant waveform NS, the high voltage pulse Vs+Vd is preceded by a pre-pulse-Vd of opposite polarity which impedes latching. Thus this addressing scheme leads to much faster latching than the bipolar addressing scheme of Figure 4, and has a much wider operating region (in other words the select resultant waveform S is fast and the nonselect resultant waveform NS is slow).

Figure 5b shows the strobe data and resultant waveforms for a modification of such a monopulse addressing scheme, as described in US Patent No. 5398042. In this case the voltage in the first slot of the strobe waveform is not zero but is a positive voltage +a. The non-select data waveform and the select data waveform are the same as in the previously described monopulse addressing scheme, whereas the non-select resultant waveform NS is of the form (-Vd+a, +Vs+Vd) and the select resultant waveform S is of the form (+Vd+a, +Vs-Vd) so that the added voltage pulse a serves to slow or speed up both the S and NS resultants.

Comparing Figure 4 and Figure 5a and 5b, it should be noted that the same data waveform acts as the select pulse for normal mode operation (Figure 4) and as the nonselect pulse for inverted mode operation (see Figures 5a and 5b), and similarly the same data waveform acts as the non-select pulse for normal mode operation and as the select pulse for inverted mode operation. However the described addressing schemes are given by way of example only, and any of these schemes may be operated in either normal mode or inverse mode, depending on the operating conditions.

There are several modifications to the strobe waveform which can be used to increase performance. For example the strobe waveform may be extended either into the preceding row or into the following row as shown in Figure 5c, so that more than one line is addressed simultaneously. In both cases the line address time is reduced significantly but at the cost of a reduced operating range. Of the two options, it is preferable to extend the strobe waveform into the following row since this leads to a lower operating voltage. Furthermore such a scheme provides a particularly powerful technique for global temperature compensation. Another modification that may be applied is to increase the magnitude of the strobe waveform towards the end of the switching period. In a further modification the strobe waveform may be extended by a pulse of the opposite polarity to the polarity of the trailing portion of the conventional strobe waveform, as shown in Figure 5d. This can be used to increase the contrast ratio due to the effect of the opposite polarity pulse which drives the director of the nonselect pixels back towards the unlatched state. These modifications are described in more detail in Jones et al. (ibid.).

The case in which the strobe waveform is extended into the following line to give faster line-address-times, in a similar way to the Malvern addressing scheme of Hughes and Raynes (as described in Liquid Crystals, 1993 Vol 13 No. 4,597-601 and British Patent No. 2262831), is also shown in Figure 6 which indicates typical blanking and strobe waveforms applied to a row electrode, and typical data waveforms applied to the column electrodes such that the strobe waveform extends into the following line. The resultant waveforms applied to the pixels are shown, together with the corresponding light transmission from the pixels. As shown in British Patent Application No.

9718369.3-DIS/IR/T1/36/39, an increased or increasing level is preferable. As previously indicated, the strobe waveform may also be extended into the previous line to achieve a faster line-address time. In this case, it is better to ensure that the applied strobe in the slots before the line-address period is close to the optimum strobe voltage, so that the same torque is applied for either data type.

Recently it has been realised that the switching torque acting on the director varies as the director reorients, due to the differing contributions from the ferroelectric and dielectric terms. This knowledge has been exploited in the DRAMA addressing scheme (British Patent Publication No. 9716164.0, US Patent Application No. 08/894507), the MASSIVE addressing scheme (European Patent Application No. 98306632.5 DIS/IRYTI/36/39) and in the addressing scheme of European Patent Publication No.

0809232-DIS/IR/T1/3 which provide novel strobe and data waveforms to optimise the performance of the addressing scheme. In each of these addressing schemes the select resultant waveform S is designed to follow a maximum torque curve as shown in the plot of voltage against the director orientation in Figure 7 (see J. C. Jones and C. V.

Brown, Proceedings of the International Displays Research Conference, 1995, Birmingham UK), whilst the non-select resultant waveform NS has as low a switching torque as possible within the constraints of optimizing the waveforms (to provide DC balancing, ensuring the same Vrms occurs on both S and NS data types, etc). This is a difficult task, since the strobe waveform is applied to both the pixels to be switched and the pixels not to be switched, and the only difference seen by the two sets of pixels is due to the different select and non-select data waveforms. Using high data voltages may increase the degree of discrimination, but this has considerable disadvantages in practical devices due to the increased power, lower contrast ratio and increased nonuniformities over the area of the device.

There is a particular limitation common to the prior art monopulse addressing schemes which is that the magnitude of the first slot of the select resultant waveform S is small (typically +Vd) and usually much lower than the optimum level. Figure 7 shows the theoretical prediction of the voltage which leads to a maximum switching torque calculated for a liquid crystal material with properties similar to those of the commercial ferroelectric liquid crystal material SCE8. It is assumed throughout this description that the liquid crystal material is in a configuration such that a positive voltage acts in the direction to cause switching into the opposite state. Also shown in Figure 7 is the locus of higher voltages at and above which the switching torque is zero as the dielectric torques completely overcome the ferroelectric switching torque. It is important to emphasise that this locus was calculated assuming the maximum torque was applied for all times immediately before a particular point on the minimum torque curve is plotted. Practically, if a voltage higher than the left hand intercept is applied at the beginning of the non-select resultant waveform, for example, then no movement of the director occurs and no switching occurs if the voltage is maintained at or above this level for the remainder of the non-select resultant waveform.

The addressing schemes in accordance with the invention to be described below remove this limitation and allow the first slot of the select resultant waveform S to approach the optimum switching torque whilst at the same time leading to a non-select resultant waveform NS in which a much lower torque occurs in this first slot. Moreover, these addressing schemes achieve these advantages with approximately half the data voltage magnitudes, thereby giving the desired fast operation with a wide operating range with much lower power consumption and higher contrast ratio.

By way of example, a basic two-slot addressing scheme in accordance with the invention will now be described with reference to Figure 9. In this case the strobe waveform has the same magnitude +Vs, and the same polarity, in both slots. The amplitude Vs is chosen to be above that required for the maximum torque at the beginning of the switching process. For a data waveform in which the polarity of the first slot is the same as that of the strobe first slot the resultant waveform voltage is therefore lowered. If Vs and Vd are chosen correctly, the resultant voltage level will be closer to that required for maximum torque at the beginning of switching, and the data waveform behaves as a select waveform. A data waveform with the opposite polarity in the first slot, however, produces a higher resultant waveform voltage, thereby increasing the dielectric effect and reducing the torque applied in the first slot. In this case the data waveform acts as a non-select waveform. Although operating above and about the measured TV minimum, the select and non-select data waveforms (+Vd,-Vd) and (-Vd, +Vd) used in this example are the same as are used in the prior art addressing scheme of Figure 4 operating in the normal mode. However, in this case, the resultant waveforms S and NS are in the form (+Vs-Vd, +Vs+Vd) and (+Vs+Vd, +Vs-Vd).

This type of addressing scheme gives improved performance over the prior art addressing scheme of Figure 5a for the duration of the first slot. Figure 7 suggests that, for the first half of the switching process, the voltage for maximum torque is roughly 50% of the measured pulse voltage minimum (Vmin) whereas, during this first period, a voltage of Vmin would provide a low, approximately zero switching torque. A typical value of Vmin is 30V, and data voltages of between 5V and 8V are practical. In such a case, a strobe first slot of 3/4Vmin 22.5 and data pulse of magnitude Vd ; l/4Vmin = 7.5V leads to a select resultant voltage in the first slot for maximum torque of Vs-Vd = 15V and a non-select resultant voltage in the first slot for zero torque of Vs+Vd = 30V.

Therefore the first slot in this addressing scheme gives similar discrimination to the JOERS/Alvey addressing scheme but faster latching (or alternatively may be chosen to operate at half the voltage for the same speed).

In practice, two factors reduce the efficacy of the addressing scheme shown in Figure 9. These factors will be described with reference to the suggested addressing schemes in accordance with the invention remedying these defects and shown in Figures 10, lIa and llb. Firstly, although the first slot gives excellent speed and discrimination, the second slot of the addressing scheme of Figure 9 tends to reduce the efficacy of the non-select resultant waveform in which the voltage Vs-Vd gives a substantial switching torque and hence reduces the operating range. This effect may be reduced by changing the voltage of the second slot of the applied strobe waveform by a, preferably by increasing the voltage by +a as shown in Figure 10. In this case, the voltage of the second slot of the select data waveform for maximum torque is increased dramatically (to approximately 3/2Vmin from Figure 7) as compared with the example of Figure 9. Thus, if os is about 2Vd (~ i/2Vmin), the voltage of the second slot of the select resultant waveform S will again be close to the maximum torque requirement Vs+a+Vd = (3/4+l/2+'/4) Vmin = 3/2Vmin, and hence fast operation is again assured. The voltage of the second slot of the non-select resultant waveform NS is lower than this, that is Vs+a-Vd = (3/4+l/2-l/4) Vmin = Vmin. This then gives excellent discrimination because the director remained unswitched in the first slot so that the high voltage, for which the torque is zero, remains about Vmin (the voltage being applied in this example). Results for the commercial FLC material SCE8 operating at 25 C are shown in Figure 12a.

Despite these excellent characteristics, there is a second factor which must be improved, and that is the pixel pattern dependence associated with the data waveforms from the line immediately before the line being addressed, since the performance of the device must be substantially independent of the particular form of the image being displayed. For the design of a practical device the worst case pixel pattern must be considered in order to ensure pixel pattern independence at all times in operation of the device. The data from the previous addressed line causes oscillations of the director at the pixels being addressed, observed as changes of transmission and a decrease in contrast, as shown in the transmission profile of Figure 6. The data pulse immediately before the line address time associated with the strobe pulse has particular relevance.

This data slot may act as a pre-pulse in a similar fashion to the first slot of the strobe for the monopolar addressing scheme of Figure 5a or 5b. However, in this situation it cannot be guaranteed that a pulse tending to speed the response will precede the select resultant, rather than a pulse tending to slow the response preceding the non-select resultant. The present scheme is particularly sensitive to this pixel pattern dependence because the switching torque and optimum voltage depend on the director orientation at the beginning of the switching process. A particularly successful method of reducing the pixel pattern dependence is to ensure that the last slot of the data waveform is zero.

Examples of such data waveforms are provided in the DRAMA addressing schemes of British Patent Application No. 9526270.5, including the three-slot scheme (+/-Vd, -/+Vd, 0), and four-slot schemes (+/-Vd,-/+Vd, 0,0), (+/-2Vd,-/+Vd, +/-Vd, 0) and (+/-2Vd,-/+3d. +/-Vd, 0).

Figures 1 la and llb show three-slot examples of addressing schemes in accordance with the invention which use this type of data waveform. In the example of Figure 1 la the strobe waveform is of the form (+Vs, +Vs+a, +Vs+ > . Furthermore the select and non-select data waveforms are of the form (+Vd,-Vd, 0) and (-Vd, +Vd, 0) so that the same voltage appears at the end of the line-address period for both the select and non-select waveforms. Hence, it is advantageous to increase the voltage of the strobe waveform in these slots to ensure that the select resultant waveform S gives a high torque, whilst the voltage in the non-select resultant waveform (much less advanced in the switching process) is above the high zero torque value. This voltage is represented by the additional voltage p in Figure 11 a, and similar increases may be made in all of the later slots of a strobe waveform having a greater number of time slots.

In the example of Figure 1 la this gives select and non-select resultant waveforms of the form (+Vs-Vd, +Vs+a+Vd, +Vs+p) and (+Vs+Vd, +Vs+a-Vd, +Vs+p).

However the shape of the optimum torque curve requires careful design of strobe waveforms having three or more slots. For example, with a four-slot scheme, better operating characteristics may result by ensuring that a is negative (that is that the strobe voltage is lower in the second slot than in the first slot) and providing a strobe waveform of the form (+2Vd,-3Vd, +Vd, 0) or (-2Vd, +3Vd,-Vd, 0). This is because the optimum torque curves are relatively flat at the start of the line-address period such that a positive a leads to the unwanted effects of switching for the non-select resultant whilst the torque for the select resultant is low. Figure lb shows a three-slot addressing scheme having a strobe waveform (+Vs, +Vs-a, +Vs+ (3) and producing select and nonselect resultant waveforms (+Vs-Vd, +Vs-a+Vd, +Vs+p) and (+Vs+Vd, +Vs-a-Vd, +Vs+p). In a further, non-illustrated addressing scheme in accordance with the invention the strobe waveform is such that the polarity of the voltage in the last time slot is opposite to the polarity of the voltage in the first time slot.

Figures 12a, 12b and 12c illustrate operating windows for a 1. Sym cell filled with the commercial FLC material SCE8 and aligned in the C2U state using the polyimide PI-32 and addressed by addressing schemes in accordance with the invention. Figure 12a shows the results obtained for different pixel patterns PP1, PP2, PP3 and PP4 with a three-slot addressing scheme having a strobe waveform (Vs, Vs, Vs) and data waveforms (+Vd,-Vd, 0) and (-Vd, +Vd, 0). The pixel patterns PP1, PP2, PP3 and PP4 correspond respectively to the addressed states of the pixels in three adjacent addressed lines (SS, S/NS, SS), (OS, S/NS, OS), (OS, S/NS, SS) and (SS, S/NS, OS) where S/NS denotes the state of a pixel addressed by the select/non-select resultant waveform and SS denotes the state of a pixel addressed by a data waveform of the same state as this resultant whereas OS denotes the state of a pixel addressed by a data waveform of the opposite state. For each pixel pattern the fastest line-address-time (f. l. a. t.) and slowest line-address-time (s. l. a. t.) producing switching have been plotted. Figure 12b shows the results obtained with a three-slot addressing scheme in which the strobe voltage is lower in the second slot and higher in the third slot of the strobe waveform and is of the form (+0.603Vd, +0.286Vd, +Vd). Figure 12c shows the results obtained using a four-slot addressing scheme having a strobe waveform (+0. 5625Vd, +0.25Vd, +0.4375Vd, +Vd) and data waveforms (+Vd,-0.666Vd, +0.333Vd,-0.666Vd) and (-Vd, +0.666Vd, -0.333Vd, +0.666Vd).

Comparing the results obtained with the prior art DRAMA addressing scheme a three-slot strobe waveform (0, Vs, Vs) and data waveforms (+Vd,-V using d, 0) and (-Vd, +Vd, 0) shown in Figure 8b with the results obtained for the same cell but addressed using an addressing scheme in accordance with the invention using a threeslot strobe waveform (+0.603Vs, +0.286Vs, +Vs) and data waveforms (+Vd,-Vd, 0) and (-Vd, +Vd, 0) shown in Figure 12b indicates that the former scheme has a fastest line-address-time of about 70zs for Vs z 22V (an average strobe voltage across the three slots of 14.7V) compared to a fastest line-address-time of about 50ps for the addressing scheme of this invention at 33V (an average strobe voltage across the three slots of 21V). Figure 8a shows corresponding results for the prior art JOERS/Alvey addressing scheme of Figure 5a indicating that an even longer fastest line-address-time is obtained with such a scheme.

Figure 13 illustrates a step in the design process for an addressing scheme in accordance with the invention in which the pulse width for switching is plotted as a function of the first slot amplitude in a two-slot addressing scheme, where the second slot has a fixed voltage of 30V, showing clearly that the first slot gives fastest switching when close to the optimum value of 15V.

It should be understood that a number of variations of the above described addressing schemes in accordance with the invention are possible within the scope of the invention. For example each such addressing scheme may be combined with a blanking waveform generator, such as is shown in Figure 1, for application of a blanking pulse to blank all the pixels along a row to the same state irrespective of the data waveform applied to the column electrode tracks in advance of the strobe waveform being applied to the row. A typical blanking pulse is shown in Figure 6.

Altematively each frame may be divided into fields in which blanking pulses are supplied in order to blank the pixels alternately into each of the two states, that is the black state and the white state, irrespective of the data waveform applied, in advance of application of the strobe pulse. Furthermore various arrangements may be provided for adjusting the strobe waveform and/or the data waveform so as to vary the resultant waveform in dependence on a particular sensed parameter in at least part of the device, for example the sensed temperature or variations in voltage or alignment within the device. Furthermore variants are possible in which the strobe waveform is extended into the following line or alternatively into the previous line to achieve a faster lineaddress-time, as already described above with reference to Figures 5c, 5d and 6. Other possible variants will be appreciated by referring to Jones et al. (ibid.) and the disclosure of European Patent Publication No. 0809232 which also gives details of a possible drive circuit which may be used for producing the required strobe and data signals.

Claims (20)

1. CLAIMS: 1. A matrix array bistable device comprising an addressable matrix of elements switchable between first and second states, first and second sets of electrodes crossing one another at the locations of the elements, data drive means for applying data signals to the first set of electrodes, each data signal including first and second time intervals within a discriminating period and being of one of two types, that is either a select data signal or a non-select data signal, and strobe drive means for applying strobe signals to the electrodes of the second set of electrodes in succession so as to switch those elements to which the select data signals are applied from the first state to the second state under the effect of the resultant of the data and strobe signals applied to said elements during the discriminating period and so as not to switch those elements to which the non-select data signals are applied, characterised in that each strobe signal comprises first and second time intervals within the discriminating period in which the voltage is non-zero and the polarity of the voltage is the same, and the voltage in the first time interval of each strobe signal and the voltage in the first time interval of each data signal are selected such that the resultant of the select data signal and the strobe signal in the first time interval is of a lower voltage than, and produces a greater switching torque than, the resultant of the non-select data signal and the strobe signal in the first time interval.
2. 2. A device according to claim 1, wherein the first and second time intervals of each strobe signal are of equal duration.
3. 3. A device according to claim 1 or 2, wherein each data signal comprises at least three time intervals within the discriminating period, the polarity of the voltage in the first time interval of the strobe signal being opposite to the polarity of the voltage in the second time interval, and the magnitude and polarity of the voltage in a last time interval of the data signal being the same for the select data signal and the non-select data signal.
4. 4. A device according to claim 3, wherein the magnitude of the voltage is the same in the first and second time intervals of each data signal, and the voltage in the last time interval of the data signal is substantially zero.
5. 5. A device according to claim 1,2,3 or 4, wherein the voltage in the second time interval of each strobe signal is greater than the voltage in the first time interval of the strobe signal.
6. 6. A device according to any preceding claim, wherein each strobe signal comprises at least three time intervals, the voltage in a last time interval of the strobe signal being greater than the voltage in the first and second time intervals of the strobe signal.
7. 7. A device according to claim 6, wherein the last time interval of each strobe signal is applied after the discriminating period.
8. 8. A device according to claim 7, wherein the polarity of the voltage in the last time interval of each strobe signal is opposite to the polarity of the voltage in the first time interval of the strobe signal within the discriminating period.
9. 9. A device according to claim 6,7 or 8, wherein each strobe signal includes an initial time interval which is applied before the discriminating period.
10. 10. A device according to claim 9, wherein the voltage in the initial time interval of each strobe signal is such that the switching torque produced is approximately the same whether the select data signal or the non-select data signal is applied.
11. 11. A device according to any preceding claim, wherein adjustment means are provided for varying the resultant in dependence on the sensed temperature of at least a part of the device.
12. 12. A device according to any preceding claim, wherein adjustment means are provided for varying the resultant to compensate for variations in voltage within the device.
13. 13. A device according to any preceding claim, wherein adjustment means are provided for varying the resultant to compensate for variations in alignment within the device.
14. 14. A device according to any one of claims 1 to 13, wherein blanking means are provided for applying blanking signals to the electrodes of the second set of electrodes in advance of the strobe signals so as to set all the addressed elements to the same state irrespective of the type of data signal applied.
15. 15. A device according to any one of claims 1 to 13, wherein the strobe drive means is arranged to apply strobe signals to the electrodes of the second set of electrodes such as to alternate the selectivity between the first and second states irrespective of the type of data signal supplied.
16. 16. A device according to any preceding claim, wherein the addressable matrix of elements is provided in a layer of ferroelectric liquid crystal material.
17. 17. A device according to claim 16, wherein the voltage in the first time interval of each strobe signal and the voltage in the first time interval of each data signal are selected such that the resultant of the data signal and the strobe signal in the first time interval produces a dielectric torque that exceeds the ferroelectric torque in the liquid crystal material.
18. 18. A drive circuit for a matrix array bistable device comprising an addressable matrix of elements switchable between first and second states and first and second sets of electrodes crossing one another at the locations of the elements, the circuit comprising data drive means for applying data signals to the first set of electrodes, each data signal including first and second time intervals within a discriminating period and being of one of two types, that is either a select data signal or a non-select data signal, and strobe drive means for applying strobe signals to the electrodes of the second set of electrodes in succession so as to switch those elements to which the select data signals are applied from the first state to the second state under the effect of the resultant of the data and strobe signals applied to said elements during the discriminating period and so as not to switch those elements to which the non-select data signals are applied, characterised in that each strobe signal comprises first and second time intervals within the discriminating period in which the voltage is non-zero and the polarity of the voltage is the same, and the voltage in the first time interval of each strobe signal and the voltage in the first time interval of each data signal are selected such that the resultant of the select data signal and the strobe signal in the first time interval is of a lower voltage than, and produces a greater switching torque than, the resultant of the non-select data signal and the strobe signal in the first time interval.
19. 19. A ferroelectric liquid crystal device substantially as hereinbefore described with reference to Figures 1, 2 and 9 to 13 of the accompanying drawings.
20. 20. A drive circuit for a ferroelectric liquid crystal device substantially as hereinbefore described with reference to Figures 1,2 and 9 to 13 of the accompanying drawings.

    20. A drive circuit for a ferroelectric liquid crystal device substantially as hereinbefore described with reference to Figures 1,2 and 9 to 13 of the accompanying drawings.

    Amendments to the claims have been filed as follows CLAIMS: 1. A matrix array bistable device comprising an addressable matrix of elements switchable between first and second states, first and second sets of electrodes crossing one another at the locations of the elements, data drive means for applying data signals to the first set of electrodes, each data signal including a first time interval at the beginning of a discriminating period and a second time interval immediately following the first time interval within the discriminating period, and the data signals being of one of two types, that is either a select data signal or a non-select data signal, and strobe drive means for applying strobe signals to the electrodes of the second set of electrodes in succession so as to switch those elements to which the select data signals are applied from the first state to the second state under the effect of the resultant of the data and strobe signals applied to said elements during the discriminating period and so as not to switch those elements to which the non-select data signals are applied, characterised in that each strobe signal comprises first and second time intervals, corresponding to the first and second time intervals of the data signals, within the discriminating period in which the voltage is non-zero and the polarity of the voltage is the same for both time intervals, and the voltage in the first time interval of each strobe signal and the voltage in the first time interval of each data signal are selected such that the resultant of the select data signal and the strobe signal in the first time interval is of the same polarity as but lesser voltage magnitude than, and produces a greater switching torque than, the resultant of the non-select data signal and the strobe signal in the first time interval.

    2. A device according to claim 1, wherein the first and second time intervals of each strobe signal are of equal duration.

    3. A device according to claim 1 or 2, wherein each data signal comprises at least three time intervals within the discriminating period, the polarity of the voltage in the first time interval of the data signal being opposite to the polarity of the voltage in the second time interval, and the magnitude and polarity of the voltage in a last time interval of the data signal being the same for the select data signal and the non-select data signal. 4. A device according to claim 3, wherein the magnitude of the voltage is the same in the first and second time intervals of each data signal, and the voltage in the last time interval of the data signal is substantially zero.

    5. A device according to claim 1,2,3 or 4, wherein the voltage in the second time interval of each strobe signal is of greater magnitude than the voltage in the first time interval of the strobe signal.

    6. A device according to any preceding claim, wherein each strobe signal comprises at least three time intervals, the voltage in a last time interval of the strobe signal being of greater magnitude than the voltage in the first and second time intervals of the strobe signal.

    7. A device according to claim 6, wherein the last time interval of each strobe signal is applied after the discriminating period.

    8. A device according to claim 7, wherein the polarity of the voltage in the last time interval of each strobe signal is opposite to the polarity of the voltage in the first time interval of the strobe signal within the discriminating period.

    9. A device according to claim 6,7 or 8, wherein each strobe signal includes an initial time interval which is applied before the discriminating period.

    10. A device according to claim 9, wherein the voltage in the initial time interval of each strobe signal is such that the switching torque produced is approximately the same whether the select data signal or the non-select data signal is applied.

    11. A device according to any preceding claim, wherein adjustment means are provided for varying the resultant in dependence on the sensed temperature of at least a part of the device.

    12. A device according to any preceding claim, wherein adjustment means are provided for varying the resultant to compensate for variations in voltage within the device.

    13. A device according to any preceding claim, wherein adjustment means are provided for varying the resultant to compensate for variations in alignment within the device.

    14. A device according to any one of claims 1 to 13, wherein blanking means are provided for applying blanking signals to the electrodes of the second set of electrodes in advance of the strobe signals so as to set all the addressed elements to the same state irrespective of the type of data signal applied.

    15. A device according to any one of claims 1 to 13, wherein the strobe drive means is arranged to apply strobe signals to the electrodes of the second set of electrodes such as to alternate the selectivity between the first and second states irrespective of the type of data signal supplied.

    16. A device according to any preceding claim, wherein the addressable matrix of elements is provided in a layer of ferroelectric liquid crystal material.

    17. A device according to claim 16, wherein the voltage in the first time interval of each strobe signal and the voltage in the first time interval of each data signal are selected such that the resultant of the data signal and the strobe signal in the first time interval produces a dielectric torque that exceeds the ferroelectric torque in the liquid crystal material.

    18. A drive circuit for a matrix array bistable device comprising an addressable matrix of elements switchable between first and second states and first and second sets of electrodes crossing one another at the locations of the elements, the circuit comprising data drive means for applying data signals to the first set of electrodes, each data signal including a first time interval at the beginning of a discriminating period and a second time interval immediately following the first time interval within the discriminating period, and the data signals being of one of two types, that is either a select data signal or a non-select data signal, and strobe drive means for applying strobe signals to the electrodes of the second set of electrodes in succession so as to switch those elements to which the select data signals are applied from the first state to the second state under the effect of the resultant of the data and strobe signals applied to said elements during the discriminating period and so as not to switch those elements to which the non-select data signals are applied, characterised in that each strobe signal comprises first and second time intervals, corresponding to the first and second time intervals of the data signals, within the discriminating period in which the voltage is non-zero and the polarity of the voltage is the same for both time intervals, and the voltage in the first time interval of each strobe signal and the voltage in the first time interval of each data signal are selected such that the resultant of the select data signal and the strobe signal in the first time interval is of the same polarity as but lesser voltage magnitude than, and produces a greater switching torque than, the resultant of the non-select data signal and the strobe signal in the first time interval.

    19. A ferroelectric liquid crystal device substantially as hereinbefore described with reference to Figures 1,2 and 9 to 13 of the accompanying drawings.