GB2346233B - Address aggregation system and method for increasing throughput of addresses to a data cache from a processor - Google Patents

Address aggregation system and method for increasing throughput of addresses to a data cache from a processor

Info

Publication number
GB2346233B
GB2346233B GB0009600A GB0009600A GB2346233B GB 2346233 B GB2346233 B GB 2346233B GB 0009600 A GB0009600 A GB 0009600A GB 0009600 A GB0009600 A GB 0009600A GB 2346233 B GB2346233 B GB 2346233B
Authority
GB
United Kingdom
Prior art keywords
addresses
processor
data cache
aggregation system
increasing throughput
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB0009600A
Other versions
GB0009600D0 (en
GB2346233A (en
Inventor
Gregg Lesartre
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/609,821 external-priority patent/US5761713A/en
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of GB0009600D0 publication Critical patent/GB0009600D0/en
Publication of GB2346233A publication Critical patent/GB2346233A/en
Application granted granted Critical
Publication of GB2346233B publication Critical patent/GB2346233B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0851—Cache with interleaved addressing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
GB0009600A 1996-03-01 1997-02-07 Address aggregation system and method for increasing throughput of addresses to a data cache from a processor Expired - Fee Related GB2346233B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/609,821 US5761713A (en) 1996-03-01 1996-03-01 Address aggregation system and method for increasing throughput to a multi-banked data cache from a processor by concurrently forwarding an address to each bank
GB9702534A GB2310741B (en) 1996-03-01 1997-02-07 Address aggregation system and method for increasing throughput of addresses to a data cache from a processor

Publications (3)

Publication Number Publication Date
GB0009600D0 GB0009600D0 (en) 2000-06-07
GB2346233A GB2346233A (en) 2000-08-02
GB2346233B true GB2346233B (en) 2000-09-20

Family

ID=26310949

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0009600A Expired - Fee Related GB2346233B (en) 1996-03-01 1997-02-07 Address aggregation system and method for increasing throughput of addresses to a data cache from a processor

Country Status (1)

Country Link
GB (1) GB2346233B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6839797B2 (en) 2001-12-21 2005-01-04 Agere Systems, Inc. Multi-bank scheduling to improve performance on tree accesses in a DRAM based random access memory subsystem

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4381541A (en) * 1980-08-28 1983-04-26 Sperry Corporation Buffer memory referencing system for two data words

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4381541A (en) * 1980-08-28 1983-04-26 Sperry Corporation Buffer memory referencing system for two data words

Also Published As

Publication number Publication date
GB0009600D0 (en) 2000-06-07
GB2346233A (en) 2000-08-02

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20100207