GB2344950A

GB2344950A - Encryption of video signals for use with ITU/R Recommendation 656 interfaces

Info

Publication number: GB2344950A
Application number: GB9827612A
Authority: GB
Inventors: Paul Gordon Robertson
Original assignee: Snell and Wilcox Ltd
Current assignee: Snell Advanced Media Ltd
Priority date: 1998-12-15
Filing date: 1998-12-15
Publication date: 2000-06-21
Anticipated expiration: 2018-12-15
Also published as: WO2000036838A2; AU1789800A; GB9827612D0; GB2344950B; EP1142335A2; WO2000036838A3

Abstract

The invention is concerned with preventing unauthorise copying when using a digital interface according to ITU/R Recomendation 656. To inhibit unauthorised copying, the standard timing reference signals in a Rec 656 digital video signal are stripped out and replaced by a single timing reference per frame. Authorised equipment contains the processing to reconstruct the necessary timing from these timing references. Additionally, the digital words can be scrambled by bit re-ordering.

Description

2344950 Encryption of Didtal Video

This invention concerns digital outputs from devices for playing prerecorded digital video media such as Digital Versatile Disks (DVI:)). Suppliers of video programme materbil am conccrncd to avoid the creation of unauthorised "pkate' copies by connecting the output of a player to a recorder. There are known methods of modifying an analogue video signal to make it unsuitable for recording without affecting the ability of a display device to show the picture; an example is the "Maaovision" system which modifies the field synchronising signals amongst other things. However, the advent of digital technology has made it possible to create copies which are undistorted replicas of the original programme. For this reason suppliers of digital consumer equipment are often contra=ally required not to

0 provide digital outputs which are capable of being recorded by unauthorised persons.

Professional video equipment almost invariably uses the digital interfaces defined by the ITUIR in their Recommendation 656. Tlese interfaces handle uincorTressed digital component (i.e. luminance and colour difference) signals and integrated 0 circuits which support the bit-serial version are readily available. There are thus many advantages to the use of Rec. 656 interfaces in consumer equiprnent; however, such use could contravene contractual requirements relating to the provision of recordable #p digital outputs.

95- The inventor has appreciated that the parallel and serial digital component interfbLces defined in ITUIR Recommendation 656 can be modified to prevent unauthorised use of the digital signal by sending the timing reference signals (TRSs) infrequently, typically once per frame, and by omitting some or all of the blanking and field phase information from the TRSs. Suitably the TRS can be placed otber than at the sLart or finish of a digital active Enc.

In a flirther aspect of the invention the transmitted TRSs include additional information about the video, such as its line standard or aspect ratio, or data to confirm the validity of the signal.

Advantageously the order of the bits in the digital words is rearranged. either in a fixed pattern or in a changing pattern synchronised by the transmitted timing reference signals.

In a normal digital component signal in accordance with ITUIR Rec. 656 the, TRSs arc sent twice per line, and they enable a receiving device, such as a recorder, to identify the order of the words in the =hiplex of luminance and colour difference words, and, in the case of the bit-serial interface. they enable the boundaries of the data words to be identified. As well as marking the start ard rmish of each line the TRSs identify the start and end of each field and frame.

Existing digital equipment relies for its proper operation on the presence of TRSs at the start and finish of each digital active line and will fail to operate if they are absent. However, if the line standard of theTsignal is known, the timing reference signals can be regenerated from the data clock if the position within the frame of one clock pulw is known. Provided a continuous clock signal is present. a single start- or end-of-field

2 TRS enables all the information normally carried by the reguUm TRSs to be regenerated.

An example of the invention will now be described with reference to the drawings in which:

Figure I shows the block diagram of a video encryption system figure 2 shows the block diAgram of a videb decryption device Referring to Figure 1, a digital video source (1) outputs a parallel (8 bits and clock) signal having the format defined in ITU/R Rec. 656. This signal feects a digital sync separator (2) and a TRS remover (3). The separator recog nises the TRSs in the input signal and decodes the following signals from them: digital line bLmk-ing (H), digital 49P field blanking (V) and field phase (F). The TRS remover replaces the TRSs by data corresponding to blanking levels.

The video data without TRSs goes to a rnodified TRS inserter (4) which inserts a modified TRS once per frame at a fixed point in the video blanking. The modified TRS consists of four data words followed by a funheT four validation words as follows (in bexadecirrial notation):

FF 00 00 IJ VIIV12 V21V22 The validation words are fixed and identify the method of encryption. The IJ word has its four most significant bits as shown in the table below and the four least significant bits are error detection bits defined in the same way as in the XY word of the TRS described in Rec. 656.

Bit Value 7. 1 6 0 0 for 16:9 aspect ratio 1 for 4:3 aspect ratio 4 1 for 625 lines 0 for 525 Lines The output of the inserter drives a bit rearranger (5) which chauges the order of the bits in the word in a changing pattern synchronised by the field phase signal. The resulting signal can be output directly as an encrypted parallel signal (6) or passed to a standard Rec. 656 Serialiser (7), which converts the parallel data into a bit-serial stream exactly as described in Rec. 656, to provide an encrypted serial signal (8).

Figure 2 shows a video decryption device. An encrypted scrial digital sigral (8) is fed to a standard Rec. 656 deserialiser (21) to provide a parallel data and clock signal to a bit order rearranger (22). Alternatively, if a parallel encrypted signal (6) is already available, it can be fed directly to the rearranger (22).

The output of the rearranger feeds a TRS detector and decoder (24). The TRS is detected in the conventional manner from its FF and 00 words, which are unaffected by the bit reordering.

The TRS detector outputs a synchronising pulse (23) when a valid TRS is detected. The line standard and aspect ratio are also decoded from the relevant bits of the TRS.

The synchronising pulse synchronises a sync pulse generator (25), which is set to the appropriate line standard by the decoded line standard infonnation and driven from the word-rate clock to generate F. V and H signals which am correctly timed to the video data.

The bit-order rearnanger (22) estorcs the correct older of the bits by the reverse of the process (5) in the encrypter. 71c changing pattern of bit order changes is synchronised 0 by the synchronising pulse (23), which occurs at a fixed position relative to the start of cach. The resulting parallel digital video signal drives a TR.S inserter (26) which inserts standard Rec. 656 TRS.s inresponse to the F, V and H signals from the SPO (25). The resulting decrypted parallel signal can be output directly for use (27), or serialised fin accordance with Rec. 656 in Serialiser (28). It should be noted that the TRS insúTtion is only neces-sary if a "standard" signal is required for subsequent processing. In most applications only the output video data from the TRS detector (24) and the F, V and H signals from the sync pulseg, enerator (25) will be required.

The above descTiption ba. been hased on eight-bit processing but the skilled man will appreciate that Rec. 656 explains how ten-bit signals are carried by the serial and parallel interfaces and that these methods are directly applicable to the subject matter of the invention.

It must be recognised that the invention has been described only by way of example and nmny variations are possible within the concepts described. Por example the contents and frequency of transmission of the TRSs could differ from that described here.

4 1. A digital video interface substantially in accordance with ITUIR Recommendation 0 656 charactcriscd in that timing reference signals are transmitted less than twice per line in order to prevent unauthorised use of the video information.

Claims

A digital video interface as described in Claim 1 where any timing

refereince signal does not correspond to the start or finish of a digital active line.

C A digital video interface in accordance with either Claim 1 or Clairn2 in which 0 the fourth word of any TRS does not contain F, V and H information in accordance with Rec. 656.

4. A digital video interface in accordance with either Claim 1 or Claim 2 in which aspect ratio information is carried in the timing reference signals.

5. A digital video interface in accordance with either Claim 1 or Claim 2 in which line standard information is carried in the timing reference signals.

6. A digital video interface in accordance with either Claim 1 or Claim 2 in which the timing reference signals include data identifying a method of encryption.

C 7. A digital video interface in accordance with any of the preceding claims in which the order of significance of the bits is rearrangcO.

8. A digital video interface in accordance with any of the preceding claims in which the order of signfficance of the bits is rearranged according to a predictable pattern.

9. Video encryption apparatus in accordance with any of the preceding claims 1 - 8.

10. Video decryption apparatus in accordance with any of the preceding claims 1 - 8.