GB2344664A - Debugging data processing systems - Google Patents

Abstract

When a data processing system, having a main processor 4 and a coprocessor 26, is in a debug mode, the instructions supplied to the main processor are different from those supplied to the coprocessor.The coprocessor 26 is supplied with a coprocessor debug data generation instruction (MCR) whilst the main processor 4 is supplied with a main processor data capture instruction (LDR). The coprocessor 26 responds to the MCR instruction by controlling debug data representing state of the data processing apparatus 2 to be placed upon a data bus 24 from where it is read by the main processor 4 under control of the LDR instruction.

Description

DEBUGGING DATA PROCESSING SYSTEMS This invention relates to the field of data processing systems. More particularly, this invention relates to debugging data processing systems.

With the advent of increasingly complex data processing systems, and the requirement for shorter development time, it is becoming increasingly important to provide powerful debugging tools to assist in system development. This is particularly the case in deeply embedded systems in which much of the systems state is normally inaccessible.

One way of dealing with the debugging problem is to provide serial scan chains around portions of the circuits of the system to allow input signals to be scanned in and applied to the circuit and output signals to be captured and scanned out of the circuit. This is the JTAG type of debugging scheme.

A problem with the serial scan chain approach to debugging is that the scan chain cells may need to be placed upon critical signal paths within the system slowing the signal paths and limiting the system performance.

Viewed from one aspect the present invention provides data processing apparatus responsive to a sequence of processor instructions containing main processor instructions and coprocessor instructions, said data processing apparatus comprising: a main processor for executing main processor instructions appearing within said sequence of processor instructions; a coprocessor coupled to said main processor for executing coprocessor instructions appearing within said sequence of processor instructions; and an instruction insertion mechanism operative in a debugging mode for supplying different processor instructions to said main processor and said coprocessor such that said main processor executes a main processor data capture instruction whilst said coprocessor executes a coprocessor debug data generation instruction whereby debug data is generated under control of said coprocessor and said debug data is captured by said main processor.

In a system having both a coprocessor and a main processor, these different elements may be controlled to cooperate while in a debug mode to recover system state information that would otherwise be difficult to obtain without a disadvantageously extensive use of scan chains. More particularly, whilst the same instruction stream is normally fed to both the main processor and the coprocessor, the invention provides that different instructions may be fed to the main processor and the coprocessor in the debug mode with the main processor being responsive to its instruction to capture debug data that is generated under control of the coprocessor in response to a coprocessor instruction executed at the same time (having been triggered to do so by execution of the main processor instruction).

The coprocessor instruction is decoded and interpreted by the coprocessor in the debug mode in a manner chosen by the system designer and is so potentially able to recover any particular items of system state that the system designer decides in advance and for which the circuitry is provided. The capture of the data by the main processor allows it to be subsequently recovered from the main processor via the normal output mechanisms of the system under control of normal main processor instructions.

In preferred embodiments the main processor data capture instruction transfers the debug data into a register of a register bank within the main processor. This data capture mechanism is both rapid and flexible.

The instruction insertion mechanism could take many forms. The mechanisms that feed the standard instructions to the main processor and the coprocessor when not in debug mode could be used to supply one of the main processor and the coprocessor with instructions during this debug mode with the other of the main processor and the coprocessor being supplied from an alternative source by mechanisms only operative in the debug mode. Alternatively, both the main processor and the coprocessor could be provided with special purpose mechanisms for supplying them with instructions during the debug mode. In this case, scan chains for scanning in instructions to the main processor and the coprocessor are preferred.

The state data generated in response to the coprocessor debug data generation instruction could be transferred to the main processor via a special purpose data path.

However, in preferred embodiments the standard data bus that is employed in normal operation may also be employed in debug operation for this purpose.

In order to recover state data from the main processor in the context of a debug operation, a register store scan chain can be provided to capture data being read from a register of the main processor and serially clock that data out from the apparatus.

The above system can be used to recover many types of otherwise inaccessible state data from the data processing system. As an example, it is possible to use this approach to recover data from various peripheral devices if the system designer arranges for the coprocessor debug data generation instructions to be interpreted in that way. However, the invention is particularly well suited to the recovery of data from cache memories and memory management units. In particular, the invention can allow the TAG contents of the CAM and the data contents of the RAM of a cache memory and an MMU to be read relatively rapidly from the system and without impacting the normally critical signal paths between the cache, MMU and main processor by inserting scan chains to capture data values on these paths. The contents of a cache memory or an MMU are often highly significant elements of debug information required during system development.

In high performance systems, the main processor will typically have an instruction pipeline. In this case, the instruction insertion mechanism can comprise a scan chain for inserting an instruction into the fetch stage of this pipeline. In such embodiments the coprocessor typically has a pipeline follower and the coprocessor instructions can similarly be inserted into the fetch stage of this coprocessor pipeline.

In the context of a cache memory or an MMU, the problem of how a particular item of data is to be selected for recovery as debug data may be addressed by using the normal victim select circuitry that in standard operation controls which item is replaced when a new item needs to be inserted in the relevant one of the cache memory or the MMU. In the debug mode this victim selection circuitry can be set up in advance to operate to select a specific desired entry for recovery as the debug data.

Viewed from another aspect the present invention provides a data processing method controlled by a sequence of processor instructions containing main processor instructions and coprocessor instructions, said data processing method comprising the steps of : executing with a main processor main processor instructions appearing within said sequence of processor instructions; executing with a coprocessor coprocessor instructions appearing within said sequence of processor instructions; and in a debugging mode, supplying different processor instructions to said main processor and said coprocessor such that said main processor executes a main processor data capture instruction whilst said coprocessor executes a coprocessor debug data generation instruction whereby debug data is generated under control of said coprocessor and said debug data is captured by said main processor.

An embodiment of the invention will now be described, by way of example only, with reference to the accompanying drawings in which: Figure 1 schematically illustrates a data processing system according to one example embodiment of the present invention; and Figure 2 schematically illustrates the operation of the main processor and the coprocessor during debug operation.

Figure 1 shows a data processing system 2 comprising a main processor 4 and a coprocessor 26. An instruction cache 8 and a data cache 10 are provided for caching instructions and data respectively. A memory management unit may also be provided.

The main processor includes an instruction executer 12 and a register bank 14.

A main processor pipeline 16 is responsive to main processor instructions read from the instruction bus 18 to feed these to the instruction executer 12 for execution. A main processor instruction scan chain 20 is provided on the instruction path for inserting instructions into the instruction pipeline 16 during debug operation. An output scan chain 22 is provided on the data path for capturing data values read out from the register bank 14 onto a data bus 24 during debug operation.

The coprocessor 26 designated as the special purpose coprocessor CP15 is provided for controlling debug operation as well as other system mode and control functions. A coprocessor instruction pipeline 28 is provided within the coprocessor 26 for following the instructions placed on the instruction bus 18 and fed to the main processor 4. When the coprocessor 26 detects a coprocessor instruction having its matching coprocessor number (i. e. 15) at the execute stage of the coprocessor instruction pipeline 28, then the coprocessor instruction decoder 30 responds to this coprocessor instruction in the manner predetermined by the system designer. In the present example, when in a debug mode, the coprocessor 26 can be made responsive to specific coprocessor instructions to control the data cache 10 or the instruction cache 8 to output either the contents of their CAM portion or their RAM portion onto the data bus 24. The respective victim selection circuitry 32,34 can be configured in advance to point to a specific cache line that it is desired to be recovered onto the data bus 24. In a round robin mode of operation of the victim select circuitry a sequence of cache lines can be accessed.

At the same time that the coprocessor 26 is controlling the cache memory 8,10 to place debug data onto the data bus 24, the main processor 4 can be reading that debug data into a register of the register bank 14. Once captured within the register bank 14, the debug data can be stored out in a subsequent processing cycle into the output scan chain 22 from where it can be recovered from the data processing apparatus 2.

The main processor instruction scan chain 20 and a coprocessor instruction scan chain 36 are used to together provide the instruction insertion mechanism. More particularly, an appropriate main processor data capture instruction can be inserted into the main processor pipeline 16 whilst a coprocessor debug data generation instruction can be inserted into the coprocessor instruction pipeline 28. When these respective instructions have advanced along to the execution stage of their pipeline, they will be executed to perform their respective roles. The advance of the main processor instruction to the execute stage triggers a similar advance of the coprocessor instruction such that the main processor instruction and coprocessor instruction are executed at effectively the same time.

It will be appreciated that the main processor pipeline 16 and the coprocessor pipeline 28 normally store the same instructions as they read these from the instruction bus 18 that they share. The present technique breaks this symmetry and causes different instructions to be presented to the coprocessor 26 and the main processor 4 such that they may cooperate together in a highly flexible manner to first trigger generation of the debug data and also the capture of this debug data.

Figure 2 schematically illustrates the different processing operations being performed in the main processor core 4 and the coprocessor 26 at different points in time. The first operations that occur are that the main processor data capture instruction (LDR) is scanned into the main processor instruction scan chain 20 whilst the interpreted mode control bit and the coprocessor debug data generation instruction (MCR) are scanned into the coprocessor instruction scan chain 36. The LDR and MCR instructions then advance in parallel down their respective pipelines 16,28 (with advances in the main processor triggering advances in the coprocessor).

When the MCR and the LDR instructions reach the execute stages at effectively the same time, the MCR instruction is interpreted by the coprocessor 26 to trigger appropriate debug data to be placed upon the data bus 24. The MCR instruction may be interpreted in a different way when not operating in the debug mode. At the same time, the LDR instruction is interpreted by the main processor 4 to read this debug data from the data bus 24 and store it within the register bank 14.

The main processor 14 then continues to execute a store to memory instruction (STR) that writes the contents of the register containing the debug data back onto the data bus 24 from where they are captured into the output scan chain 22 prior to being scanned out.

In the Annex attached hereto an extract of a document describing debug support is given. This extract deals with interpreted access commands in accordance with one example of the present invention.

Further details of debug operations of integrated circuits in the context of which the present invention may be used can be found in the ARM9TDMI Reference Manual (ARM Document DDI 0145A Chapter 5) which was published in November 1998. Further details of boundary scan systems of a type that may be used with the invention are described in IEEE Standard 1149.1-1990 Standard Test Access Port and Boundary Scan Architecture.

ANNEX Debug Support PCLKBS This is the update clock, generated in the UPDATE-DR state.

Typically the value scanned into the chain will be transferred to the cell output on the rising edge of this signal.

ICAPCLKBS. ECAPCLKBS These are the capture clocks used to sample data into the scan cells during INTEST and EXTEST respectively. These clocks are generated in the CAPTURE-DR state.

SHCLK1BS, SHCLK2BS These are non-overlapping clocks generated in the SHIFT-DR state that are used to clock the master and slave element of the scan cells respectively. When the state machine is not in the SHIFT-DR state, both these clocks are LOW. nHIGHZ This signal can be used to drive the outputs of the scan cells to the high impedance state. This signal is driven LOW when the MGHZ instruction is loaded into the instruction register, and HIGH at all other umes.

In addition to these control outputs, SDINBS output and SDOUTBS input are also provided. When an external scan chain is in use. SDOUTBS should be connected to the serial data output and SDINBS should be connected to the serial data input.

8.6.6 Scan chains 4 and 15-the ARM920T memory system On entry to debug state, the debugger should extract and save the state of CP15. It is advisable that the caches and MMUs are then switched off to prevent any debug accesses to memory from altering their state. At this point, the debugger can non invasively determine the state of the memory system. When in debug state, the debugger is able to see the state of the ARNI920T memory system. This includes: CPIS caches MMU PA tag RAM.

Scan chains 15 and 4 are reserved for this use.

Scan chain 15 This scan chain is 40 bits long, shown below in Table 8-7. With scan chain 15 selected, TDI is connected to bit 39 and TDO is connected to bit 0. An access via this scan chain allows all of CP15's registers to be read and written, the cache CAM and RAM to be read and the TLB CAM and RAM to be read. There are two mechanisms for accesses via scan chain 15, outlined below.

Physical access 1. In SHIFT-DR, shift in the read/write bit. register address and register value for writing, shown in Table 8-8.

2. Move through UPDATE-DR. For a write, the register will be updated here.

3. For reading, return to SHIFT-DR through CAPTURE-DR and shift out the register value.

Interpreted access l. A physical access read-modify-write tn C15 (test state) must be done in order to set bit 0, CP15 interpret.

2. The required MCR/MRC instruction word is shifted in to scan chain 15.

3. A system-speed LDR (read) or STR (write) is performed on the ARM9TDMI.

4. CP15 will respond to this LDR/STR by executing the coprocessor instruction in its scan chain.

5. In the case of a LDR, the data will be returned to the ARM9TDMI and can be captured onto scan chain l by performing an STR.

6. In the case of an STR, the interpreted MCR will complete with the data that is issued from the ARM9TDMI.

7. A physical access read-modify-write to C15 (test state) must be done in order to clear CP 15 interpret, bit 0.

Table 8-7 Scan chain 15 format and access modes Interpreted access Physical access Scan chain bit Function Read/Write Function Read > Nrite 39 0 Write nR/W Write 38: 33 000000 Write Register address Write 32: 1 Instruction word Write Register value Read/Write 0 0 Write l Write Debug access to CP15 The mapping of the 6-bit register address field to the CP15 registers for physical access is shown in Table 8-8.

Table 8-8 Physical access mapping to CP15 registers Address Register [38] [37: 34] [33] Number Name Type 0 0x0 0 CO ID register Read 0 0x0 l CO Cache type Read 0 Oxl 0 Cl Control Read/Write 0 0x9 0 C9 Data cache lock-down Read 0 0x9 1 C9 Instruction cache lock-down Read 0 OxD 0 C13 Process ID Read/Write 0 OxF 0 C15. State Test state Read/Write 1 0xD 1 C15. C. I.Ind Instruction cache index Read 1 0xE 1 C15.C.D.Ind Data cache index Read 1 0x1 1 C15. C. I instruction cache ReadNVnte Table 8-8 Physical access mapping to CP15 registers (continued) Address Register I Ox2 I C15. C. D Data cache Read/Write l Ox5 0 C15. M. I Instvction MMU Read t 0x6 0 C15. M. D Data MMU Read The mapping of the 32-bit instruction word field to the remaining CP15 registers for interpreted access is shown in Table 8-9. The construction of a CP15 instruction word from ARM assembler is shown in Figure 2-1 on page 2-3 Table 8-9 Interpreted access mapping to CP15 registers ARM920T Instruction CP15 Instruction Word CP15 Register Write Read Write Read STR Rd, < Address > LDR Rd, < Address > MCR p15.5.r0.c15.c1.2 MRC p15.5.r0.c15.c1.2 I TTB STR rd. < Address > LDR Rd. < Address > MCR p15.5.r0.c15.c2 2 MRC p15.0.r0.c2.c0.0 D TTB STR rd. < Address > LDR Rd. < Address > MCR p15.5.r0.c15.c1.3 MRC p15.5.r0.c15.c1.3 I DAC STR Rd. < Address > LDR Rd. < Address > MCR p15.5.r0.c15. c2.3 MRC p15.0.r0.c3.c0.0 D DAC STR LDRRd. Rd. < Address > MCR pI5. 0. N. c5. eO, O MRC p 5. 0. A. c5. cO. O FSR STR Rd. < Address > LDR Rd. < Address > MCR p15.0.r0.c6.c0.0 MRCp15.0.r0, c6. cO. O FAR STR rd. < Address > N/A MCR p15.0.r0.c9.c1.1 N/A ICache lock-down victum STR RcL < Address > N/A MCR p I 5. 0. rO. c9. cl. O N/A DCache lock-down vicnm STR Rd. < Address > N/A MCR p15.0.r0.c9.c0.1 N/A ICache lock-down base and vicnm STR Rd. < Address > NIA MCR pI5. 0. t9. c9. c0. 0 N/A DCache lock-down base and mcam STRRd. < Address > LDR Rd. < Address > MCR p15.0.r0.c10.c0.1 MRC p15.0.r0.c10.c0.1 I TLB lock-down STR Rd. < Address > LDR Rd. < Address > MCR p15.0.r0.c10.c0.0 MRC p15.0.r0.c10.c0.0 D TLB lock-down Debug access to the MMU This is achieved through scan chain 15. using the interpreted access mechanism. The supported subset of MMU debug operations is shown in Table 8-10. In order to read the instruction or data TLB the followine seauence must be taken : 1. Read-modify-write of Cl to turn off both caches and MMU.

2. Read-modify-write of C15. State to set MMU test and CP15 intecpret.

3. Interpreted LDR. MRC = read C10.

4. STR of value loaded in (3), captured on scan chain 1 and shifted out.

5. Interpreted STR, < address > = victim [=0]. base [=0]. MCR = write C10.

6. Interpreted 8 word LDM. MCR = cAM read.

7.8 word STM of values loaded in (6), captured on scan chain I and shifted out.

8. Repeat (6) and (7) x 8.

9. Interpreted LDR. MCR = RAM1 read.

10. Interpreted LDR. MCR = RAM2 read.

11. 2 word STM of values loaded in (9) and (10). captured on scan chain 1 and shifted out.

12. Repeat (9), (10) and (11) x 64.

13. Interpreted SR < address = victim and base [=value in (4)]. MCR = write c1o.

14. Read-modify-write of C15. State to clear MMU test and CP15 interpret.

15. Write Cl with value read in (1).

Table 8-10 Interpreted access mapping to the MMU ARM920T Instruction Word CP15 Instruction Word MMU Operation LDR Rd. < Address > MCR p15.4.r0.c15,c6, 4 D CAM read or LDMIA Rn, < Rlist > LDR Rd. < address > MCR p15.4.r010. 4 D RAMI read orLDMIA Rn, < R1isc LDRRd. < address > MCRpl5. 4. r0. c15. c2.3 D RAM2 read or LDMIA Rn. < Rlist > Table 8-10 Interpreted access mapping to the MMU (continued) ARM920T Instruction Word CP15 Instruction Word MMU Operation LDR Rd. < Address > MCR p15,4,r0,c15,c5, 4 I CAM read or LDMIA Rn. < Rlist > LDR Rd. < Address > MCR p15,4,r0,c15,c9, 4 [RAMl read or LDMIA Rn, < Rlist > LDR Rd. < Address > MCR p15,4,r0,c15,c1.5 I RAM2 read or LDMIA Rn. < Rlist > Debug access to the caches This is achieved through scan chain 15, using the interpreted access mechanism. The supported subset of cache debug operations is shown in Table 8-11 on page 8-34. In order to read the instruction or data cache the following sequence must be taken: 1. Read-modify-write of Cl to tum both caches and MMU off and set round-robin mode.

2. Read-modify-write of C15. State to set CP15 interpret.

3. Interpreted LDR, < address > = seg. MCR = CAM read.

4. Read-modify-write of C 15. State to clear CP15 interpret.

5. Read C15. C. {I/D}. Ind (victim of current segment).

6. Repeat (2) (5) for each segment.

7. Read-modify-write of C15. State to set CP15 interpret.

8. Interpreted STR, < address > = index [= O], seg. MCR = wrice C9 victim- 9. Interpreted 8 word LDM, < address > = seg, word [= 0]. MCX = RAM read.

10. Interpreted LDR, < address > = seg. MCR = CAM read.

I I. Read-modify-write to C15. State to clear CP15 interpret.

12. 9 word STM of values loaded in (9) and (10), captured on scan chain 1 and shifted out.

14. Repeat (9) # (13) x 64.

15. Repeat (8)- (14) for each segment.

16. Interpreted STR, < address > = index @= value read in (5)], seg.

MCR = write C9 victim.

17. Repeat (16) for each segment.

18. Read-modify-write to C15. State to clear CP15 interpret.

19. Write the value of C I read in (1).

Table 8-11 Interpreted access mapping to the caches ARM920T instruction word Instruction word Cache operation LDR Rd. < address > or LDMIA MCR p15.2.r0.c15. c6.2 D CAM read Rn. < Rlist > LDR Rd. < Address > or LDMIA MCR p15.2.r0.c15.c10. 2 D RAM read Rn. < Rlist > STR Rd. < address > MCR p15.0.r0. c7. c6, 0 D invalidate all STR Rd. < address > MCR p15.0.r0.c7.c6.1 D invalidate single by VA LDR Rd. < address > or LDMIA MCR pl5. 2. r0. c15.c5, 2 I CAM read Rn, < Rlist > LDR Rd, < address > or LDMIA MCR p 15. 2. r0, c 15. c9, 2 [RAM read Rn. < Rlist > STR Rd. < address > MCR p15.0.r0.c7.c5, 0 I in validate all STR Rd. < Address > MCR p15.0.r0.c7.c5,1 I in validate single by VA

Claims (18)

1. CLAIMS 1. Data processing apparatus responsive to a sequence of processor instructions containing main processor instructions and coprocessor instructions, said data processing apparatus comprising: a main processor for executing main processor instructions appearing within said sequence of processor instructions; a coprocessor coupled to said main processor for executing coprocessor instructions appearing within said sequence of processor instructions; and an instruction insertion mechanism operative in a debugging mode for supplying different processor instructions to said main processor and said coprocessor such that said main processor executes a main processor data capture instruction whilst said coprocessor executes a coprocessor debug data generation instruction whereby debug data is generated under control of said coprocessor and said debug data is captured by said main processor.
2. 2. Data processor apparatus as claimed in claim 1, wherein said main processor includes a register bank and said main processor data capture instruction loads said debug data into a register within said register bank.
3. 3. Data processing apparatus as claimed in claim 2, comprising a register store scan chain operative in said debug mode to capture data being read from said register and serially clock said data out of said data processing apparatus.
4. 4. Data processing apparatus as claimed in any one of claims 1, 2 and 3, wherein said coprocessor debug data generation instruction operates in said debug mode to trigger said coprocessor to control transfer of state data onto a data bus coupled to said main processor.
5. 5. Data processing apparatus as claimed in any one of the preceding claims, comprising a cache memory, a coprocessor cache debug data generation instruction triggering said coprocessor to read data contained within said cache memory as said debug data.
6. 6. Data processing apparatus as claimed in claim 5, wherein said cache memory includes a content addressable memory storing cache TAG data, a coprocessor cache TAG debug data generation instruction triggering said coprocessor to read TAG data contained within said content addressable memory as said debug data.
7. 7. Data processing apparatus as claimed in any one of claims 5 and 6, wherein said cache memory includes a cache RAM storing cached data, a coprocessor cache RAM debug data generation instruction triggering said coprocessor to read cached data contained within said content addressable memory as said debug data.
8. 8. Data processing apparatus as claimed in any one of the preceding claims, wherein said coprocessor includes a coprocessor instruction pipeline, said instruction insertion mechanism comprising a coprocessor instruction scan chain operative in said debug mode to serially clock said coprocessor debug data generation instruction into said coprocessor instruction pipeline.
9. 9. Data processing apparatus as claimed in any one of the preceding claims, wherein said main processor includes a main processor instruction pipeline, said instruction insertion mechanism comprising a main processor instruction scan chain operative in said debug mode to serially clock said main processor data capture instruction into said main processor instruction pipeline.
10. 10. Data processing apparatus as claimed in claim 5, wherein said cache memory includes a victim selection circuit, said victim selection circuit serving in said debug mode to select a cache line from which data is read as said debug data.
11. 11. Data processing apparatus as claimed in claim 10, wherein said victim selection circuit may be configured under processing instruction control to select a specific cache line in said debug mode.
12. 12. Data processing apparatus as claimed in claim 11, wherein said victim selection circuit may be configured under processing instruction control to operate in a round robin mode to select cache line in sequence in said debug mode.
13. 13. Data processing apparatus as claimed in any one of the preceding claims, comprising a memory management unit, a coprocessor MMU debug data generation instruction triggering said memory management unit to read access control data contained within said memory management unit as said debug data.
14. 14. Data processing apparatus as claimed in any one of the preceding claims, comprising a plurality of coprocessors, one of said coprocessor being a responsive to said coprocessor debug data generation instruction in said debug mode.
15. 15. Data processing apparatus as claimed in any one of the preceding claims, wherein when not in said debug mode said coprocessor debug data generation instruction has a different function than when in said debug mode.
16. 16. A data processing method controlled by a sequence of processor instructions containing main processor instructions and coprocessor instructions, said data processing method comprising the steps of : executing with a main processor main processor instructions appearing within said sequence of processor instructions; executing with a coprocessor coprocessor instructions appearing within said sequence of processor instructions; and in a debugging mode, supplying different processor instructions to said main processor and said coprocessor such that said main processor executes a main processor data capture instruction whilst said coprocessor executes a coprocessor debug data generation instruction whereby debug data is generated under control of said coprocessor and said debug data is captured by said main processor.
17. 17. Data processing apparatus substantially as hereinbefore described with reference to the accompanying drawings.
18. 18. A data processing method substantially as hereinbefore described with reference to the accompanying drawings.