GB2342761A

GB2342761A - Testing read and write channel processors

Info

Publication number: GB2342761A
Application number: GB9923299A
Authority: GB
Inventors: Alfred Yeung; Tzu Wang Pan
Original assignee: NEC Corp
Current assignee: NEC Corp
Priority date: 1998-10-01
Filing date: 1999-10-01
Publication date: 2000-04-19
Anticipated expiration: 2019-10-01
Also published as: JP2002216301A; GB9923299D0; JP3406978B2; JP3510613B2; JP2000113401A; GB2342761B

Abstract

A built-in self test arrangement used in a system for writing signals to a storage medium such as a magnetic disc, and reading data from the medium, has a variable gain amplifier 431 with a noise generator 432 which amplifies an input read signal. A differentiator 436 models the effects of the storage medium. An output 406 is coupled to the differentiator so that an analog test path including an attenuator 430 is provided between write input 401 and data output 406. A digital test path is also provided, and includes a simulator 412 and noise generator 414.

Description

METHOD AND APPARATUS FOR PROVIDING A TESTING LOOP BETWEEN A WRITE CHANNEL PROCESSOR AND A READ CHANNEL PROCESSOR The present invention relates generally to testing a system for reading and writing data for data storage. More specifically, a system and method is disclosed that includes a test loop back circuit between a write channel processor and a read channel processor that facilitates testing the performance of a reading operation and a writing operation.

Built in self test (BIST) circuits are included on read/write chips for magnetic storage systems to facilitate testing of the read channel processor and the write channel processor included on such chips. Figure I is a block diagram illustrating a write channel processor testing circuit 100. A write channel processor 102 is a processor that transforms input data into a write signal that may be applied to a magnetic storage disk.

When operating normally, write channel processor 102 receives input data and outputs a write signal. In order to test write channel processor 102, test data is generated that the write channel processor may operate on to produce a write signal. A pattern generator 104 is used for this purpose. Pattern generator 104 generates data for write channel processor 102.

In an EPRML system, write channel processor 102 includes an encoder that encodes the input data according to an encoding scheme specified by the EPRML system.

The write channel processor also includes a data scrambler as well as other components described below. In addition to encoding the data, write channel processor 102 also adds synchronization marks to the data for the purpose of facilitating the recovery of a clock signal from the data when the data is read. The signal output from the write channel processor is a high speed signal and so it is usually necessary to include a signature analyzer 106 on chip in order to avoid the need to provide a high speed interface to a tester for functional tests. It would be beneficial if the need to provide such circuitry could be eliminated.

Testing the operation of a read channel processor presents similar difficulties.

Figure 1B is a block diagram illustrating a read channel processor test system 110. A read channel processor 112 normally operates by inputting a read signal obtained from a data channel and outputting a data signal. In order to test read channel processor 110, it is necessary to generate a read signal using a pattern generator 114 that includes the expected characteristics of an actual read signal transmitted by a real data channel.

Pattern generator 114 must operate at a high speed to simulate the high speed obtained from a read data disk. In an EPRML system, for example, the data rate of the signal input to the read channel processor may range from about 150 megabits per second to over 600 megabits per second. The data output rate of the read channel processor in contrast is about 50 megahertz : Pattern generator 114 must include a substantial amount of logic in order to simulate an actual signal input to the read channel processor. Thus, pattern generator 104 is a complex device. A signature analyzer 116 analyzes the data output by read channel processor 112 to determine whether it is correct data given the input data pattern supplie by pattern generator 114.

It would be useful if the complexity of these two test systems could be reduced.

First, it would be desirable if the logic required to generate appropriate patterns for the purpose of testing the read channel processor cou] d be simplified. Also, it would be desirable if the complexity of the signature analyzer required to provide an interface from the write channel output to a tester could be reduced.

A system and method are disclosed for providing a test loop on a chip that includes a read channel processor and a write channel processor. A simple data signal is provided to the write channel processor, which outputs the data to a digital data charinef simulation circuit that simulates the transfer function of a physical data channel. In addition, a digital noise simulator may add noise to the signal. The signal generated by the write channel processor and transformed by the digital physical media simulation circuit is input to the read channel processor. The output of the read channel processor is compared to the test data and, in this matter, it is determined whether the write channel processor and the read channel processor are both functioning correctly.

It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, a method, or a computer readable medium. Several inventive embodiments of the present invention are described below.

In one embodiment, a built in self test used in a system for writing signals to a storage medium and reading signal from the storage medium is disclosed. A digital write path receives input data and processes the input data for writing the input data to the storage medium. A junction is connected to the digital write path. A first branch of the junction is connected to a digital simulated media transfer function generator and a second branch of the junction is connected to a write path that leads to a write output. A noise generator is connected to the digital simulated media transfer function generator. A multiplexer has a first input and a second input. The first input is connected to the noise generator and the second input is connected to the output of a read path. Thus, a digital test path is provided for the system for writing signals to a storage medium and reading signal from the storage medium.

In another embodiment, a built in self test used in a system for writing signals to a storage medium and reading signal from the storage medium is disclosed. The system includes a read input that is configured to receive an input read signal. A variable gain amplifier is configured to amplify the input read signal. A differentiator is configured to differentiate the input read signal to model the effect of the storage medium. A data output outputs data obtained from the input read signal after the read signal is processed by the differentiator. Thus, an analog test path is provided for the system for writing signals to a storage medium and reading signal from the storage medium.

These and other features and advantages of the present invention will be presented in more detail in the following specification of the invention and the accompanying figures which illustrate by way of example the principles of the invention.

The present invention will be readily understood by the following detailed description in conjunction with the accompanying drawings, wherein like reference numerals designate like structural elements, and in which: Figure 1 is a block diagram illustrating a write channel processor testing circuit.

Figure IB is a block diagram illustrating a read channel processor test system.

Figure 2A is a block diagram illustrating a write channel processor.

Figure 2B is a block diagram illustrating a read channel processor.

Figure 3 is a block diagram of a system that includes both a write channel processor and a read channel processor with an analog test loop and a digital test loop provided.

Figure 4 is a block diagram illustrating in more detail an on chip BIST system for a read/write chip.

Reference will now be made in detail to the preferred embodiment of the invention. An example of the preferred embodiment is illustrated in the accompanying drawings. While the invention will be described in conjunction with that preferred embodiment, it will be understood that it is not intended to limit the invention to one preferred embodiment. On the contrary, it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The present invention may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the present invention.

In one embodiment, the system and method disclosed is used with a read channel processor and a write channel processor that process signals for a magnetic storage disk in an EPRML system. For the purpose of example, this embodiment will be described in detail in the following description. It should be noted, however, that in other embodiments, the test loop back method may be used with other types of data channes.

Figure 2A is a block diagram illustrating a write channel processor 200. Write channel processor 200 includes a scrambler 204 and an encoder 202. Encoder 202 encodes data for writing to the disk and scrambler 204 is used in some embodiments to scramble the input data to reduce the likelihood of a repetitive pattern being written to the disk. A synch pulse inserter 206 inserts synch pulses into the encoded output and a precoder 208 precodes the write signal. A precompensator 210 precompensates the signal prior to writing to the disk.

Figure 2B is a block diagram illustrating a read channel processor 210. Read channel processor 210 includes an analog to digital converter 212, an equalizer 211, and a Viterbi detector 214 that determines the most likely input signal written to the read channel. Read channel processor 210 also includes a decoder 216 that decodes the output of the Viterbi detector and a descrambler 218 that descrambles the decoder output. If the system works correctly, then the output data from the decoder of read channel processor 210 is the same as the data input to encoder 202 in the write channel processor.

Figure 3 is a block diagram of a system that includes both a write channel processor 300 and a read channel processor 302 with an analog test loop and a digital test loop provided. In one embodiment, the system is implemented on a single chip. When the chip is operating in normal mode, data is input to write channel processor 300. As mentioned above, write channel processor 300 encodes the data and adds synchronization marks and in some embodiments write channel processor 300 also scrambles the data before writing the data to the magnetic disk storage medium. The data output from write channel processor 300 is sent along write path 310 and written to a magnetic recording disk 312 using a magnetic recording head 313.

In normal operation, the read channel reads data from magnetic storage disk 312 using magnetic read head 315. The signal is transferred to a read channel processor 302 via a read path 320.

In addition to read path 310 and write path 320, a digital test loop path 330 and an analog test loop path 340 are also shown. The two test loops are described in further detail in connection with Figure 4. The two loops provide modeling of the effect of the channel on the signal, including noise introduced to the signal by the system as a result of imperfections in the channel. Digital loop 330 includes a digital simulated media channel transfer function generator and analog loop 340 includes an analog channel simulator.

A digital multiplexer 334 is provided to switch between inputting the digital test loop signal to read channel processor 302 or an actual data signal read from the data storage media. In one embodiment, the MUX is set to input the signal from the loop 330 only during testing and once the system is tested, the MUX is set to transfer the read signal from the disk to read channel processor 302. A register is provided to change the input of the MUX that is connected to the read channel processor. One advantage of this architecture is that when systems fail, the chips on the board may be tested by reactivating the test loop.

An analog multiplexer 334 is provided to switch between inputting the analog test loop signal and a read signal from the magnetic storage disk. Multiplexer 344 includes a register that contains a bit which switches the input of multiplexer 344 between the output of the magnetic storage disk and output of the analog test loop.

Thus, an analog test loop is provided that simulates the transfer function of the data channel and also provides noise for the purpose of testing the performance of the system with noise.

By providing the internal test loops shown above, the system shown in Figure 3 eliminates the need for providing an on chip signature analyzer to analyze the write channel processor output and a complex pattern generator to simulate an input signal to the read channel processor for testing. The system may be tested by simply inputting some data to write channel processor 300 and configuring the two multiplexers to activate either the digital test loop or the analog test loop. When, for example, the digital test loop is activated, the write channel processor itself provides its own circuitry to generate a signal to be read by the read channel processor and so that circuitry need not be simulated by a pattern generator. Also, no high speed signal analyzer is needed to analyze the output from the write channel processor 300. The signal is propagated through the read channel and the output of read channel may simple be checked against the written input. If the system is working correctly, then the output of the read channel processor matches the input data. In one embodiment, testing may be further simplified by inputting a static data signal to write channel processor 300. It is not necessary to input changing data to write channel processor 300 because, as mentioned above, write channel processor 300 includes a data scrambling module that scrambles the data and thus provides appropriate random test data for the system from a static input.

Figure 4 is a block diagram illustrating in more detail an on chip BIST system for a read/write chip 400. Chip 400 includes a write input 401. Write input 401 is connected to a digital write path 406 which includes an encoder, a scrambler, a synch pulse inserter, and a precoder. The output of the digital write path 406 is sent to a write precompensator 404 which is connected to a write driver 402. The output of write driver 402 is sent to a write output 405 for writing a signal to a disk. It should be noted that a preamplifier may also be included in the write path either on the chip or off the chip after the write driver.

The output of the digital write path 406 may also be connected through a junction 410 to a digital test loop that includes a digital simulated media transfer function generator 412 and a digital noise function generator 414. Simulated media transfer function generator 412 and noise function generator 414 combine to digitally model the effect of the physical media on the signal.

In one embodiment, noise function generator 414 generates a pseudo random bit sequence of noise which is added to the signal. In one embodiment, the signal is a six-bit signal and the last three bits of the signal are randomized using the pseudo random bit sequence. In addition, it is also possible to randomize additional bits of the signal to simulate more serious error conditions.

The output of noise generator 414 is input to a multiplexer 420 that selectively connects either the digital test loop or the read path output from an analog to digital converter 440 to the data output. Thus, junction 410 and multiplexer 420 may be configured to either connect the output of the write precompensator to write output 405 for writing to disk or to a digital test loop and a read channel data output 406 for the purpose of testing the write path. In one embodiment, the configuration is accomplished by setting bits in registers that control the state of junction 410 and multiplexer 438.

An analog test loop may be activated by connecting the write output 405 to the read input through an attenuator 430 and a coupling capacitor. Attenuator 430 is used because the write output signal is generally stronger than the write input signal. The read input is connected to a variable gain amplifier 431. In addition, a noise generator 432 may be selectively connected to variable gain amplifier 431 for the purpose for adding noise to the signal for testing. Noise generator 432 may either be input directly to variable gain amplifier 431 or may be connected to the read input via'a summing junction that transfers both the read input and the output of noise generator 432 to the variable gain amplifier.

The output of variable gain amplifier 431 is connected to a filter 434. Filter 434 provides equalization of the read signal. In addition, for the purpose of modeling the data channel, filter 434 may also include a differentiator 436. Differentiator 436 differentiates the equalized signal, modeling the effect of writing the signal to a magnetic disk and reading the signal from the disk. The undifferentiated output of the filter and the differentiated output of the filter are both input to a multiplexer 438 which selects between the two inputs. The output of multiplexer 438 is input to an analog to digital converter 440. The analog test loop is activated in one embodiment by setting a bit in a register that activates a noise generator and also selects the active input of multiplexer 438. The output of analog to digital converter 440, as mentioned above, is connected to an input of multiplexer 420, which is connected to the read channel data output 406.

Thus, the analog test loop is activated by connecting the write input to the read input through an attenuator 430 and a coupling capacitor. Since the signal input to the read input does not include the effect of the channel, differentiator 436 is also included in the path to model the effect of writing and reading the signal to and from a magnetic disk.

The inclusion of differentiator 436 in the analog test loop path enables the effect of the data channel to be modeled so that the analog read path circuitry can be tested.

An analog and a digital test loop has been disclosed for a system that writes signals to a storage medium and reads signals from the storage medium. The analog test loop includes a differentiator that models the effect of writing and reading on the write signal. Both the analog test loop and the digital test loop include a noise generator for adding noise to the signal. The analog test loop provides simultaneous testing of the entire system. The digital test loop allows the digital write path to be tested independently of the read path.

Although the foregoing invention has been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. It should be noted that there are many alternative ways of implementing both the process and apparatus of the present invention. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.

Claims

1. A built-in self test used in a system for writing signals to a storage medium and reading signal from the storage medium comprising: a digital write path that receives input data and processes the input data for writing the input data to the storage medium; a junction connected to the digital write path wherein a first branch of the junction is connected to a digital simulated media transfer function generator and a second branch of the junction is connected to a write path that leads to a write output; a noise generator connected to the digital simulated media transfer function generator; a multiplexer having a first input and a second input, the first input being connected to the noise generator and the second input being connected to the output of a read path; whereby a digital test path is provided for the system for writing signals to a storage mediurn and reading signal from the storage medium.

2. A built-in self test used in a system for writing signals to a storage medium and reading signal from the storage medium as recited in claim 1 wherein the storage medium is a magnetic storage medium.

3. A built-in self test used in a system for writing signals to a storage medium and reading signal from the storage medium as recited in claim I wherein the system for writing signals to a storage medium and reading signal from the storage medium is a PRML system.

4. A built-in self test used in a system for writing signals to a storage medium and reading signal from the storage medium comprising: a write channel processor write path a read channel processor read path a digital test path ; and an analog test path.

5. A built-in self test used in a system for writing signals to a storage medium and reading signal from the storage medium comprising : a read input that is configured to receive an input read signal; a variable gain amplifier configured to amplify the input read signal; a differentiator configured to differentiate the input read signal to model the effect of the storage medium; a data output to that outputs data obtained from the input read signal after the read signal is processed by the differentiator; whereby an analog test path is provided for the system for writing signals to a storage medium and reading signal from the storage medium.

6. A built-in self test used in a system for writing signals to a storage medium and reading signal from the storage medium as recited in claim 5 further including an equalization filter that is connected between the differentiator and the variable gain amplifier.

7. A built-in self test used in a system for writing signals to a storage medium and reading signal from the storage medium as recited in claim 5 wherein the differentiator is included in an equalization filter.

8. A built-in self test used in a system for writing signals to a storage medium and reading signal from the storage medium as recited in claim 5 further including a noise generator that generates noise in the output of the variable gain amplifier.

9. A built-in self test used in a system for writing signals to a storage medium and reading signals from the storage medium as claimed in claim 1 substantially as described herein with reference to the accompanying drawings.

10. A built-in self text used in a system for writing signals to a storage medium and reading signals from the storage medium as claimed in claim 4 substantially as described herein with reference to the accompanying drawings.

11. A built-in self text used in a system for writing signals to a storage medium and reading signals from the storage medium as claimed in claim 5 substantially as described herein with reference to the accompany drawings.