GB2341242A - Signal decoding apparatus - Google Patents

Abstract

A signal decoding apparatus for remotely controlling a programmable device eg a lighting dimmer irrespective of phase of a power supply comprises an input conductor receiving control data signals to be supplied to an input data register, a memory storing a number representing a predetermined operating condition of a programmable device, microprocessor means to retrieve the number from the memory, register means to store a representation of the retrieved number, an AC power connection and a zero cross detector coupled to the AC supply. The microprocessor is responsive to the zero crossing detector to allow a control signal to be input to the input data register that is independent of the phase of the power supply and in a form comparable to that of the number stored in the memory. A comparator compares the control signal input from the input data register and the stored number register to produce an enable signal in response to a match between the two compared signals.

Description

2341242 "MULTIPLE CHANNEL, MULTIPLE SCENE DIMMING SYSTEM" This invention

relates generally to lighting controllers, and in particular to light dimming systems.

Light dimming systems are used to control multiple lighting circuits which may be widely separated from each other by a substantial distance, for example in a restaurant, a large meeting hall or in a theater. The lighting circuits are connected to power dim.mers so that the intensity of the lights can be controlled collectively, individually or in groups whereby a variety of different combinations of lighting levels may be selected for achieving different lighting effects (scenes).

Typically, each light or group of lights is selectively controlled through a power dimmer, which is in turn connected to an individual controller or operator i5 switch. In such a system, separate sets of wires run from a central controller to each light or group of lights. Sometimes, dimmers are included along with wall-mounted toggle switches for controlling the level of power supplied to the separate lighting circuits. Such dimmers visually take the form of rheostats which are manually set to the desired level of brightness- Consequent-ly, even for small installations, a large amount of wiring is necessary to connect all of the lights to their respective power dimmers, and to connect the power dimmers to their respec- tive controllers.

Conventional lighting control and dimming system s p.-ovide a main switch control station and one or more renote dimming stations t-hat are capable of independent ONIO--F oneration and dimming control. Such systems utilize three-way and four- way dimmer switches in combination with one or more traveler -wires to provide independent ON/OFF dim-:.iing operation at each remote location.

in a typical installation in which a single overhead light is controlled and dimned from a main station and a remote station, a manual, two-way dimmer switch is installed in a wall box at the main switch station, and a manual, two-way dimmer switch is installed in a wall box at the remote switch station. One side of the lamn load is connected to the nower source neutral conductor and the other side of the lamp load is connected by a load conductor to the main station switch. A hot conductor connects the hot supply line to the remote dimmer switch. The main di=er switch and remote dimmer switch are further interconnected by an auxiliary power distribution conductor, commonly referred to as a traveler conductor, a hot 1ne conductor and a ground safety conductor. In this two- way switching and dimming arrangement, the lamp load is wired in the conventional "switched hot" configuration.

Some remote dimmer switches have been connected to a master dim-mer controller in such installations, but have required two or more additional wiring conductors and a remote power supply for providing logic high and logic low control signals to the master switch control circuit for CIN and OFF operation of the lighting load. In a retrofit installation in which the main power switch and remote switch are to be replaced, it is desirable to remove the switches at each switch station and install a main dimmer controller in the main station wall box and a remote dimmer in each remote station wall box. Moreover, it is desirable to connect the remote dimmer switches to the main dimmer switch control circuit by utilizing only the existing traveler conductor and ground safety conductor that interconnect the main and remote wall box switch stations. In new wiring installations, a single conductor (e.g- traveler conductor) interconnection of remote dimmer stations with the master dimming controller is also desirable for the purpose of simplifying the -wiring interconnections and for reducing wiring installation costs.

In domestic and commercial installations, two- phase power is supplied, with phase A power being applied to one group of electrical loads, and phase B power being applied to another load group. Consequently, in a large area lighting installation, some of the lighting loads will he supplied by phase A power, and other lighting loads will be supplied by phase B power. Dimming systems typically utilize semiconductor switching devices whose duty cycle is controlled with reference to the phase of the current wavef orm. Because of the phase dif f erence, it is dif f icult to utilize conventional light dimming systems which emploY a microprocessor controlled memory unit for selectively controlling the application of power to a specific group of lighting loads, individual ones of ',.,;hich may be separately energized by phase A and phase B power.

Consequently, a light d-inming system is les-reci Jr. which the amount of wiring required for connecting a controller to multiple power dimmers is substantiallv reduced- Such a lighting control and dimming system. desirably should be operable -,.?ia a single conductor by which several individually-dinmable lighting loads can be controlled without appreciably increasing the anount of wiring. Moreover, in large area lighting, multiple power phase installations, the lighting control and dinming system should be capable of reliable operation in which dimmer station address signals from a remote controller or a master controller can be commun3-cated independently of line phase per dimmer station or controller station.

The presenz invention provides, in various aspects, 'light di-nming systems, appararus devices and controllers as defined in the claims.

According to one aspect of the present invention, a lighting control and dimming system utilizes a single conductor, for example the traveler conductor of existing -wiring, for transmitting analog data signals to each dimmer of a light/dimmer group. The master controller includes a signal generator for generating a unique and predetermined analog data signal corresponding "Cc a predetermined lighting intensity level for a particular scene. The predetermined analog data signals are stored in a read-only memory of a microcontroller in the master controller and are transmitted serially over the traveler conductor to each di-mrier unit. Each dimmer unit. includes a micro i I controller and read-only memory in which corresponding dimmer unit identification binary numbers are storedIn response to operator selection of a predetermined scene, the microcontroller selects from memory the corresponding binary data signal and transmits it serially as an analog data signal over the traveler conductor to an input shift, register in each dimmer. The data content of the input shift register is compared, hit-by-bit, wLth a binary number stored in the dimmer ROM. A serial bit comparator produces an enable signal in response to a bitby-bit identity match between the transmitted analog data signal and the preset binary identification number stored in the dimmer ROM. Only a match between the transmitted analog data signal and the stored binary number will produce a predetermined scene. After being enabled, the dimmer can be manually adjusted to a new intensity setting, as desired.

According to another aspect of %the invention, the remote signalling and selection of a specific scene is made independently of phase by sampling the logic value of the remote input analog data signal immediately following a logic I to logic o transition of a zero cross signal. If the high to low transition occurs at any time during which logic 1 is loaded into the zero crossing signal is low, each dimmer remote input shift register. If no high-to-low transition occurs during that period, that particular bit of the remote input shift register is cleared to logic 0. Each time the zero crossing signal returns to logic high, the contents of each dimmer remote, input register are shifted and the contents of each in-put register are compared bit-by-bit to the contents of the binary unit. identification number that is stored in the read-only memory of each dimmer microccntroller. A particular dimmer is enabled in response to a natch between the analog remote signal and the preset binary number.

operational features and advantages of t'he present invention will be further understood upon consider- attion of tne followina deta-.'-"led description of an exe,niiD!arv embod- Jm.en-t- of the invention taken with --e-if::eren--e to --he accompanying drawings, -n which:

FIGURE 1_ is a block schematic diagram of a multichannel, multiple scene lighting and dimming circuit is constructed to embody the present invention; FIGURE 2 is a block sche.,nati-c diagram of the master controller shown in FIGURE 1; FIGURE 3 is a simplified circuit diagram of the serial bit comparator of FIGURE 2.

FIGURE 4 is a simplied schematic block diagram of an edge detector circuit for practicing the methods illustrated by the waveforms of FIGURES 5, 6, and 7; FIGURE 5 is a waveforn diagram of the analog data signal corresponding with a HEX-A pulse train; FIGURE 6 is a waveform diagram of the zero cross signal appearing on the output of the zero cross detector; FIGURE 7 and FIGURE 8 are waveform diagrams corresponding with FIGURE 5 and FIGURE 6, which illustrate an alternative high-to-low transition detection method; FIGURE 9 is a block schematic diagram of a lighting and dimming circuit which includes local and network remote controllers; and, FIGURE 10 is a schematic diagram of the low pass attenuator circuit shown in FIGURE 9.

Referring now to FIGURE 1, the lighting control system 10 of the present invention will be described with reference to the hot, neutral and ground safety power conductors 12, 14 and 16, respectively, of a 120 VAC, 60 HZ single phase AC power source which supplies operating power to multiple lighting loads LOAD 1, LOAD 2,..., LOAD N.

is According to conventional AC wiring practice, one ter-ininal of a lighting load, for example LOAD 1, is connected to the neutral supply conductor 14 by a load conductor 18, and the other terminal of LOAD 1 is connected to the switched terminal of a dimmer switch DIM 1 by a load conductor 20.

Preferably, the dim-ner switch DIM 1, in part, is a program- nable di=er as described and claimed in U.S.Patent 4,733,138 and U.S. Patent 5,194,858 which are assigned to the assignee of the present invention, and are incorporated herein bv reference.

Operating power is conducted through a thermal circuit breaker 22 which connects the conductor 12 and an J1.C i3ower bus 24. Load current is returned through the neutral cond-t-ictor 14 to a neutral bus 26. According to 0- conventional practice, the ground safety conductor 16 is also electrically connected to the AC neutral bus and is routed in parallel with the hot conductor!2 along the distribution path for safety purposes. At least the hot conductor 12 and 11--he ground safety conductor 16 is avail able at each d-L--=.er station- A traveler conductor 28 is also available in addition to the hot and ground safety conductors between the dimming stations.

In a typical system, the lighting control system of 10 includes a remote controller 30 and a master controller 32. The number of dimmer switches which may be coupled to the master controller 21 is limited to approximatelv 24 channels because of fan-out loading, since the dimners draw operating current in the standby operating mode.

is Referring now to FIGURE 1 and FIGURE 2, 'Che dimmer switches DIM 1, DIM 2,...' DIM N have identical circuit construction. The dimmer switch DIM 1 has a first power input conductor 34 connected to the hot power conductor 12 and a second power input conductor 36 con- nected to the ground safety conductor 16. The dimmer switch DIM I also includes a signal input conductor 38 which is electri-cally connected to the traveler conductor 28 which leads from the remote controller 30 and master controller 32 to each dimmer unit The remote controller 30 includes input power conductors 40, 42, 44 electrically connected to the hot, neutral and ground conductors 12, 14, 16, respectively, and a sig-nal output conductor 46 which is electrically con- nected to the traveler conductor 28. The traveler conductor 2s is electrically connected to a remote signal output node 48 of the master controller unit 32. The master controller 32 includes input power conductors 41, 43 and 43 electrically connected to the hot, neutral and ground safety conductors 12, 14, and 16, respectively.

It will be appreciated tha"t, the dimmer switch stations DIM 1, DIM 2, DIM 3,...' DIM N of a typical installation are widely separated with respect to each other, and with respect to the remote controller 30 and the master controller 32. Thus, at each dimming station and each controller, at least the hot conductor 12, the ground safety conductor 16 and the traveler conductor 28 are available for interconnection, but only the traveler conductor is required to be a common physical conductor connected to each unit for sending and receiving control signals independently of the line phase of power supplying each dimmer or controller.

Consequently, the dimmers, master controller and remote controller are wire-for-wire interchangeable with conventional two- way manual power switches. Each dimmer switch, the master controller and remote controller include manually operable, momentary contact switches designated ON and OFF, respectively. According to this arrangement, independent ON/OFF manual switch operation is provided at each controller and dimmer station.

Referring now to FIGURE 2, a master controller 32 4, shown that is capable of staring four scenes correspond- ing with four separate intensity levels (A, B, C, 0), in addition to ON and OFF connections and is connected in communication with one of the dimmer units DIM 1 via the traveler conductor 28 in the same ma=er as each of the other dimmer units of the system are connected. The controller includes a microcontrciler 30, a read-only matnory 52, a power supply 54 and a serial encoder register 56. These components are arranged in the form of an in.,formation storage and retrieval system for storing a predetermined number of scenes and performing all the necessary control functions- The microcon'troller 50 may be any one of several conventional microcontrollers that are commercially available- The type of microcontroller used -is largely dependent upon the capacity desired, and is designed so that a variety of logical and arithmetic operations may be performed on or between two accumulation registers including additions, subtractions, logical A-NDIS, ORIS, compares, complements, tests and shifts. Dedicated registers (not shown) are used for control of the svstem, and include a program counter, an index register, a stack pointer and a condition code register. These are generally controlled by the microcontroller logic, although they may be used or altered under the control of a stored operating program.

The microcontroller 50 includes a read-only memory (ROM) 52 in which an cperat'ng program is stored.

The operating program allows user programs and data to be stored in the read-only nemory, the working registers to be _11 examined and the execution of the user program to be supervised- Preferably, the read-only memory 52 is implemented by an electrically programmable read-only memory (EPROM).

The master controller 32 includes an ON switch, an OFF switch and four pre-set scene switches labeled A, B, 2 these switches are single pole, C and D. All o-IL single throw, non-latching push-button switches. The depression of each switch provides a connection to a ground reference voltage from a local power supply 54 and supplies the microcontroller 50 with a logical "zero" input. The microconIC-roller 50 recognizes the logical zero as a signal that the switch has been depressed. Other configurations of the switches are possible, provided that each switch have an operative and a non-operative position in order to provide logic signals to the microcontroller. The ON switch provides a fade "up" function when it is depressed and held. Likewise, the OFF switch provides a fade "down" switch which is operative when it is depressed and held in the closed position. The switches A, B, C and D correspond with four predetermined hexadecimal numbers, HEX-A, HEX-B, HEX-C and HEX-D which are stored in the read-only memory 52.

The operating program of the microcontroller 50 addresses the various input switches and determines the status o each switch. When a preset switch is depressed, its status is logic low and the operating program of the m-icrocontroller issues a command that retrieves the -12 corresponding HEX-coded signal from the read-only memory and inputs the HEX-coded signal to the serial encoder register 56. In the example shown in FIGURE 2, preset switch A is depressed, with F-EX signal HEX-A being re- trieved and input into the serial encoder register 56. The analog data signal corresponding with HEXA is transmitted to the traveler conductor 28 through an cutout conductor 48.

In the output mode, a communications interface transfers the coded signal HEX-A over an internal bus to the serial encoder register 56 according to a clock signal 55. Condition codes determine the transmission rate and the number of start, stop and parity bits required. In the example given herein of HEX-coded signals, all bits are information bits. The number of start, stop and parity bits is zero. The complete analog data word HEY-A is shifted out of the serial encoder register 56 through the output conductor 48 at the predetermined clock rate. FIGURE 5 shows the form of the analog data signal which is a series of pulses of variable duration between a high value (+V) representing logic "1" and a low value (-V) representing logic "0".

Each dimming unit, such as DIM 1, includes a decoder So for receiving, decoding and comparing the remote analog signal HEX-A and comparing it with a predetermined HEX coded unit identification number in a read-only memory 60- The encoded analog signal HEX-A is input from the -13traveler conductor 28 through an input conductor 62 to a shift register 64.

Referring to FIGURE 2, the controller 32 and dimmer DIM 1 could be respectively powered by different phases of a two-phase A-C power distribution system. In such a multiple phase system, the remote signalling and selection of each dimmer having a binary number stored in the EPROM memory 60 is made independently of the applied AC power phase by sampling the logic value of the remote input signal in relation to a zero cross signal of the AC line voltage applied to the dimmer. For this Purpose, a zero cross detector 66 produces a zero cross signal 68 that is derived from zero cross transitions of the line voltage on the hot conductor 12.

in accordance with one technique generally illustrated in FIGURES 5 AND 6, if a high-to-low transition of the remote input signal occurs at any time during which the zero crossing signal is low, the least significant bit of the dimmer input register 64 is set to logic 11111., Such transitions are shown by the arrows on the waveforms of FIGURE 5. if no high-to-low transition occurs during that period, that particular bit of the dim-mer input register is cleared to logic 11011. Each time the zero crossing signal returns to logic high, the contents of each dimmer register are shifted.

After shifting, the contents of each input register dimmer are compared bit-by-bit to HEX-coded numbers which are stored in the read-only memory 60 of the dimmer microcontroller 78. Each dimmer is enabled in response to a bit-by-bit 'match between the analog remote signal and a HEX-coded number stored in the memory 01' that dimmer. As shown in FIGURE 2, DIM 1 includes a semiconduc tor switching device, such as a thyristor having a gate -g" that is responsive to an enable signal from comparator 72.

Referring now to FIGUREE 4, FIGURE 5 and FIGURE 6, f the zero cross in response to a high-to-lcw transition oj signal 68, the operating program of the microcontroller 78 retrieves a binary nu-,-,-Lber (for example, HEX-A) stored in the read-only memory 60 and inputs it to a serial encoder register 70. Each time the zero crossing signal returns to t register 64 logic high, the contents of the dimmer shij and the serial encoder register 70 are shifted by the output of an edge detector circuit 99, which is a portion of the decoder 58, as shown in FIGURE A. The bit contents of each register are conducted to a serial bit comparator 72 through output buses 74, 76, respectively. FIGURES 5 and 6 have similar horizontal time axes Referring now to FIGURE 3, the shift register 64 and the serial encoder register 70 are six bit shift registers that are designed to hold the bits of the HEX encoded data word transmitted over the traveler conductor 28. In the present example, where the HEX encoded data word contains six bits of information, the encoded analog signal on conductor 62 is fed one bit at a time into the shift register 64 until all six bits are contained in the register and are simultaneously conducted over the corre- sponding six output lines 64A, 64B, 64C, 64D, 64E and 64F. Likewise, the binary number HEX-A, which was previouslv stored in the read-only memory 60, is retrieved by a -microcontroller 78 and is fed one bit at a ti-ne into the serial encoder register 70 until all six bits are contained in the register. The logic value of each bit stored in the serial encoder register 70 is conducted over output lines 70A, 70B, 70C, 700, 70E and 70F.

corresponding bits 64F and 70F are simultaneously applied to the inputs of an exclusive OR (XOR) gate 80 for comparison. Likewise, the corresponding bit pairs of the remaining bits of each register are input to exclusive OR (XOR) gates 82, 84, 86, 88 and 90, respectively, for comparison of each bit pair. According to the logic of an exclusive OR (XOR) gate, a logic zero on both inputs yields a logic zero and a logic one on both inputs yields a logic zero. If there is a logic match between corresponding bits, the output of the exclusive OR gate will be logic zero. Consequently, when there is an identical match between the remote analog data word (HEX-A) and the binary number (HF-X- A) stored in the read-only memory 60, the output of each XCR gate is logic zero.

The outputs of the XOR gates are inverted by inverters 92, 94, 96, 90, 100 and 102, respectively. The inverted outputs are input to an AND gate 104 which provides a logic one enable signal 106 when each of its inputs is at logic one value. This will occur only when there is an exact match between the encoded remote signal (HEX-A) and the binary numbers stored in the read-only memory 60 (HEX-A) - Under this condition, the output of each XOR gate is logic zero, and each inverted out-put is logic one. in response to that condition, the AND gate 104 produces a logic one signal on the output conductor 106, and is logic zero under all other input conditions- The ON function and the OFF -function are generated in response to all data bits of the shift register 6.A being at logic one value (ON function), or all data bits are logic zero (OFF function) The output of each data bit is input to an AND gate 108 which produces the ON signal in response to each input being at logic one value. Likewise, the bit contents are input to a NOR gate 110. According to the logic function of a NOR gate, a logic high output is produced in response to each input being at logic zero value. By this arrangement, the OFF signal is produced when each bit of the shift register 642 is at logic zero- Accordingly, it will be seen that each dimmer unit can be loaded with unique encoded numbers which correspond to the encoded unit identification numbers stored in the read- only memory 52 of a remote controller or the main controller 32 in order to obtain a particular dimming level on the dimmer output. When an input switch (ON, A, B, C, D, OFF) is depressed, encoded analog signals are conducted over the traveler conductor 28 as a serial stream of analog pulses that are applied to the shift register 64 input of each dimmer unit. In this manner, each di-mmer unit is enabled by r,.,anQallv depressing one of -17the selector switches that results in the above-desc-_ibed match occurring.

The master controller 32 of FIGURES 1 and 2 allows selection of any scene, fade to "FULL" (ON) or 11OFFIt and raise or lower all dimmers together, without losing the scene or preset memories. The remote controller of FIGURE 1 has selector switches that will select only the ON scene or the OFF scene and raise or lower all channels togetherFor selection of a specific scene, the desired switch ON, A, B, C, D or OFF is depressed in the master controller- The current scene switch includes a light emitting diode (LED), not shown, which will glow to indicate scene status. To raise all dimmer channels together, the ON scene switch is pressed and held until the lights reach the desired is intensity. When all channels are raised or lowered together, the system is in the ON condition. although each dimmer is not necessarily at its preset ON level and may, in fact, be at a lower intensity.

Referring now to FIGURE 7 and FIGURE 8, in an alternative embodiment of a signal decoding technique, the microcontroller 78 of each dimmer includes another subroutine program that performs exactly as stated above except that it waits for the zero crossing to transition high before checking the remote input 62 of the decoder 53.

This is necessary to accommodate a condition in which the first routine is not able to decode the remote pulse L-rain correctly, thereby assuring more reliable operation- According to an alternative method of decoding the four remote signals (A, E, C, D), each time a zero crossing signal makes a high to low transition, such as shown by the down directed arrows in FIGL-RE 8, the remote input to the microcontroller is sampled to obtain the logic level. If the remote input is high, then the least significant bit (LSB) of a first remote input register is set 'to logic "111. If the renote input is 1.ow when the zero crossing makes its high to low transition, then the L5B of the register is cleared to logic zero (11011) After setting or clearing this bit, the register contents are shifted left and an exclusive OR operation is per-formed between the remote input register, and a second remote input register- The result of the exclusive OR (XOR) operation is is then compared with the four binary numbers for the four dimmer scenes. If there is a match, then the dimmer has successfully decoded a remote signal.

In the second re-mote memory register, the status of the remote input for the microcontroller 78 is stored based in response to a low to high transition of the zero crossing signal. For example, when the zero crossing signal changes from a low logi c level to a high logic level, such as shown by the up directed arrows in FIGURE 8, the remote input 62 to the micrcontroller is read to check its logic level. If it is high, then the least significant bit (LSB) of the second reniote input register is set to logic high (11111). If it is logic low, then the L5B of -the renote, input register No- 2 is cleared to a zero. After -19setting or clearing this bit, the register contents are shifted left.

Referring now to FIGURE 9 and FIGURE 10, a low pass attenuator circuit 110 is interposed betweenthe remote master controllers 30, 32 and the dimmer DIM i. The attenuator circulit i10 permits a single remote controller, for example remote controller 30, to change a single d=ing station, for example DIM 1, without affecting the intensity setting of any of the other dimmers that are connected to the network traveller conductor 28. Preferably, the attenuator circuit 110 provides attenuation in a ratio of about 20:1_ The attenuator circuit 110 includes a low pass filter 112 connected in series with the local remote controller 30 on input conductor 46 and input node 33 to decoder 58. In this example, the low pass filter 112 includes series resistant R20 and $21 with resistor R19 and camacitor C10 connected to resDective terminals of resistor R201 R19 and C1O have other terminals that are grounded.

The network traveller 28 is decoupled with respect to the input terminal node 33 of the dimmer DIM 1 by a circuit portion 114 which is connected inseries electrical circuit relation between traveler 38 and input node 33. In circuit portion 114, a diac diode D3 presents a high impedance to the f low of current from the input node 33 through the network remote controller input terminal from conductor 38. Circuit portion 114 also has a low pass filter comprising, in this example, series resistors RS and R4 with resistor R18, capacitor C6 and capacitor C9 each -20having a terminal connected respectively to a firs-, terminal of RS, a second terminal of RS, and the Side of R4 connected to the input node 33. Second terminals of R18, C6 and C9 are grounded.

1. Signal decoder apparatus, suitable for use in a progra=able device that can be controlled from a location remoze the device independently of phase of AC supply pc,;er to 'which the device is connected in use, comprising:

an input conductor for receiving control io data signals and supplying the signals to input data register means coupled to the input conductor; a memory for storing a n u= er representing a predetermined operating condition for the programmable power conductors for connection with an alternating current (AC) source of AC line voltage; a zero cross detector coupled to one of the power conductors for producing a zero cross signal from zero cross transitions of AC line voltage; a microcontroller, coupled to the memory, for containing an operating program to retrieve the stared n=ber from the memory; a stored data register, coupled to the microcontooller, for receiving a signal from the microcon- troller representing the stored number; the microcontroller also being coupled to the zero cross detector and the input data register means and -JincludJng means responsive to zerc, =-oss signals fro-,n th-e zerc cress detectcr to allow the input data rGaisi-e -neans to receive a zc--izrol sjg-.nal fren thee input --or.ducto-r that is of nhase of -oc-,4er and is in a f co---narab-e to the stored number from z-'ne a comparatcr cou-pled to the irput data register means and --c the stored data for recev ina a-rid comparing con-re-' s-Jgr.a' fror, the input data register nreans the stored signai from r-he stored data register and for an output "enable" signal i_n res-owse to a -natch bet-weer. compared signals.

2. Signal decoder a-onarazus in accordance withcla-im 1 wherein.

_he in-put data register -means, the zero is cross dezector, and the microcontroller are arranged to coo e-ate so that a control sig-nal, rec:aived an the input conductor, in an analog form of variable duration pulses of a magnitude 11111 fron a base "0" is translated -=c a digital -om a base "0" in L_ - for-m of binary pulses of a inagn-itude "I" L the iinput data register means; and r_he me-nory, m-icroccn--rolle-- and S-r-cred data register are arranged to cooperate- so that a stored number J- th.e memory is rece-.ved also in a digital form of binary pulses of a -magnitude "I" fr,-,ti a base "0" in the stored data register.

13 - 3. Signal decoder apparatus in accordance w..., c", a m 1 o r a j 2!1-- - w, ei n:

the zero cross detector is arranged --c nroduce zero cross sic-rials as a series of nulses with to low transi-tions and low to high transitions correspond ing to the zero cross zransitions off the line vclzage.

4 - Signal decoder apparatus in accordance any one o_f claims 1 zo 3 where-in: the zero cross detecitor, the microcon- io troller, and the input data register means are further arranged to cooperate so that, in response to a control signal in the analog for-m on the input conductor, the register means is set '--c a logic 11111 bit unon each 1,111 to "C" transition of the control signal occu--rJncj when the is zero cross signal is low and the register means is set to a logic 1, 011 bit when the zero cross signal is low between transitions and the control signal has no I'i" to "0" transition.

signal decoder apparatus in accordance with any one o-IE claims 1 to 3 wkierein:

the zero cross dettector,the -m-icrocontro-l- !er, and the input data register means are f ur-=her arranged tc cooperatle so that, in response to a control sicnal in zhe analog on the input conductor, the register means is set to a logic "I" bit, upon each transition of zP---0 cross signal in one direction occurring when the controll signal -;:..s loc--c "I" and is set to a "C" bit upon each transition of z,7-e zero cross sia-nal -ir, tIhe sa,-te one direction occurring Wnen the analoc. cor.zrcl signal is logic S 6. ignal decode-r annarazjs -n accordance an,v C-le 0 C1;2ims 1 to 5 W,-, the input data register means cc-.-np-- ises a 'ster that receives - shift rea -he controL signal in digital L 0 --.nt.

io 7. Signal decoder apparazus in accordance wi--h ariv one of clai-ns 1 -c 5 -whe.-ejn:

Ihe input, data reg-'ster means com-prises a.,ff-irst input register and second input register; the frirst innut register is arranged to sample the control signal nulse level uinon high to low transitions of -he zero cross signals and the second input register is arranged to sample 'the control signal pulse level upon low to high transitions of the zero cross signals.

8 Signal -,accder apparatus.,"-n accordance with claim 7 wherain:

the in-put dat-a regIster means further comprises neans for performing an exclus--,,;e OR operation on the conzrcl signal as sampled bv the recmective first and second input regis'ners and supplying the result of t.he exclusLve OR c-oeration to the co=,Qara:ior.

9 Signal decoder apparatus in accordance wi--h claim 8 w.r,-erein:

the Ifirst. input register is arranged to a data bit set to logic: "I" if the conc-.-ol signal on the input cor.duczor is high whan a high -.-c low transition of the zero cross signals ccc-,-lrs and a further data bit sat to logic 11011 if the control signal an the -innut conduc--or is low when the high to low transition of the zero cross signals occurs; and 0 the second input register is arranged to have a datta bit set to logic 11111 if the control signal on the input conductor is h.gh when a low to high transition of the zero cross signals occurs and a fur-ther data bit set to logic "C" if the control signal on the input conductor is is low when the low to high transition cE the zero cross A prograrunable device c omp r i S i n g, i n combination, signal decoder apparatus in accordance with anyone of claimsi to 9 and a SWitChin.a device coupled to the comparator of the signal decoder apparatus to respond to an ou-k-put "enable" signal from the comparator and produce the mredetermined operating condition.

z crogran,-,nable device in accordance w:Lz-l', claim 10 in which the m is a rog-rammable device lighting wherein the sw-i-L-ch-ing device has mower and load e-rminals for interconnection with the AC mower source and -26 lc-ad and Cie device further has 12 Signal decoder ae=arat-,-'s i.n accordaince with any one 0-f 1 Z0 9 wnere-n:

the innut data re(=--ster means, t'-.-ie ze-rc) cross detector, and the are further arranged to ccoce:ate so that a conzrcl signal in the --ed -he digital analog forn, is subiect zo ba-i-nw 4= for-m and eacl7_ bit thereof utilized -'--v --'n= comparator to produce an enable signal 13 Signal decoder apparatus i-n accordance with any one of clairms 1 --o 9 or 12 wherein:

each of the innu.'- data register means and :t register with a bit is the stored data register is a shif capacity equal to information bits of the control signal and the stored -iL-L-c-ber, and the registers, nicrocontroller, and comna--a't--or are further arranged so that- control signal recl,-,-ires no prior or subsequent data bit- for indicating the start or ter-mination off a control signal.

d a 14 A progra=ab-e device in accord claim 1 furtIner an inpuz circuit having an output terminal coupled to an inpult- node at th---- input conductor for the S- -us ignal decoder an-nara- -27 irst j,-1z)ut -he incut ci-rcu-it having a ter-minal fer receiving a control signal from a first external controller that is arranged to supply control signals to the --nstant programmable device and a second input terminal for receiving a control signal from, a second eyzernal controller that. is arranged to sunciv cortrcsignals to a plurality of programmable devices including others in addition to the instant progrannable device; the input circuit including a first subc-i-r- cuit portion coupled be-tween the first -Input terminal and the input node and a second subc-ircu-it portion coupled between the second inpuz terminal and the input node; the first and second subcIrcuit mortions being arranged to allow control signals from such a first is external controller to be received at the inpur- node without affecting any other programmable devices to which such a second external controller is counlad.

A programmable device in accordance with clain 14 wherein:

said first circuit subportion comprises an attenuator circuit including a first low pass filter; and; said second circuit subportion comprises a second low pass in series with a saniconductor device presenting a high ii-,iwedance blocking control signals received at the input node _from the first circuit subcortion fron, being received at the second incut terminal.

- 28 16.

erence -o -scr4]Ded with re_. -'-,e drawnzs.

2- 17 A device ccmiD---s-n-, a.)i:arat,-,s in accor--ance wit:h c:--a-m 16 a s.,,;ii tch-ing device ccupp-ed ofE the signal Jecoder acDarat,,is tc res-;3ond to an c)uz--u: _rom the conna--a-or and produce 18 A_ a-' ly as reference:o the 19 d -i as he g