GB2340685A

GB2340685A - A bias voltage generator for CMOS input buffers

Info

Publication number: GB2340685A
Application number: GB9817397A
Authority: GB
Inventors: Trevor Monk; Peter William Hughes
Original assignee: SGS Thomson Microelectronics Ltd
Current assignee: STMicroelectronics Ltd Great Britain
Priority date: 1998-08-10
Filing date: 1998-08-10
Publication date: 2000-02-23
Anticipated expiration: 2018-08-10
Also published as: GB9817397D0; GB2340685B

Abstract

A bias voltage generator for CMOS input buffers comprises a scaled dummy inverter 124-127 to which a reference input signal Vref1 corresponding to the desired input switching threshold is applied. The output of the inverter is fed back directly to the gates of the control transistors 126 and 127. This signal CTRL1,CTRL2 is conveyed to the corresponding control transistors in each input CMOS buffer, thereby stabilising the switching thresholds of the buffers against process, temperature and supply voltage variations. An uncontrolled inverter 122 may be placed in parallel with the controlled inverter 123.

Description

2340685 CONTROLLABLE BIASING CIRCUITRY

The present invention relates to control circuitry for an input buffer for receiving and outputting data. In particular the input threshold voltage of the buffer may be precisely controllable to accurately meet specifications and to decrease input rise/fall propagation delays through the buffer output.

In order to receive data from an external source, integrated chips need dedicated circuitry in order to t ' ake the off-chip signal and buffer it ready't& be used by the integrated chip (IC) core logic circuitry. In buffering the signal the circuitry typically converts variable voltage signals from the external source to a substantially square signal at essentially one of two voltages. Figure 1A shows part of an IC attached to a circuit board 12 in which input signals are input to bond pads 13 on the chip package 15, which signals are buffered at 14 prior to use by the core logic 10.

A standard input buffer circuit for such an IC typically consists of a pair of standard P/N inverters as shown in Figure 1B connected between an input bond pad and the core logic circuitry of the chip. As shown each inverter may be made up of a P-type and N-type device as is well known in the art. Such circuitry generally works well but is not suitable for applications in which the chip interface specification requires a very precise input threshold of the buffer.

Figure 1C shows how the output voltage V2 of the first inverter shown in Figure 1B varies as a positive ramped input voltage V1 on a bond pad 13 is increased. As the positive ramped input voltage VI increases to around the threshold voltage Vth the output from the first inverter passes through a transition from high to low output. Likewise if the input voltage were represented by a negative ramped voltage the output of the first inverter would have a transition from a low to high output at a threshold voltage. For applications which require a very precise 2 input threshold the transition made by the inverter output must occur within a precisely def ined voltage range. Under these conditions a standard P/N inverter may have too much variation in its input voltage threshold due to variations in the strength (current driving capacity) of the P and N-type devices making up the inverter.

An existing solution to that problem is the use of a true differential mode circuit for example a long-tailed pair comparator circuit. However such circuitry hLs other inherent disadvantages such as a pobr'rejection of power supply noise at high frequency as well as causing a static current drain which prohibits IDDQ testing of the rebulting IC.

It is therefore an aim of the present invention to at least partly overcome the problems existing in the prior art and to allow for a process /voltage/ temperature insensitive circuit which has a precisely controllable input voltage threshold with the advantages of both the inverter and comparator circuits but with none of the disadvantages.

It is also an aim of the present invention to allow for the precise control of input threshold voltage for both positive and negative going input voltages to ensure that the circuitry provides identical propagation delays through the input buffer circuitry for both positive and negative going input signals.

According to the present invention there is provided biasing circuitry comprising a controllable inverter including at least one control element for varying the response of the controllable inverter to a first reference voltage, wherein the ouput of said controllable inverter provides a control signal for each said at least one control element, and wherein each said control signal provides a biasing signal.

Preferably said controllable inverter further comprises a first branch and a second branch for cooperatively generating an output 3 signal at the output node, each branch being connected to a f irst input node to receive the f irst reference voltage, wherein at least one of the branches includes a control element for controlling the relative voltage sensitivity of the f irst and second branches thereby controlling the response of the controllable inverter to the reference voltage.

Advantageously the relative transconductance of the f irst and second branches is variable' in respect to each said control signal.

Conveniently said first branch is connected between a first voltage supply and the output node, and said second branch is connected between said output node and a second lower voltage supply.

Embodiments of the present invention will now be described hereinafter by way of example only with reference to the accompanying drawings in which:

Figure 1A is a schematic diagram showing the conventional position of an input buffer, Figure 1B is a schematic diagram of an input buffer used in the prior art,

Figure 1C shows how the output voltage of a prior art input buffer varies as input voltage is increased,

Figure 2 is a schematic diagram showing an input buffer, Figure 3 is a schematic diagram showing an input circuit, Figure 4 shows how the voltages and output of the input buffer shown in Filure 2 vary, Figure 5 shows the input circuit of Figure 3 in more detail, 4 Figure 6 is a schematic diagram showing the biasing circuit of the input buffer shown in Figure 2, Figure 7 is a schematic diagram showing another biasing circuit for an input buffer, Figure 8 is a schematic diagram showing overvoltage protection for an input buffer, Figure 9 is a schematic diagram illustrating an alternative input circuit, Figure 10 is a schematic diagram illustrating an alternative input circuit, Figure 11 is a schematic diagram illustrating a further alternative input circuit.

Throughout the description like reference numerals refer to like parts.

Figure 2 shows the control circuitry 20 according to a first embodiment of the present invention which has a biasing circuit 21 having a first and second input reference voltage VREFI, VREE.2 and which provides control signals CTRL 1 and CTRL 2 out on signal line 22 and 23 respectively. These control signals are input into a number N of input circuits 240-N each of which is connected to signal lines 22 and 23 for receiving control signals CTRL 1 and CTRL 2 for input. Each input circuit 24 also has a respective input voltage VOO-01; on respective input lines 270-N and provides a respective output voltage V10-IN in dependence on the corresponding input voltage and control signals.

Each input circuit 240-11 acts as an input buffer between an external source and internal core logic 10 of an IC and receives the respective input voltage from a respective bond pad 250-N, connected to the respective external source, and outputs a respective output voltage signal on line 26.-, to the core logic.

Figure 3 shows the circuitry of one of the input circuits 24. in more detail. It will be understood that each of the input circuits 24.-, may be constructed and arranged similarly. The input circuit has an input voltage VOO input connected via line 27 to a standard inverter 30 and a variable strength inverter 31 arranged in parallel. The output from the standard inverter 30 and the output from the variable strength inverter 31 are connected at node 32 to form the input of a second standard inverter 33, which is thus-connected in series with the pair of inverters 30, 31. The output of the -second standard inverter provides the output V, , f rom the input circuitry. The output from the variable strength inverter 31 is controlled by the control signals CTRL 1 and CTRL 2 on signal lines 22 and 23 provided by the biasing circuit 21.

Figure 4 illustrates how the voltage Vnodeat the node 32 varies as a positive-going ramp voltage V.. is applied to bond pad 25.. As the voltage V.. is initially set to zero volts the inverted output at node 32 is high and then switches from high to low as the input voltage V.. is ramped up to a high voltage.

VREF2 (not shown) corresponds to the predetermined threshold voltage at node 32 which should be set so that the output voltage V10 from the input circuit switches at a predetermined input threshold voltage VRwl. By precisely controlling this threshold VREF, to within a very small range (for example 200 millivolts) it is possible to equalise rise/fall propagation delays through the input buffer. It is the input circuity 24., and biasing circuit 21 _of the present invention which allows the control of the special voltage to be achieved. The equalisation of propagation delays allows higher data rates to be achieved.

Curve V,,din Figure 4 shows the output voltage at node 32 from the standard inverter 30 as it would be without any influence from the variable strength inverter 31. The curves 42,43 shows 6 how the variable strength inverter may af f ect the voltage output at node 32. By controlling the variable strength inverter by setting the control signals on line 22 and 23 to an appropriate level the voltage at node 32 changes from high to low at a lower (42) or higher (43) input voltage V., than it would otherwise do usi ng merely the standard inverter 30.

Hence by appropriate control of the signals on lines 22 and 23 the effective switching threshold of the input buffer may be varied around that of the standard inverter. It is therefore possible to select control s1gnalsCTRL 1 and CTRL 2 such that the input buffer switches at a predetermined input voltage level VREF1 Without the variable strength inverter variations of process, voltage and/or temperature to the input buffer would tend to result in variations voltage V,,d, at node 32.

The shape of the curves in Figure 4 indicating the response to input voltage would remain the same but the curves will be dis placed with respect to the ordinate-as shown by the arrow in Figure 4. Without control from the variable inverter 31 the result would be that the threshold voltage of the input voltage V00at which the first stage switches would not be the desired voltage but would vary according to the variations in process, voltage and/or temperature. However the control signals CTRL 1 and CTRL 2 can be set to accommodate for any such variation providing the P:N ratio may be varied so as to provide a sufficiently wide adjustment range.

Figure 5 shows the circuitry of the input circuitry 240 in still further detail which includes a modified inverter circuit forming a first stage 3 ' 7 and a standard inverter forming a second stage 38. The input vol tage VOO is connected via line 27 to the first standard inverter 30. The input voltage signal on line 27 is connected to the gate of a P-type transistor 51 which has its source connected to a supply rail voltage Vdd and its drain 7 connected to output node 52 and to the drain of an N-type transistor 53. The gate of the N-type transistor 53 is also connected to the input signal line 27. The source of the N-type transistor 53 is connected to ground. The output node 52 of the standard inverter 30 is connected via signal line 35 to node 32.

The input voltage VOO is also input on signal line 27 to the variable strength inverter 31. The input voltage signal line 27 is connected to the gate of a P-type transistor 54 which has its drain connected to node 55 and to the dra.in of an N-type transistor 56. The gatebf transistor 56 is connected to the input voltage VOO on line 27. The source of transistor 56 is connected to the drain of N-type transistor 61. The gate of transistor 61 is connected to receive control signal CTRL 2 output from the biasing circuit 21. The source of the transistor 61 is connected to ground. The source of transistor 54 is connected to the drain of a P- type transistor 57. The source of transistor 57 is connected to a high voltage Supply Vdd. The gate of transistor 57 is connected to receive control signal CTRL 1. The output node 55 of the variable strength inverter 31 is connected, via signal line 36, to node 32.

Node 32 is connected to the gate of a P-type transistor 58 of the second standard inverter 33. The source of transistor 58 is connected to a supply voltage Vdd. The drain of transistor 58 is connected to node 59 and to the drain of N-type transistor 60. The source of transistor 60 is connected to ground. The gate of transistor 60 is also connected to the node 32. The output from node 59 of the second standard inverter 33 provides the output V,, from the input circuit.

With the control signal CTRL 1 at the gate of transistor 57 and the control signal CTRL 2 set at digital levels the variable strength inverter can be made to behave like a standard inverter or can be deactivated. When CTRL 1 is low and CTRL 2 is high the variable strength inverter behaves like a standard inverter and the result is that the voltage at node 32 varies as shown by the 8 curve V..d,. in Figure 4. When CTRL 1 is high and CTRI, 2 is low the variable strength inverter is deactivated which allows the circuitry to be used in a conventional double inverter configuration. The disabling of the variable strength inverter also allows the chip to operate in a low power mode. It would also be possible to place a switch or other bypassing circuitry (not shown) in first stage 37 to bypass the effect of the variable inverter.

The control transistors 57 and 61 may be controlled by the signals CTRI, 1 and CTRL 2- to vary the t rans conductance of the pull-up P-part of the variable strength inverter 31 relative to the transconductance of the pull-down N-part of the variable strength inverter 31. By transconductance is meant the input voltage sensitivity of the output current.

As the input voltage VOO is the same for both the P and N-parts of the variable strength inverter 31, and as the current flowing through the P and N-parts must be equal this relative change in the transconductance results in a different voltage drop across the P-type transistors 54,57 from Vdd to node 55 and for the Ntype transistors 56,61 from node 55 to ground. The result is that the voltage at node 55 is controlled in accordance with the P:N ratio of trans conductance in the P and N-parts of the variable strength inverter circuitry 31.

As the P:N ratio (that is the ratio of transconductance in the P and Nparts of the variable strength inverter circuitry) of the variable strength inverter 31 and thereby the P:N ratio of the combined standard inverter 30 and variable inverter 31 is varied the voltage Vnd. at node 32 will vary as shown in Figure 4. However with the control signal CTRI, 1 and CTRL 2 set to provide a maximum P:N ratio, that is a maximum voltage sensitivity in the P-type transistors relative to the voltage sensitivity in the Ntype transistors, the voltage at V..d.. varies with respect to input voltage V.. as shown in curve P:N (max). with the control signals CTRI, 1 and CTRI, 2 set for a minimum P:N ratio the voltage 9 V,,.. varies with respect to input voltage V,, as shown in curve P:N (min) The control voltage CTRL 1 and control voltage CTRL 2 are selected by the biasing circuit 21 as described hereinafter and may be set such that the output voltage at node 32 switches from high to low at a lower or higher input voltage VREF2 than would occur using standard inverters alone. The threshold voltage VREF2 of the standard inverter 33 forming the second state 38 is the voltage at which the voltage at node 32 switches is selected to ensure that the output V,, from the input circuit 24. switches at the desired threshold voltage Vp..j.

1 Referring to Figure 6 the biasing circuitry 100 for providing the control signals CTRI, 1 and CTRL 2 used in each of the input circuits 240-5 will now be described.

The biasing circuitry 100 includes a modified inverter circuit which forms a first stage circuit 101 which is, in this implementation a replica of the first stage circuit 37 of the input stage. The first stage circuit includes a standard inverter 102 and a variable strength inverter 103 which comprises an N-type and P-type transistor 104,105 arranged together with an N-type and P-type control transistor 106,107. The transistors' dimensions are the same or similarly scaled so as to have the same P:N ratio as those of the first stage circuit 37.

It may be particularly advantageous to use physically smaller transistors in the biasing circuit 100 to enable the power loss from the circuit 100 to be minimised. This is permissible providing the P:N ratios of the transistors are maintained.

The gate of the P-type control transistor 107 of the biasing circuit 100 is connected to the control signal CTRL 1. The gate of N-type control transistor 106 is connected to the control signal CTRL 2. The output node 108 from the variable inverter 103 is connected at node 109 to the output of standard inverter 102. Node 109 is connected to a first input of a bias level controller 110 which outputs the control signals CTRL 1 and CTRL 2 via signal lines 111 and 112 respectively.

The preset voltage VREFI input at the first stage 101 of 'the biasing circuitry 100 corresponds to the desired input threshold of the input circuits and represents the voltage at which it is desired that the input circuits 240-Iq will switch. The preset voltage VREF2 input at the bias level control 110 corresponds to the desired output voltage Vmde from the first..stage 101 at the input voltage of VREF1. The bias level controller sets the control signals CTRL 1 and CTRL 2 so that the voltage at node 109 is equal to the voltage VREF2. The &.ontrol signals CTRL 1 and CTRL 2 are connected to each input circuit 240-m via respective signal lines 22 and 23. The bias level controller could be provided by a differential amplifier receiving VREF2 at its inverting input with its non-inverting input connected to node 109 and outputting a single signal for CTRL 1 and CTRL2. Since a similar variation of CTRU and CTRL2 adjusts the properties of the variable strength inverter, CTRU and CTR12 may be connected in this way.

By selecting the size (ie lengths and widths) of the transistors in the standard inverters of the modified inverter circuits of both the input circuits and biasing circuit the effects of the standard inverters can be set as dominant. This allows the input buffer to be better controlled with respect to variations in the control signals CTRLI and CTRL2.

According to a second embodiment of the present invention the biasing circuit shown in Figure 7 may be used to provide the control signals.CTRL 1 and CTRL 2 utilised by each of the input circuits 240-m.

The biasing circuitry 120 includes a modified inverter circuit which forms a first stage 121 which is a replica of the first stage circuit 37 of the input stage in terms of transistor device width and lengths. The first stage includes a standard inverter 11 122 and a variable strength inverter 123 which comprises an N type and P- type transistor 124,125 arranged conventionally as an inverter, but with an N-type control transistor 126 between the source of transistor 124 and ground and a P-type control transistor 127 between the source of transistor 125 and a high voltage source Vdd Again a scaled replica stage may be used advantageously to reduce power consumption, provided the P:N ratios are maintained.

The output of standard inv!rter 122 Is connected to node 129 and node 128 between the drain of transistor 125 and drain of transistor 124. The gate of P-type transistor 127 and N-type transistor 126 are connected to the output node 130 of the first stage 121. The node 130 is also connected to node 129. The voltage at node 130 forms the control voltages CTRL 1 and CTRL 2 where CTRL 1 is equal to CTRL 2. This circuit stabilises when CTRL1 and CTRL2 reach an intermediate voltage level equal to the output of the first stage circuit for an input voltage VREFI.Since it is a characteristic of the first stage circuit to switch its output very sharply between a high voltage level and a low voltage level, this arrangement ensures that CTRU and CTRL2 are set such that the first stage circuit is switching between the high and low levels at input voltage VREF1' The biasing circuitry 120 provides a relatively simple circuit for providing the control signals used in the input circuits 24.

Figure 8 illustrates how the first stage 87 of the input circuitry 240-N may be modified to provide over-voltage tolerance in accordance with a third embodiment of the present invention.

As shown the input circuitry 240 includes a first stage 87 and a second stage 88. The input voltage VOO is connected to the drain of N-type transistor 90. The gate of the transistor 90 is connected to a high voltage source Vdd and the source of the transistor 90 is connected via line 91 to the first standard 12 inverter 92 which includes P-type transistor 93 and N-type transistor 94 connected in a conventional inverter configuration. The source of transistor 93 is connected to the drain of P-type transistor 95. The source of transistor 95 is connected to a high voltage supply Vdd. The gate of transistor 95 is connected to the input voltage VOO via line 96 which is also connected to the gate of P-type transistor 97.

The input voltage from line 91 is also connected to the gate of P-type transistor 101 and N-type transistor 100 of the variable inverter 98. The two transistors 100,101 are connected in the manner of a conventional inverter. The source of transistor 100 is connected to the drain of Ntype transistor 99. The source of transistor 99 is connected to ground and the gate of the transistor 99 is connected to a control signal CTRL 2 from the biasing circuit.

The source of transistor 101 is connected to the drain of a Ptype transistor 97. The gate of the transistor 97 is connected via line 96 to the input voltage. The source of transistor 97 is connected to the drain of a P-type transistor 102, the gate of which is connected to a control signal CTRL 1 from the biasing circuit. The source of transistor 102 is connected to a high voltage source Vdd.

The output node 103 from the standard inverter 92 is connected to output node 104 from the variable strength inverter 98. The output from the first stage is connected to the second stage 88 of the input circuitry which includes a standard inverter 105.

As will be understood the input circuitry shown in Figure 8 corresponds to the input circuitry shown in Figure 5 except for the addition of the three overvoltage control transistors 90,95 and 97. These operate to limit the voltage input via line 91 to ensure damage does not occur to the circuitry.

It will likewise be understood that similar overvoltage control 13 transistors could be added to the biasing circuitry to ensure damage does not occur.

Figure 9 shows an alternative input circuit 24 in accordance with a fourth embodiment of the present invention. As shown the modified inverter circuit which forms the first stage 120 of the input circuit has been modified by omitting one of the control transistors from the variable strength inverter 121 which includes a P-type transistor 122 and N-type transistor 123 connected in a conventional inverter manner. The source of the P-type transistor 122 is dorinected.to the drain of the control transistor 124. The source of the control transistor 124 is connected to a high voltage Supply Vdd. The gate of the control transistor is connected to receive a control signal CTRL 1 from the biasing circuit.

The biasing circuit 21 used in conjunction with the modified input circuit 24 configured as shown in Figure 8 may likewise be configured as the first stage 120 as there is no requirement to generate a second control signal CTRL 2.

Although the trans conductance ratio of the P-type portion of the variable strength inverter to the N-type portion (the P:N ratio) can be varied in this way by varying control signal CTRL 1 the N-type transistor is invariable and the ratio may therefore only be decreased. The N-type transistor 123 must therefore be carefully preselected to ensure that the range within which the operating ratios may be varied is set to provide the desired control.

It will also be understood that rather than omitting the N-type transistor from the variable transistor the P-type transistor could be omitted in which case an N-type control transistor may be used to vary the P:N ratio of the modified inverter circuit. A biasing circuit could likewise be provided to provide a control signal CTRL 2 for input circuits modified in that manner.

14 Figure 10 shows an alternative of the modified inverter circuit 150 in accordance with a fifth embodiment of the present invention which provides a lower capacitance advantage at the output compared to the embodiments of the modified inverter circuits described hereinabove. It will be understood that the circuit 150 could be used in any of the input circuits 24 and/or biasing circuit 21 as described herein.

The input to the modified inverter circuit 150 is connected via line 149 to the gates of P-type transisto3. 151 and N-type transistor 152 which are'"arranged in a conventional inverter configuration with the drains of transistors 151 and 152 connected together at output 'node 160. The source of the transistor 151 is connected to the drain of P-type pull-up transistor 153 and to node 154. The gate of pull-up transistor 153 is connected to ground. The source of transistor 153 is connected to a high voltage Supply Vdd such as a supply rail. Node 154 is connected to the drain of a P-type transistor 155. The gate of this transistor 155 is connected to receive the control signal CTRL1. The source of the transistor 155 is also connected to the high voltage supply Vdd.

The source of N-type transistor 152 is connected to node 156 and to the drain of N-type pull-down transistor 157 which has its gate connected to a high voltage supply Vdd. The source of the pull-down transistor 157 is connected to ground. Node 156 is connected to the drain of N-type transistor 1.58 which has its gate connected to receive the control signal CTRL 2. The source of transistor 158 is connected to ground. The output at the output node 164 forms the output of the modified inverter circuit 150.

By varying the control signals CTRL 1 and CTRL 2 the ratio of the transconductance in the P-type portion of the modified inverter circuit to the N-type portion (the P:N ratio) may be varied. As the input voltage of both P and N-type parts is commonly determined on line 149 and since the current through the P and N-parts is equal the variation in the P:N ratio results in a different voltage from Vdd to node 160 and from node 160 to ground. In this way the output of each input circuit having such a modified inverter circuit 150 followed in series by a standard inverter may be precisely controlled to switch at a predetermined threshold input voltage VREFI Figure 11 shows an alternative modified inverter circuit 170 in accordance with a sixth embodiment of the present invention. The modified inverter circuit is similar to that shown in Figure 10 as described hereinabove -but is further adapted to allow for digital signal rather than an analogue signal control.

I The input to the modified inverter 170 is connected via line 179 to the gates of P-type transistor 180 and N-type transistor 181 which are arranged in a conventional inverter configuration with the drains of the transistors 180 and 181 connected together at an output node 182. The source of the transistor 180 is connected to the drain of the P-type transistor 183 and to node 184. The gate of transistor 183 is connected to ground. The source of transistor 183 is connected to a high voltage supply such as a supply rail. Node 184 is connected to the drain of a number M of P-type control transistors 1850-m. The source of each of the control transistors 1850-m is connected to a high voltage Supply Vdd. The gate of each of. the control transistors 1850-m is connected to a respective input node 1860-m each of which receives a respective input control signal from a biasing circuit.

The digital control signals at nodes 1860-m can be generated using, for example, the combination of the previously described bias generation circuit, with the analogue output voltage (assuming CTRL 1 equals CTRL 2) being converted into a series of digital control outputs via a ADC(analogue to digital converter) such as a potential-dividing ladder circuit.

The N-type portion of the modified inverter circuit 170 is configured similarly. The source of N-type transistor 181 is 16 connected to node 187 and to the drain of N-type transistor 188. The gate of transistor 188 is connected to a high voltage supply Vdd. The source of the transistor 188 is connected to ground.

Node 187 is connected to the drain of a number L of N-type control transistors 1890-L The source of each of the control transistors 1890-L 'S connected to ground. The gate of each of the control transistors 1890- L 'S connected to a respective input node 1900-L each of which receives a respective input control signal from a biasing circuit.

By providing digital rather than analogue control of the control transistors improved control of the input voltage threshold may be achieved as noise effects are effectively eliminated from the control signal.

The present invention may include any feature or combination of features disclosed herein either implicitly or explicitly or any generalisation thereof, irrespective of whether it relates to the pre. sent claimed invention. In particular the"standard inverter" of the first stage of the input circuits or biasing circuits described hereinabove may be removed without losing many of the benefits described.

In view of the foregoing description it will be evident to a person skilled in the art that various modifications may be made within the scope of the invention.

17

Claims

CLAIMS:

1. Biasing circuitry comprising: a controllable inverter including at least one control element for varying the response of the controllable inverter to a first reference voltage; wherein the ouput of said controllable inverter provides a control signal for each said at least one control element; and wherein each said control signal provides a biasing signal.

2. Biasing circuitry abc6rding to claim 1, wherein said controllable inverter further comprises: a first branch and a seCond branch for cooperatively generating an output signal at the output node, each branch being connected to a first input node to receive the first reference voltage; wherein at least one of the branches includes a control element for controlling the relative voltage sensitivity of the first and second branches thereby controlling the response of the controllable inverter to the reference voltage.

3. Biasing circuitry according to claim 2, wherein the relative transconductance of the first and second branches is variable in respect to each said control signal.

4. Biasing circuitry according to claim 2 or 3, wherein said first branch is connected between a first voltage supply and the output node; and said second branch is connected between said output node and a second lower voltage supply.

5. Biasing circuitry according to claim 2 or 3 to 4 when dependent upon claim 2, wherein said first branch comprises at least one P-type branch transistor and said second branch comprises at least one N-type branch transistor.

6. Biasing circuitry according to claim 2 or 3 to 5 when 18 dependent upon claim 2, wherein each branch comprises at least one control element for controlling the voltage sensitivity of the respective branch.

7. Biasing circuitry according to claim 6 wherein the output of said controllable inverter provides the control signal for said control element in each branch.

8. Biasing circuitry according to claim 6 wherein said at least one control element in said first branch comprises a P-type control transistor.

9. Biasing circuitry according'to claim 6 wherein said at least one control element in said second branch comprises an N-type control transistor.

10. Biasing circuitry according to claim 8 or 9, wherein the relative voltage sensitivity of the first and second branches is controlled by setting the gate voltage of each of said control transistors.

11. Biasing circuitry according to claim 5 or 6 to 10 when dependent upon claim 5, wherein the gates of said at least one P-type branch transistor and said at least one N-type branch transistor are connected together and to said first input node.

12. Biasing circuitry according to claim 11 wherein the drain of said at least one P-type branch transistor is connected to the drain of said at least one N-type branch transistor and to said output node.

13. Biasing circuitry according to claim 11 or 12, wherein said first branch includes said at least one control element comprising a P-type control transistor; wherein the source of said P-type control transistor is connected to a first voltage supply; the gate of said P-type control transistor is connected to 19 receive the output of said controllable Inverter; and the drain of said P- type control transistor is connected to the source of said at least one P- type branch transistor.

14. Biasing circuitry according to claims 11 to 13, wherein said second branch includes at least one control element comprising an N-type control transistor; wherein the source of said N-type control transistor is connected to a second lower voltage supply; the gate of said N-type control transisto.r is connected to receive the output of said controllable inverter; and the drain of said N-type control transistor is connected to the source of said at least one i-type branch transistor.

15. Biasing circuitry according to any one of the preceding claims further comprising a first inverter connected in parallel with said controllable inverter between a first input node and an output node.

16. Biasing circuitry according to claim 15, wherein said at least one control element may be set to disable the controllable inverter.

17. Biasing circuitry according to any one of the preceding claims for providing biasing signals for an input buffer, wherein each said biasing signal is connected to bias a respective control element in an associated input circuit of said input buffer.

18. Biasing circuitry according to claim 17 wherein said biasing signals are connected to more than one input buffer.

19. Biasing circuitry according to claim 17, wherein the relative t rans conductance of the first and second branches in said controllable inverter matches the relative transconductance of the first and second branches of a controllable inverter in the input Circuits of said input buffer.

20. Biasing circuitry constructed and arranged substantially as herein described with reference to or as shown in Figures 2 to 11.

Amendments to the claims have been filed as follows 1. Biasing circuitry comprising: a controllable inverter including at least one control element arranged to receive a digital control signal for varying the response of the controllable inverter to a first reference voltage; wherein the ouput of said controllable inverter provides a control signal for each said at least one control element; and wherein each said control signal provides a biasing signal.

2. Biasing circuitry according to claim 1, wherein said controllable inverter further comprises: a first branch and a second branch for cooperatively generating an output signal at the output node, each branch being connected to a first input node to receive the first reference voltage; wherein at least one of the branches includes a control element for controlling the relative voltage sensitivity of the first and second branches thereby controlling the response of the controllable inverter to the reference voltage.

_)J_ dependent upon claim 2, wherein each branch comprises at least one control element for controlling the voltage sensitivity of the respective branch.

9. Biasing circuitry according'to claim 6 wherein said at least one control element in said second branch comprises an Ntype control transistor.

13. Biasing circuitry according to claim 11 or 12, wherein said first branch includes said at least one control element comprising a P-type control transistor; wherein the source of said P-type control transistor is connected to a first voltage supply; the gate of said P-type control transistor is connected to receive the output of said controllable inverter; and the drain of said P- type control transistor is connected to the source of said at least one P- type branch transistor.

14. Biasing circuitry according to claims 11 to 13, wherein said second branch includes at least one control element comprising an N-type control transistor; wherein the source of said N-type control transistor is connected to a second lower voltage supply; the gate of said Ntype control transisto.r is connected to receive the output of said controllable inverter; and the drain of said N-type control transistor is connected to the source of said at least one N-type branch transistor.