GB2340679A

GB2340679A - Frequency synthesizer

Info

Publication number: GB2340679A
Application number: GB9817908A
Authority: GB
Inventors: Robert Owen Bristow
Original assignee: Telefonaktiebolaget LM Ericsson AB
Current assignee: Telefonaktiebolaget LM Ericsson AB
Priority date: 1998-08-17
Filing date: 1998-08-17
Publication date: 2000-02-23
Anticipated expiration: 2018-08-17
Also published as: GB2340679B; GB9817908D0

Abstract

A frequency synthesizer comprises first and second phase locked loop (PLL) circuits 10 and 11 for generating two frequencies simultaneously, for example the receiver and transmitter frequencies 12 and 13 of a mobile phone. In order to generate frequencies which are non-integer divisors of a reference frequency 7, the dividing value sent to divider circuits 2a and 2b in each PLL is perturbed in such a way to make the dividing value settle to a desired point between two adjacent integers. Instead of having two complex controllers, ie. one for supplying dividing values to each of the two PLL circuits 10 and 11, a common controller 15 supplies dividing values to both. Dividing values can either be sent alternately to each PLL 10 and 11, or as alternate bursts of values to each PLL 10 and 11. The common controller 15 may also be shared between more than two PLL circuits for generating more than two frequencies simultaneously.

Description

FREQUENCY SYNTHESIS

FIELD OF THE INVENTION

The present invention relates to a frequency synthesizer for providing two separate frequency signals simultaneously, in particular, the transmit and receive frequency signals for a mobile radio system.

BACKGROUND TO THE INVENTIO

Figure 1 shows a typical frequency synthesizer according to the prior art. The output frequency of a voltage controlled oscillator 1 is set using a phase error loop, commonly called a phase locked loop (PLL).

In such a loop, an error signal 6 is derived in a phase comparator 3 by comparing a frequency reference 7 with a divided version 8 of the voltage controlled oscillator frequency 9. The error signal is then passed through a loop filter 4 and returned to the input of the WO 1 for control thereof. A drawback of this technique is that the divider 2 can only be set to divide by integers N, and this limits the frequency resolution that is possible.

In a known improvement shown in figure 2, the divisor value N, used by the divider 2, is perturbed by a controller 5 in such a way as to make the average value of the divisor settle to a desired point between two adjacent integers. Such an improvement forms a fractional synthesizer which overcomes the resolution restriction.

The controller 5 required to perform the perturbation may be quite complex, especially if high resolution and freedom from spurious signals is to be guaranteed. A frequency synthesizer of this type is -2 described in US-5,079,521, for example.

Many radio systems need to transmit and receive simultaneously on different RF channels. This leads to the need for two RF sources, one to act as the transmitter carrier signal, the other as the receiver local oscillator. In some systems there is no simple relationship between these two required frequencies, leading to complicated and extensive circuitry. In such systems requiring two separate frequencies, two fractional PLL circuits as described above are needed.

This in turn means that two complex controllers are needed.

is The aim of the present invention is to remove the need for two complex controllers by sharing a single controller between two or more PLL circuits.

SUMMARY OF THE INVENTIO

According to a first aspect of the invention, there is provided a frequency synthesizer for generating two separate frecluencies simultaneously, comprising; a first phase locked loop circuit for generating a first frequency, having a first divider circuit which receives a first dividing value; a second phase locked loop circuit for generating a second frequency, having a second divider circuit which receives a second dividing value; characterised in that a common controller is provided for supplying the first and second dividing values in turn to each of the divider circuits.

According to a second aspect of the invention, there is provided a method of providing two frequencies simultaneously in a frequency synthesizer comprised of two phase locked loop circuits for generating the two frequencies, each phase locked loop circuit having a divider circuit for receiving first and second dividing values respectively, the method comprising the steps of sending the first and second dividing values in turn to each of the divider circuits from a common controller.

BRIEF DESCRIPTION OF THE DRAWINGS

For a better understanding of the present invention, and to show more clearly how it may be carried into effect, reference will now be made, by way of example, to the accompanying drawings, in which:

Figure 1 is a block diagram showing a frequency synthesizer according to the prior art; is Figure 2 is block diagram showing another frequency synthesizer according to the prior art;

Figure 3 is a block diagram showing a frequency synthesizer according to a preferred embodiment of the present invention.

Figure 4 is a flow chart showing the operation of the invention in a first mode.

Figure 5 is a flow chart showing the operation of the invention in a second mode.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Figure 3 shows a frequency synthesizer according to the preferred embodiment of the present invention.

A first phase locked loop circuit 10 comprises a voltage controlled oscillator la, the output frequency of which is fed to a divide by N circuit 2a. A phase comparator 3a compares the phase difference between the output Sa. of the divide by N circuit 2a and a reference frequency 7. The output voltage 6a from the phase comparator is fed back through a low pass filter 4a to the input of the voltage controlled oscillator la, thereby creating the phase locked loop.

The output 9a of the voltage controlled oscillator la provides the frequency for a receiver 13, which is connected to a combined antenna 14.

A second phase locked loop circuit 11, comprises a voltage controlled oscillator 1b, the output frequency of which is fed to a divide by N circuit 2b. A phase comparator 3b compares the phase difference between the output 8b of the divide by N circuit 2b and the reference frequency 7. (An alternative would be to supply a different reference frequency to the second PLL 11). The output voltage 6b f rom the phase comparator is fed back through a low pass filter 4b to the input of the voltage controlled oscillator 1b, thereby creating the phase locked loop.

The output 9b of the voltage controlled oscillator lb provides the frequency for a transmitter 12, which is also connected to the combined antenna 14.

In order to increase the resolution of the two frequencies 9a and 9b so that they are not constrained to being integer fractions of the reference frequency, a common controller 15 provides divider values to each of the divide by N circuits 2a and 2b in turn.

The divider circuits 2a, 2b each receive a number (the division ratio) from the controller 15, and either count upwards until that number is reached, or count downwards from that number until zero is reached. At the end point, a pulse is sent to the phase comparator 3a, 3b. In either case, the number is stored and re used until a different number is received.

Another possibility is to allow sharing of the common controller 15 relying on the action of the loop filters 4a and 4b in the PLL circuits 10 and 11. In line with control loop theory, each filter 4a and 4b will normally have an integrator. These can be designed such that, if either phase comparator 3a or 3b is disabled, the output of the associated integrator remains constant until internal offsets and drifts start to affect it.

When the controller 15 is supplying a divider value to the divide by N circuit 2a in PLL circuit 10, the output of the phase comparator 3b in PLL 11 is disabled. During this time, the input voltage to the voltage controlled oscillator ib is maintained by the is integrating effect of filter 4b.

When the controller 15 switches to supply a divider value to the divide by N circuit 2b in PLL 11, the output of the phase comparator 3a is disabled in PLL 10. During this time, the input voltage to voltage controlled oscillator la is maintained by the integrating effect of filter 4a.

Therefore, due to the integrating effect, the filters 4a and 4b act as forms of memory which enable the controller 15 to be temporarily removed from one PLL circuit 10 and connected to the other PLL circuit 11, and vice versa.

The controller 15 may be arranged either to send alternate divider ratios to each PLL 10 and 11, or a burst of ratios to one PLL alternately with the other, or any combination of these. A description of these two modes of operation will be given below on the assumption that the two required frequencies are F. and FEI, and that two divider ratios A, and A2 in a f irst sequence are required to generate F,, and two divider ratios B, and B2 in a second sequence are required to generate FB. The following description further assumes that the first and second sequences are only two digits long. That is, the first sequence is A,, A2s A,, and the second sequence is B,, B2, B,, Figure 4 shows the operation of the controller in the first mode in which divider ratios are sent in turn to each PLL 10 and 11. According to this mode of operation, the controller supplies divider value A, to the first PLL circuit (step S1), switches to supply B, to-the second PLL circuit (step S2), switches to supply A2 to the first PLL circuit (step S3), switches to Supply B2 to the second PLL circuit (step S4), then repeats the sequence starting from step S1.

Figure 5 shows the operation of the controller in the second mode in which bursts of divider ratios are sent in turn to each PLL 10 and 11. According to this second mode of operation, the controller supplies divider value A, to the first PLL circuit (step S1), followed by A2 to the same PLL circuit (step S2), then switches to supply B, followed by B. to the second PLL circuit (steps S3 and S4), and so on.

The example described above is based on the simple case of needing a sequence of only two divider ratios to obtain the required fractional average division ratio for each frequency. However, the invention may equally be used in systems using longer sequences for achieving the desired frequencies, for example, using 64 bit sequences. In the case of the first mode shown in Figure 4, this only requires the relevant numbers from the two sequences to be sent alternately to the relevant dividers. However, the extent to which these sequences may be sent in bursts, as shown in Figure 5, will depend on the degree to which the loop bandwidth of each PLL can be reduced, because this will rely on the phase comparators remaining at the correct frequency when no signal is being supplied. This in turn will depend upon how much the ppm frequency accuracy can be reduced for a particular application.

Although the preferred embodiment has been described in a system which generates only two frequencies simultaneously, the invention may also be applied to systems which generate more than two is frequencies. The sharing of the controller 15 in this manner is achieved by changing the integrating factor of each loop depending upon the number of PLL circuits which are sharing the controller 15.

There is therefore provided a frequency synthesiser which allows the use of a common controller for two fractional-N dividers.

9 -a

Claims

1. A frequency synthesizer for generating two separate frequencies simultaneously, comprising; a first phase locked loop circuit for generating a first frequency, having a first divider circuit which receives a first dividing value; a second phase locked loop circuit for generating a second frequency, having a second divider circuit which receives a second dividing value; characterised in that a common controller is provided for supplying the first and second dividing values in turn to each of the divider circuits.

is

2. A frequency synthesizer as claimed in claim 1 wherein the controller sends divide.r values alternately to each phase locked loop.

3. A frequency synthesizer as claimed in claim 1 wherein the controller sends a burst of divider values alternately to each phase locked loop.

4. A frequency synthesizer as claimed in claim i wherein the controller sends a combination of individual divider values and bursts of divider values alternately to each phase locked loop.

5. A method of providing two frequencies simultaneously in a frequency synthesizer comprised of two phase locked loops circuits for generating the two frequencies, each phase locked loop circuit having a divider circuit for receiving first and second dividing values respectively, the method comprising the steps of sending the first and second dividing values in turn to each of the divider circuits from a common controller.

6. A method as claimed in claim 5 wherein divider values are sent alternately to each phase locked loop.

7. A method as claimed in claim 5 wherein bursts of divider values are sent alternately to each phase locked loop.

8. A method as claimed in claim 5 wherein a 10 combination of individual divider values and bursts of divider values are sent alternately to each phase locked loop circuit.

9. ' A method according to any of claims 5 to 8 wherein 15 the two frequencies comprise the transmit and receive frequencies in a radio communications system.

10. A frequency synthesizer substantially as hereinbefore described with reference to, and as shown 20 in, Figure 3 of the drawings.

11. A method of providing two frequencies simultaneously, substantially as hereinbefore described with reference to, and as shown in, Figure 4 or Figure 25 5 of the drawings.

12. A radio communication system having a frequency synthesizer as claimed in any of claims 1 to 4 wherein the first and second frequencies are transmit and 30 receive frequencies of the radio communication system.