GB2335555A

GB2335555A - Phase locked loop oscillator circuit

Info

Publication number: GB2335555A
Application number: GB9805847A
Authority: GB
Inventors: Anthony David Newton; Hans Staufer
Original assignee: Motorola Inc
Current assignee: Motorola Solutions Inc
Priority date: 1998-03-20
Filing date: 1998-03-20
Publication date: 1999-09-22
Also published as: GB9805847D0

Abstract

A phase locked loop includes a ring oscillator as a voltage controlled oscillator. This oscillator has a frequency control input 50, a common frequency output 60 and a number of stages 10, 20 and 30 operating in sequence and having a fundamental frequency of operation. Each of the stages includes a pull-down transistor 12, 22 or 32 connected as a cascode and supplying charging current to pull-down transistors 14, 24 or 34 arranged as a capacitor. The cascodes conduct in sequence and by adding their currents together at a summing resistor 40, a current is derived at 60 which fluctuates at three times the fundamental frequency. A prescaler (fig.2 not shown) also forming part of the phase locked loop including the ring oscillator is supplied with the fundamental frequency derived at terminal 38 instead of the higher frequency at output 60 and the power consumption of the loop is reduced. The phase locked loop may form part of a frequency synthesiser used in mobile telephones.

Description

2335555 PHASE MCKED IP 0SCRXATOR CHICM

Field of the Invention

This invention relates to phase locked loop oscillator circuits, and particularly but not exclusively to phase locked loop oscillator circuits for frequency synthesiser applications.

Backoround of the Invention In many portable devices, such as mobile telephones, increasing attempts are being made to reduce the power consumption of the devices.

Phase locked loop oscillator circuits are typically used in frequency synthesiser applications and other electronic applications to generate a reference signal for use in the application.

Very high frequency phase locked loop oscillator circuits are often required in order to generate fast reference signal speeds. However, a problem with these arrangements is that the power consumed by a phase locked loop oscillator circuit increases tremendously with increasing frequency.

In particular, typical phase locked loop oscillator circuits include a prescaler stage which operates at a high toggle rate, thereby resulting in relatively large power consumption.

What is needed is an improved phase locked loop oscillator circuit, having reduced power consumption at high-frequencies.

This invention seeks to provide a phase locked loop oscillator circuit which mitigates the above mentioned disadvantages.

Summary of the Invention

According to the present invention there is provided a phase locked loop oscillator circuit comprising: a ring oscillator having a common input, a common output and a plurality of stages each having an output; and, a prescaler coupled to receive the output from one of the plurality of stages, an operating frequency of the prescaler being determined by the output from the one of the plurality of stages, the prescaler being arranged to provide a prescaled output from which the common input signal to the ring oscillator is derived, wherein the common output is a sum of the outputs of each of the plurality of stages, such that the frequency of the common output is substantially higher than the operating frequency of the prescaler.

In this way an improved phase locked loop oscillator circuit is provided, having reduced power consumption at high-frequencies.

Brief Description of the Drawings

An exemplary embodiment of the invention will now be described with reference to the drawing in which:

FIG. 1 shows a preferred embodiment of a ring oscillator in accordance with the invention.

FIG. 2 shows a phase locked loop oscillator circuit incorporating the ring oscillator of FIG. 1.

Detailed Description of a Preferred Embodiment

Referring to FIG. 1, there is shown a ring oscillator 5, comprising first, second and third ring stages 10, 20 and 30 respectively, a silmming resistor 40, a frequency control input 50 which drives an emitter follower transistor 35 55, and a common output 60.

The first ring stage 10 comprises a first pull-down transistor 12, a second pull-down transistor 14 and a first stage load resistor 16.

The first pull-down transistor 12 is arranged as a cascode, and has a collector terminal coupled to the common output 60, a base terminal coupled to a node 51 and an emitter terminal to be further described below. The node 51 is coupled to the common input 50 via a resistor 52, and is further coupled to ground via two diodes 56 and 57 respectively. In this way the node 51 is biased by the two diodes 56 and 57 respectively.

The second pull-down transistor 14 is arranged as a capacitor, and has a collector terminal having three connections. The first connection is to the emitter terminal of the first pull-down transistor 12. The second connection is to the common input 50 via the DC bias transistor 55 and the first stage load resistor 16. The third connection is to the second transistor stage 20, to be further described below. In this way the load seen by the collector terminal of the second pull-down transistor 14 is the sum of the emitter terminal impedance of the first pull-down transistor 12 and the first stage load resistor 16. The second pull-down transistor 14 also has a base terminal to be further described below, and an emitter terminal coupled to ground. The second pull-down transistor 14 may be formed as a parasitic capacitance.

The second ring stage 20 comprises a third pull-down transistor 22, a fourth pull-down transistor 24 and a second stage load resistor 26, in a similar configuration to that of the first ring stage 10, with two exceptions: the third connection of the collector of the fourth pull-down transistor 24 is to the third ring stage 30, and the base terminal of the fourth pull-down transistor 24 is connected to the collector of the second pull-down transistor 14 (the third connection mentioned in the paragraph above).

Similarly the third ring stage 30 comprises a fifth pull-down transistor 32, a sixth pull-down transistor 34 and a third stage load resistor 36, in a similar configuration to that of the first and second ring stages 10 and 20, with two exceptions: the third connection of the collector of the sixth pull-down transistor 34 is to the base terminal of the second pull-down transistor 14 (marked as path 35), and the base terminal of the sixth pull-down transistor 34 is connected to the collector of the fourth pull-down transistor 24.

In this way the first, second and third ring stages 10, 20 and 30 respectively form the ring oscillator 5. The 'ring' is formed by the base and collector terminals of the second, fourth and sixth pull-down transistors 14, 24 and 34 respectively, which are interconnected as described above.

The collector terminal of the sixth pull-down transistor 34 (coupled to the 10 path 35) is also coupled to an output 38, to be further described below.

In operation, the first, second and third stage load resistors 14, 24 and 34 respectively are driven by the frequency control input 50 via the emitter follower transistor 55. A voltage V applied to the load resistors 14, 24 and 34 respectively defines a charging current I to the capacitors formed by the second, fourth and sixth pull-down transistors 14, 24 and 34 respectively. The voltage swing of these capacitors is essentially constant, and therefore increasing the charging current serves to increase the oscillation frequency of the capacitors.

The collectors of the first, third and fifth pull-down transistors respectively (the cascodes) feed the summing resistor 40. Since the three cascodes conduct in sequence to give a fundamental frequency, by adding their respective currents together, a current is derived that fluctuates at three times the fundamental frequency. Hence across the summing resistor 40 (and therefore at the common output 60) there is a signal having a frequency of substantially three times the fundamental frequency.

In this way the ring oscillator 5 provides the desired frequency at the common output 60, while the phase locked loop 100 operates at one third of this frequency, thereby reducing power consumption.

Referring now also to FIG. 2, there is shown a phase locked loop oscillator circuit 100, incorporating the ring oscillator 5, a prescaler 110, a phase detector 120, a reference oscillator 130 and a filter 140.

The output 38 of the ring oscillator 5 is coupled to an input of the prescaler 110. An output of the prescaler 110 is coupled to the phase detector 120, which also receives a reference input from the reference oscillator 130.

An output of the phase detector 120 is coupled via the filter 140 to common input 50 of the ring oscillator 5.

The output 38 contains the fundamental frequency, and therefore the phase locked loop oscillator circuit 100, including the prescaler 110, operates at this fundamental frequency. However, the output 60 of the ring oscillator has a frequency of substantially three times the fundamental frequency. In this way a large saving in power is achieved, by not operating the entire phase locked loop oscillator circuit 100 (and in particular the prescaler 110) at the frequency of the output 60, but at approximately one third of this frequency.

It will be appreciated that alternative embodiments to the one described above are possible. For example, the three ring stages 10, 20 and 30 mentioned above could be replaced with an alternate number of stages, which is preferably an odd number.

Furthermore, the precise configuration of the circuit 100 may vary from that disclosed above.

Claims

1. A phase locked loop oscillator circuit, comprising:

a ring oscillator having a common input, a common output and a plurality of stages each having an output; and, a prescaler coupled to receive the output from one of the plurality of stages, an operating frequency of the prescaler being determined by the output from the one of the plurality of stages, the prescaler being arranged to provide a prescaled output from which the common input signal to the ring oscillator is derived, wherein the common output is a sum of the outputs of each of the plurality of stages, such that the frequency of the common output is substantially higher than the operating frequency of the prescaler.

2. The phase locked loop oscillator of claim 1 wherein the plurality of stages of the ring oscillator comprises an odd number of stages.

3. The phase locked loop oscillator of claim 1 wherein the plurality of stages of the ring oscillator comprises 3 stages.

4. The phase locked loop oscillator of claim 1 or claim 2 wherein each of the plurality of stages includes a pull-down transistor in a cascode configuration.

5. The phase locked loop oscillator of any preceding claim wherein each of the plurality of stages includes a parasitic capacitor.

6. A phase locked loop oscillator circuit substantially as hereinbefore described and with reference to the drawings.