GB2333912A - Universal switching power supply - Google Patents

Abstract

A switching power supply for generating one or more output voltage levels wherein the power supply is operable over a range of AC and DC input supply voltages. The switching power supply comprises an input stage 103, a start-up stage 104, a first stage 101, and a second stage 102. The first stage energizes the second stage, and the second stage includes output circuits for generating one or more output voltage levels. The second stage also includes a transformer for isolating the first stage. Detailed circuits of the stages are described (Figs 3 and 4).

Description

UNIVERSAL SWITCHING POWER SUPPLY DESCRIPTION FIELD OF TB INVENTION The present invention relates to power supplies and more particularly to a switching power supply capable of accepting a range of input voltages.

BACKGROUND OF TEE tNVZNTIOW Power supplies in one form or another are found in most electrical and electronic equipment. Power supplies fall into two general categories: AC (alternating current) and DC (direct current) supplies. The prevalence of an AC mains supply means that most power supplies utilize an AC voltage as the input voltage which is converted to DC level or other AC level outputs. The output characteristics of the supply are determined by the particular requirements of the electrical/electronic apparatus coupled to the power supply.

While an AC mains supply is typically utilized to energize the power supply, there are many applications where a supply voltage other than the standard 120 VAC will be available. The primary power source may comprise a nonstandard AC supply voltage, for example anywhere in the range 9 to 250 VAC at 40 to 70 Hertz. In other applications, the equipment may be run on a battery and the primary supply voltage will comprise a DC voltage, for example in the range 9 to 250 VDC. In order to function properly and avoid damage, the power supply must be matched to the available supply voltage. As a result a particular piece of electronic equipment will need more than one power supply to accommodate the various supply or mains voltages, for example electronic equipment for North America will require 110 VAC, whereas equipment for Europe will require 220 VAC. It will be appreciated that this increases the component costs for the equipment as well as manufacturing costs.

One solution has been to provide the power supply with a multiple tap transformer. The power supply is configured for the supply voltage by selecting the appropriate tap for the input voltage. Typically, the power supply is configured at the user end. It will be appreciated that this complicates the set-up procedure and underlies the need to carefully follow the user manual. To facilitate set-up, some power supplies include a transformer coupled to a rotative switch for selecting the correct taps and configuring the power supply for the required primary voltage. While such an arrangement makes it easier for user to configure the power supply for the mains supply, an erroneous setting, for example 220 VAC instead of 110 VAC, can damage the equipment.

Accordingly, there remains a need for a universal power supply capable of operating on a wide range of input voltages preferably in both AC and DC. Moreover, such a power supply should be "quiet" so as not to create interference with the electronic equipment connected to the power supply.

BRIEF SUMMARY OF THE INVENTION The present invention provides a universal switching power supply capable of operating over a range of input AC voltages in the range 9 to 250VAC at 40 to 70 Hertz and over a range of input DC voltages in the range 9 to 250 VDC. In one embodiment, the power supply provides +15V, -15V and +30 V rail outputs with a common ground and +1SV and -15V rail outputs with another common ground isolated for 250VAC. The rails are isolated from the high voltage.

According to the invention, the AC input voltage from the mains supply is rectified and filtered to provide a high voltage output rail. The power supply according to the present invention features a dual stage arrangement.

The first stage comprises a buck converter, whereas the second stage comprises a full-bridge converter.

Advantageously, the first stage generates a fixed voltage with good efficiency as long as the input supply high voltage is higher or equal than the desired low voltage output level. The second stage generates a fixed voltage level efficiently and with good isolation characteristics provided the input supply voltage remains relatively constant. According to this aspect of the invention, the first stage provides a stable input supply voltage which enables the second stage to generate constant output voltage levels, while maintaining isolation between the outputs of the power supply and the input voltage supply.

Advantageously, the generation of high frequency "spikes" in the two stages is minimized. Spikes in a power supply affect the efficiency by creating heat when the high frequency spikes are absorbed and not passed by the transformer to the output.

In one aspect, the present invention provides a switching power supply for generating one or more output voltage levels, said switching power supply comprising: (a) an input stage having means for receiving a supply voltage and means for converting said supply voltage to a DC level; (b) a first stage coupled to said input stage for receiving said DC level and said first stage having means for producing an output voltage from said DC level; and (c) a second stage coupled to said first stage and having means for receiving said output voltage produced by said first stage and means for generating one or more output voltage levels, and said second stage including means for isolating said first stage.

BRIEF DESCRIPTION OF THE DRAWINGS Reference will now be made to the accompanying figures which show, by way of example, a preferred embodiment of the present invention, and in which: Fig. 1 is a schematic representation of a power supply according to the present invention; Fig. 2 is a block diagram of a preferred embodiment of a switching power supply according to the invention; Fig. 3 is a schematic diagram showing the first stage of the switching power supply of Fig. 2; Fig. 4 is a schematic diagram showing the second stage of the switching power supply of Fig. 2; and Fig. 5 is a timing diagram showing selected signals for the switching power supply in Figs. 3 and 4.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Reference is first made to Fig. 1 which shows a switching power supply 10 according - to the present invention. The switching power supply 10 comprises a first stage indicated by reference 11 and a second stage indicated by reference 12. The first stage 11 includes a buck converter circuit, and the second stage 12 includes a full switching bridge converter circuit.

As shown in Fig. 1, the first stage 11 comprises an oscillator 20, a switch 21, an inductor 22, a capacitor 23 and a diode 24. The output of the oscillator 20 drives the switch 21 which is connected to the anode of the diode 24 and one terminal of the inductor 22. The other terminal of the inductor 22 is connected to one terminal of the capacitor 23 and forms an output for the first stage 11.

The cathode of the diode 24 and other terminal of the capacitor 23 are coupled to a high voltage rail HV indicated by 26. The high voltage rail 26 comprises a DC supply voltage which may be derived from a DC power source or converted from an AC mains supply.

The oscillator 20 chops the input voltage, i.e. the high voltage HV from the rail 26, and applies the pulses to the inductor 22 and capacitor 23. The capacitor 22 and inductor 23 form a LC filter which averages the pulses. The output voltage from the first stage 11 is lower than the input voltage HV applied on the high voltage rail 26.

The output from the first stage 11 provides the input to the second stage 12. As shown in Fig. 1, the second stage 12 comprises an oscillator 30, a full-bridge converter 31 and an isolation transformer 33. The fullbridge converter 31 comprises four switching devices 32, shown individually as 32a, 32b, 32c and 32d. The switching devices 32 are connected in a bridge configuration, and switching devices 32a and 32d are controlled by one output from the oscillator 30, and switching devices 32b and 32c are controlled by the other output from the oscillator 30.

The output from the converter 31 is connected to the primary winding of the transformer 33. Through the switching of the bridge converter 31, an alternating voltage is induced in the secondary winding of the transformer 33. The output from the secondary winding is rectified by a diode 34 and applied to a capacitor 35. The capacitor 35 "smoothes" the rectified output and provides a DC output voltage at output 36. A load represented by a resistor 37 is coupled to the output 36.

Advantageously, the buck converter for the first stage 11 produces an efficient output and maintains a stable output voltage level provided the input supply voltage HV does not drop below the output level. However, the first stage 11 does not provide a high degree of isolation. Advantageously, the full-bridge converter 31 in the second stage 12 provides a very efficient output with low ripple and good isolation by utilizing the isolation transformer 33. However by itself the full-bridge converter cannot maintain a constant output level if the input voltage (i.e. HV rail 26) varies. Thus, the first stage 11 maintains the input voltage at a constant level and the second stage 12 produces an efficient output which is isolated. As will understand by those skilled in the art, isolation from the high voltage is desirable for safety reasons, particularly in the field of consumer electronics.

Reference is next made to Fig. 2 and Figs. 3-4 which show an implementation of a switching power supply 100 according to the present invention. The power supply 100 is arranged to generate +15V, -15V and +30V outputs with a common ground, and +15V and -15V outputs with another common reference isolated for 250 VAC. The power supply 100 is operable from an AC power source (e.g. mains supply) in the range 9-250 VAC, 40 to 70Hz or from DC power source (e.g. a battery) in the range 9-250 VDC. Fig. 2 shows the switching power supply 100 in block diagram form, while Figs. 3 and 4 show the power supply 100 in schematic form. In Figs. 2 to 4, like reference numerals indicate like elements.

As shown in Fig. 2, the switching power supply 100 comprises a first stage 101, a second stage 102, a supply input stage 103, an oscillator start-up stage 104, and a voltage levels detector and feedback stage 105.

The supply input stage 103 provides a supply input for the power supply 100 and as shown comprises a plug 110 which connects to an energy source denoted generally by 99. According to the invention the power supply 100 is operable from either a DC energy source (e.g. a battery) or an AC energy source (e.g. a 120 VAC "mains" supply). The input stage 103 includes a surge protection circuit 111, a line filter il3, and a full bridge rectifier and filter 115. Since it is more convenient work in DC, the full bridge rectifier and filter 115 are provided to convert the input from an AC energy source into a DC output HV on an output rail 117. The input stage 103 includes two lines 116a and 116b (Fig. 3) which connect to a plug 110 which is coupled to the AC power source or DC power source 99.

The surge protection circuit 111 comprises a pair of varistors S1 and S2. The function of the varistors S1 and S2 is to clip surges on lines 116a, 116b from the energy source 99 (e.g. the mains supply). The first varistor S1 clips differential surges on the two lines 116a and 116b. The second varistor S2 clips common mode surges on the first line 116a. When a common mode surge occurs on line 116b, the varistors S1 and S2 clip the surge. The surge protection circuit 111 also includes a fuse F1. The varistors S1 and S2 are placed before the fuse F1 to absorb surges which would otherwise "blown the fuse Fl.

Accordingly, the varistors S1 and S2 are rated for 250 VAC.

The fuse F1 provides overload protection for the first stage 101, specifically against a short circuit on the primary of transformer T1. The fuse F1 is rated as follows. The first stage 101 includes a large capacity capacitor C18 which can draw a charging current up to lOOA.

Because of the magnitude of this current, the fuse F1 is selected to be of the "slow blow" type. The high average current (approximately 0.5A) occurs when the input voltage is 9 VAC. While a fuse rated at 1 Ampere is capable of withstanding the average high current, a fuse with a 2 Ampere rating from the Littlefuse Corporation is selected for handling the inrush current that is the worst at 250 VAC. The 2AG fuse from the Littlefuse Corp. is rated with a rupture current of 100A in AC/DC.

The line filter 113 is included for compliance with emission standards (i.e. CISPR 11, CLASS B and FCC part 15, CLASS B). The line filter 113 comprises a capacitor C2, a choke T2, and ferrite beads L3, L4. The capacitor C2 shorts the lines 116a and 116b together at high frequencies. Because the lines 116a, 116b are connected to the mains supply, the capacitor is an X-type capacitor as will be understood by one skilled in the art.

The choke T2 comprises a 10-mH common mode choke. The principal function of the choke T2 is to disconnect the power supply 100 from the mains supply line at medium to high frequencies. Because the common mode choke T2 is not perfect at very high frequencies (i.e. over 30 MHz), the ferrite beads L3 and L4 are included to handle the high frequency range. As shown in Fig. 3, the line filter 113 also includes capacitors C97 and C99 for shorting high frequency signals on lines 116a, 116b to ground GND.

Because the capacitors C97 and C99 are connected across the line voltage and ground, the capacitors C97, C99 are Ytype. To damp the high Q of the capacitors C97, C99, a 10 Ohm resistor R56 is connected in series with capacitor C97 and another 10-Ohm resistor R57 is connected in series with capacitor C99 (Fig. 3). Because a common mode surge on the input lines 116a, 116b could damage the resistors R56 and R57, diodes D34 and D10 are connected across resistor R56 and diodes D42 and D48 are connected across resistor R57 as shown in Fig. 3. The diodes D10, D34, D42, D48 limit the excursion on each of the resistors R56 and R57 to +0.7 Volts.

The full-bridge rectifier 115 is included in the input stage 103 to rectify an AC input from the energy source 99 and generate a DC output HV on output rail 117.

As shown in Fig. 3, the full-bridge rectifier and filter 115 comprises four diodes Dull, D12, D13, D14. The diodes Dll-D14 are connected in a bridge configuration. The line voltage output from the choke T2 provides the input to the bridge and the output of the bridge is connected to the high voltage DC rail 117. To handle the range of input line voltages from the energy source 99, the diodes Dll-D14 are preferably rated for 3 A at 400 V. Because the diodes D11-D14 make noise when they switch, a snubber circuit 118 is added across each diode Dll-D14 as shown in Fig. 3 to damp the switching noise. Each snubber circuit 118, shown individually as also, 118b, 118c, 118d in Fig. 3, comprises a respective resistor R58, R59, R60 and R61 and a respective capacitor C35, C36, C37 and C41.

The first stage 101 also includes a line filter 120 to filter the output from the bridge rectifier 115 and produce low ripple high voltage HV on the output rail 117.

The line filter 120 comprises capacitors C18 and C83. In the present implementation, the capacitor C18 has a capacitance of 22 uF. The second capacitor C83 has a capacitance of 0.22 uF and is included to filter high frequency spikes. Preferably, both capacitors C1B, C83 are rated for 400 VDC.

Referring to Fig. 2, the first stage 101 includes a buck converter circuit comprising an oscillator 120, a switch Q9, a diode D21, an inductor L1 and a capacitor C24.

The output of the oscillator 120 is coupled to the switch Q9 through a network comprising series of gates 122, a high voltage detector 124, and an envelope detector 126. (The operation of the gates 122 is described in more detail below.) As shown in Fig. 2, the cathode of the diode D21 is coupled to the high voltage rail 117 and the anode is connected to one terminal of the switch Q9. The anode of diode D21 is also connected to one terminal of the inductor L1. The other terminal of the inductor L1 is connected to one terminal of the capacitor C24 and also to the anode of a Zener diode Z14. The other terminal of the capacitor C24 is connected to the high voltage rail 117. The cathode of the Zener diode Z14 is also connected to the high voltage rail 117. The output of the buck converter circuit is coupled to the second stage 102 through capacitors C3 and C45, resistor R63 and Zener diode Z1 as shown in Figs. 2 and 4.

The oscillator 120 chops the input voltage HV from the high voltage rail 117 and applies the pulses to the inductor L1 and capacitor C24. The inductor L1 and capacitor C24 form a LC filter which averages the pulses.

In order to start the oscillator 120 an 8-volt start-up voltage is provided. The start-up stage 104 generates the start-up voltage on output rail P8V for the oscillator 120.

As shown in Fig. 2, the start-up stage 104 comprises first and second voltage regulators 130, 132 and a voltage pump 134. The first voltage regulator 130 generates the initial start-up voltage on output rail P8V for the oscillator 120 as will be described. The second voltage regulator 132 then maintains the level on output rail P8V based on the output of the first stage 101. As shown in Fig. 2, the second voltage regulator 132 is coupled to a secondary winding 136 on transformer T1 through a rectifier and filter circuit 138. The operation of the second regulator 132 is also described in more detail below. The output rail P8V from the first 130 and second 132 voltage regulators is coupled to the oscillator 120 through an P8V output rail circuit 121 which is also described in more detail below.

The first voltage regulator 130 generates the 8 volt start up voltage on output rail P8V directly from the high voltage rail 117. As shown in Fig. 3, the first voltage regulator 130 comprises a transistor Q8, a transistor Q6, and zener diodes Z6 and Z12. Because the voltage level on the high voltage rail 117 can vary from 7.5 VDC to 400 VDC, a MOSFET is used for transistor Q8, preferably a N channel MOSFET rated for 400 Volts. The MOSFET Q8 is configured in a common drain arrangement with feedback through the zener diode Z6 and the bipolar transistor Q6. As shown in Fig. 3, the source of the MOSFET Q8 is connected to the high voltage rail 117 through a current limiting resistor R64. The drain of the MOSFET Q8 is coupled to common rail ACOM through the zener diode Z6 and a resistor R13. The drain of the MOSFET Q8 is also connected to the anode of the zener diode Z12 to form an output node 140 which is coupled to the P8V output rail circuit 121. The cathode of the zener diode Z12 is connected to the gate of the MOSFET Q3 and the collector of transistor Q6. The base of transistor Q6 is connected to the junction formed by the anode of zener diode Z6 and one terminal of the resistor R13.

The gate of the MOSFET Q8 is coupled to the output of the voltage pump 134 through the resistors R11, R12. If the gate of the MOSFET QB is coupled directly to the high voltage rail 117 through the resistors Ril and R12, there is a voltage drop of at least 4 Volts. This means that the regulator 130 will only produce an output of about 3.5 Volts (i.e. when HV = 7.5 Volts) which is not sufficient to start the oscillator 120. The principal function of the voltage pump 134 is to raise the voltage 8 Volts higher than the level on the rail 117 during a low voltage state.

Once the voltage level on output rail P8V reaches the 8 Volt level, the oscillator 120 is started and the first stage 101 starts producing an output through the switching action of switch Q9 as will be described in more detail below. At that moment, the second stage 102 of the power supply 100 will begin receiving the output from the first stage 101 and a voltage will be induced into the secondary winding 136 of the transformer T1. As shown in Fig. 4, the secondary winding 136 is coupled to the rectifier circuit 138 which comprises a capacitor ClS and a diode D31. The rectifier circuit 138 also includes a snubber circuit comprising a capacitor C46 and a resistor R62 to damp the switching noise from diode D31. The diode D31 rectifies the voltage signal induced in the secondary winding 136 and the capacitor C15 is charged to 15 VDC.

The output from the rectifier circuit 138 is coupled to the input of the second voltage regulator 132.

As shown in Fig. 3, the second regulator 132 comprises transistors Q5, Q? and zener diode Z5. The collector of transistor Q5 is coupled to the output of the rectifier circuit 138. A resistor R18 is coupled across the collector/base junction of transistor Q5 and the base of Q5 is also coupled to the collector of transistor Q7.

The transistor Q7 is configured in common-emitter mode with resistors R17 and R15 as shown in Fig. 3. The zener diode Z5 is coupled to the base of transistor Q7 and emitter of transistor Q5. The output (i.e. the cathode of the zener diode Z5) of the second regulator 132 is coupled to diode D16 in the P8V output rail circuit 121. The second output regulator 132 regulates the voltage to 8 Volts on output rail P8V when the zener Z5 is turned on. The zener ZS is turned on by the transistor Q5 which is coupled to the output of the rectifier circuit 138. As shown in Fig. 3, the output of the zener Z5 is also coupled to the base of transistor Q6 in the first voltage regulator 130 through resistor R14 and a zener diode Z15 in the output rail circuit 121 for P8V. The zener diode Z15 provides a threshold for turning on the transistor Q6 and disabling the MOSFET Q8. It is preferable to turn on transistor Q6 only when transistor QS is supplying a low voltage. In the present arrangement, the MOSFET Q8 is disabled when the output voltage from rectifier circuit 138 reaches 7 Volts (i.e. Vzls + BE (6.2 + 0.7 Volts)). It is preferable to disable the MOSFET Q8 especially at high voltage because even if the current is low, the power dissipation in MOSFET Q8 will be high. This feature makes the start up stage 104 more efficient.

Referring to Fig. 3, the start-up stage 104 includes a capacitor C72 to filter the rail P8V which is included in the P8V output rail circuit 121. The P8V output rail circuit 121 also includes diodes D1S, D16 and the zener diode Z15 and resistor R14. The diode D15 is connected to the output (i.e. the cathode of zener diode Z6) of the first voltage regulator 130. The other diode D16 is connected to the output (i.e. the cathode of zener diode Z5) of the second voltage regulator 132. The diode D16 is the same type as diode Dl5 so that the diodes D15, D16 turn off at the same voltage. Diode D17 is included to prevent a negative bias when transistor Q8 is turned off.

It will also be appreciated that the zener Z12 protects the gate of the MOSFET QB which could be pulled above 400 VDC by the series connected resistors R11 and R12.

As shown in Fig. 3, the start-up stage 104 also includes the voltage pump 134 comprising diodes D35, D36, resistor Rl01 and capacitor C42. The junction formed by the cathode of diode D35 and anode of diode D36 is connected to the output of the oscillator 120 through the series connected resistor R101 and capacitor C42. The anode of the diode D35 is coupled to the high voltage rail 117. The cathode of the diode D36 forms the output for the voltage pump 104 and is connected to the gate of the MOSFET Q8 through the series connected resistors R11 and R12.

Referring to Fig. 2, the oscillator 120 and gates 122 generate control pulses 302 (Fig. 5) which actuate the switch Q9. The opening, and closing of the switch Q9 generates pulses through the inductor L1 and capacitor C24 which transfers energy to the second stage 102. As will now be described, the oscillator 120 and gates 122 are configured to operate in two modes so that the same amount of energy is transferred in each cycle. In a first mode, the duty cycle of the control pulses to the switch Q9 are changed while the frequency remains the same. However, if the output voltage is very low, this leads to a long duty cycle (i.e. wide pulse width) and consequent slow turn on time for the power supply 100. Conversely, if the output voltage is very high, the resultant duty cycle for the control pulses leads to a very a narrow pulse which would be impractical and put severe design constraints on the circuit. Consequently, a second mode of operation is provided in which control pulses for actuating the switch Q9 are skipped when the output is at a high voltage level.

Referring to Fig. 3, the oscillator 120 is coupled to the switch Q9 through a series of NAND gates 122, shown individually as 123a, 123b and 123c. The oscillator 120 is implemented using a CMOS version of the industry standard 555 timer chip indicated by U8. The timer chip U8 produces a pulsed output 300 (Fig. 4) on pin 3. As shown in Fig. 3, pin 3 on the timer U8 is connected to one input of the second gate 123b. The other input of the second gate 123b is connected to the output of the first gate 123a. One input of the first gate 123a is connected to the output of the envelope detector 126 and the other input feeds back the output from the second gate 123b. The output from the second gate 123b is connected to one input of the third gate 123c. The other input of the third gate 123c is coupled to the high voltage rail 117 through a voltage divider formed from resistors R106, R71 and R19 as shown in Fig. 3. The output of the third gate 123c is coupled the switch Q9 through a push-pull circuit 150 comprising NPN transistor Q10 and PNP transistor Qll.

The push-pull circuit 150 is coupled to the P8V rail 121.

The transistors Q10 and Qll in the push-pull circuit 150 provide a low impedance to quickly charge and to discharge the stray capacitance on the gate of the MOSFET Q9. To provide adequate power handling capability, the switch Q9 comprises a N-channel MOSFET rated for 400 VDC. As shown in Fig. 3, the source of the MOSFET Q9 is connected to the junction formed by the connection of the diode D21 and the inductor L1. To damp the switching noise from the diode D21 a snubber circuit comprising capacitor C43 and resistor R55 is included. Similarly, to damp the switching noise from the MOSFET Q9 a snubber circuit comprising capacitor C44 and resistor R54 is provided. Preferably, the diode D21 is rated for at least a 400 Volt reverse voltage and comprises an ultra-fast type diode. The capacitors C43 and C44 for the snubber circuits are rated for at least 400 Volts and capable of accepting a high dV/dt. Preferably, the capacitors C43 and C44 comprise NPO dielectric capacitors which advantageously also exhibit a very low dissipation factor.

The timer chip U8 is configured so that the duty cycle of the pulses 300 (Fig. 5) on the output (pin 3) vary linearly as an inverse function of the voltage level HV on the high voltage rail 117. This function is achieved by configuring the timer chip U8 as follows. The trigger (pin 2) and the threshold (pin 6) on the timer U8 are both connected to a capacitor C16. The capacitor C16 is charged by the high voltage rail 117 through a pair of series connected resistors R20 and R113. The higher the voltage on the rail 117, the quicker the capacitor C16 is charged.

As shown in Fig. 3, the discharge input (pin 7) is connected to the capacitor C16 through a resistor R21.

The resistor R21 and the capacitor C16 serve to determine off time for the pulses in the output 300. To avoid affecting the pulse off time, diodes D19 and D20 are provided as shown in Fig. 3. When the output (pin 3) of the timer U8 is at 0 Volts, the anode of the diode D20 is lower than the cathode (i.e. capacitor C16 will have at least 1/3 of P8V or 2.67 Volts). As a result diode D20 does not conduct and the current from resistors from resistors R20 and R113 is shunted by diode D19. With diode D20 off, the discharge of the capacitor C16 is only dependent on the resistor R21, and the resistors R20 and R113 are set to transfer the same amount of energy per cycle. As also shown in Fig. 3, the output rail P8V is connected to the reset input (pin 4) of the timer chip U8 so that the rail P8V provides a reset to the timer U8 until the 8-Volt level is reached.

The pulsed output signal 300 from the timer U8 is used to generate a gate control signal 312 (Fig. 5) which is applied to the gate of the MOSFET Q9. As the voltage level HV on the rail 117 increases the pulse width for the output signal 300 from the timer U8 will become narrower as illustrated at 301 and 303 in Fig. 4. Eventually a certain point is reached where the timer U8 cannot switch fast enough to create a narrower pulse width. Since the width of the pulses in the gate control signal 302 (Fig. 5) controls the current in the inductor L1 and also the stored energy, the second mode of skipping pulses is used to control the switching of the MOSFET transistor Q9 and thereby the energy stored in the inductor L1.

The skipping of pulses in the pulsed output 300 from the timer U8 is controlled by a feedback control loop 152. As shown in Fig. 2, the feedback control loop 152 comprises an opto-coupler U4 (Fig. 4) and a voltage level detector 154. The voltage level detector 154 senses the voltage level HV-DCOM on the high voltage rail 119 (Fig. 4) in the second stage 102. Because the high voltage rail 119 is referenced to DCOM in the second stage, the opto-coupler U4 is utilized for isolation. As shown in Fig. 4, the voltage level detector 154 comprises resistor R30 and zener diode Z3. The resistor R30 is connected to the high voltage rail 119 and drives an internal LED 154 in the opto-coupler U4. When the internal LED 154 is turned on, the emitted light activates an internal phototransistor 156 which produces an active LOW output, i.e. pulls down a feedback output 158. The voltage level detector 154 is configured to drive the internal LED 154 when the voltage level HV-DCOM on the high voltage rail 119 reaches 7.5 VDC.

The 7.5 VDC level corresponds to a 9 VDC supply input (i.e. from the energy source 99) with the voltage drops across the two diodes D11, D12 in the full-bridge rectifier 115 taken into account. This is the lowest supply voltage level the power supply 100 will operate under for this embodiment.

The voltage applied to the second stage 102 is controlled by the switching of the transistor Q9. Once the voltage level HV-DCOM on the high voltage rail 119 in the second stage 102 reaches the pre-determined level (i.e. 7.5 VDC) denoted by 304 in Fig. 5, the opto-coupler U4 is triggered (306 in Fig. 5) which pulls down the feedback output 158 (308 in Fig. 5). The signal 308 (Fig. 5) on the feedback output 158 is coupled to the inputs of gate 123d which is configured as an inverter. The output signal 310 (Fig. 5) from gate 123d is coupled to one input of gate 123a and one input of gate 123c. When the signal 308 (Fig.

5) on the feedback output 158 is low, the output 310 (Fig.

5) from the gate 123d blocks the control pulses (312 in Fig. 5) to the gate of the MOSFET Q9 and keeps the MOSFET Q9 off (314 in Fig. 5) until the voltage level HV-DCOM on the high voltage rail 119 drops below the threshold voltage (i.e. 7.5 VDC). Fig. 5 also shows the timing for the output 316 from the gate 123b and the input 318 to the gate 123c.

As shown in Fig. 2, the output of the gate 123d is also connected to the envelope detector 126. The envelope detector 126 comprises a diode D18 and a capacitor C13 as shown in Fig. 3. When signal 308 (Fig. 5) on the feedback output 158 is active LOW, the inverted output 310 (Fig. 5) from the gate 123d causes the diode D18 to conduct and the capacitor C13 discharges (because its reference is P8V). In order to avoid spikes on the output rail P8V, the capacitor C72 should be at least 10 times bigger than capacitor C13. When the HV-DCOM voltage level on the high voltage rail 119 (Fig. 4) drops below the threshold level (i.e. 7.5 VDC) the signal level on the feedback output 158 is pulled up by rail P8V, the resistor R19 pulls the input to gate 123c down and the output of the gate 123c goes high and the MOSFET Q9 is turned on and energy is transferred to the second stage 102, i.e. without chopping the voltage HV on the rail 117.

While the capacitor C72 preferably has a capacitance which is sufficient to filter the rail P8V, the value of capacitor C72 should not be so large as to slow down the energizing of the rail P8V. If the energizing of the rail P8V is too slow, the proper operation of the oscillator 120 could be affected. For example, if the oscillator 120 keeps the switch Q9 on too long, this can force a high voltage across the zener Z14 (Fig. 4) and as a result the fuse F3 would rupture because the voltage of zener Z1 is lower than zener Z14. The zener Z14 would continue to conduct and the current flowing through the inductor Ll and the MOSFET Q9 would increase until the interconnect (e.g. circuit board trace) fails. At that moment, the energy stored in the inductor L1 would try to find a path and would increase the voltage on the MOSFET Q9 up to the breakdown voltage for the MOSFET Q9. At that level, the MOSFET Q9 would fail and short circuit the rail P8V via the transistor Q10. As the level on the output rail P8V, the MOSFET Q8 will attempt to raise the voltage level on the rail P8V. The MOSFET Q8 will continue to draw current from the high voltage rail 117 until the resistor R64 eventually fails.

Referring back to Fig. 3, the capacitor C13 is tied to the output rail P8V in order to provide a start-up condition when the MOSFET Q9 is off or in oscillation. As also shown in Fig. 3, the resistors R106 and R71 are provided with resistance values which disable the envelope detector 126 when the voltage level HV on the high voltage rail 117 is greater than 30 VDC.

Reference is made back to Fig. 2 and the second stage 102 for the power supply 100. As described above, the second stage 102 includes a full-bridge converter 200 and an isolation transformer Tl. The full-bridge converter 200 comprises an oscillator 201 and two pairs of complementary switching devices U9A, U9B and U1OA, U1OB.

The switching devices US and U10 are connected in a bridge configuration. The primary winding of the transformer T1 is coupled to the output of the bridge converter 200. The second stage 102 also includes a rectifier and filter stage 206, a rectifier and filter stage 208, and a voltage doubler 210. The rectifier and filter stage 206 is coupled to a secondary winding 212 on the transformer T1 and generates a +15VDC output rail P1SVI and a -lSVDC output rail N15VI which are referenced to a common ground ICOM isolated for 250 VAC. The rectifier and filter stage 208 is coupled to a secondary winding 214 on the transformer TI. The rectifier and filter stage 208 generates a +15VDC output rail P15V and a -15 VDC output rail N1SV. The voltage doubler 210 is coupled to output rail P15v and generates a +30VDC output rail P30V. The output rails P15V, N15V and P30V are referenced to the common ground GND.

As shown in Fig. 4, the oscillator 201 for the second stage 102 is implemented using a CMOS version of a 555 timer chip denoted by U3. The timer chip U3 is configured in known manner utilizing resistors R23-R27 and capacitors C21, C33 to produce 100 kHz output pulses on pin 3. The output of the timer U3 is coupled to the base of a transistor Q12. The transistor Q12 in conjunction with the internal discharge MOSFET transistor (not shown) on pin 7 of the timer chip U3 drives the complementary pair of MOSFET transistors U9A and U9B. The output from the complementary MOSFET pair U9 drives the complementary pair of MOSFET transistors U1OA and U1OB. With this arrangement, each MOSFET pair U9, U10 provides the inverse voltage thereby effectively driving the primary winding of the transformer T1 with +7.5 Volts.

The output pulses from the timer chip U3 have a 50% duty cycle and frequency f = 2*R26*C33 = 100 kHz. To prevent a DC offset, the duty cycle is tuned to 50% by the selection of the appropriate values for resistors R23, R24 and R25. As will be apparent to those skilled in the art, the values for the resistors R23-R25 may have to be recalibrated for 555 timer chips from different manufacturers.

As described above, the HV-DCOM voltage value on the high voltage rail 119 for the second stage 102 is regulated at 7.5 VDC by the voltage regulator 154 and the feedback control loop 152 to the first stage 101. For additional safety, a voltage level detector 216 for the output rail P15V and a voltage level detector 218 for the P30V output rail are provided. The respective outputs from the voltage level detectors 216, 218 are wire OR'd and coupled to the input of a second opto-coupler U7. The output of the opto-coupler U7 is connected to the input of gate 123d.

Referring to Fig. 4, the voltage level detector 216 for the P15V output rail comprises zener diodes Zll and Z10 and resistor R37. The zener diodes Z10, Z11 and the resistor R37 are connected to the internal LED in the optocoupler U7 as shown in Fig. 4. Similarly, the voltage level detector 218 for the P30V output rail comprises zener diode Z9 and utilizes the resistor R37. As shown in Fig.

5, if the voltage level on the P15V output rail exceeds the respective threshold value (i.e. 15.3 VDC) as indicated by 320, then the zener diodes Z10, Zll generate an output 322 which turns on the internal LED in the opto-coupler U7 to generate an output signal 324 on the feedback output 158.

The feedback output 158 disables the MOSFET Q9 in the first stage 101 as described above the high voltage level detector 154. Similarly, when the voltage level on the P30V output rail exceeds the threshold value (i.e. 30.9 VDC), the zener diode Z9 produces an output 328 which causes the internal LED in the opto-coupler U7 to generate output signal 330 on the feedback output 158.

Referring back to Fig. 4, the transformer Tl comprises a primary winding and the three secondary windings 136, 212, 214. The ratio between the primary and the secondary windings is 1:2. As a result, working with a 7.5 Volt level on the output rail 117 coupled to the primary, outputs of +15 Volts and -15 Volts are conveniently generated on the secondary side of the transformer T1.

In the context of the present power supply 100, it is desirable utilize a transformer T1 having a small core while maintaining efficient operation. In order to improve the efficiency of the transformer T1, the secondary windings are wound on top of the primary winding with windings being formed from triple (Teflon) insulted wire.

Advantageously, the second !and third layers of insulation provide isolation in the event the first (or second) layer is damaged.

As shown in Fig. 4, the secondary winding 136 feeds the voltage regulator 138 in the first stage 101 with +15 VDC which is converted into 8 VDC by the rectifier and filter stage 138 as described above. Because of the low power requirement , the secondary winding 136 may comprise a thin wire, for example gauge #29.

The secondary winding 212 is utilized to create the isolated PlSVI and N15VI output rails which are referenced to common rail ICOM and completely isolated at 250 VAC/VDC. The rectifier and filter circuit 206 comprises a stage 207a for generating the positive output rail PlSVI and a stage 20yb for generating the negative output rail N1SVI. Each of the stages 207 comprise respective rectifying diodes D22, D23 and smoothing capacitors Cl9, C5. To damp the switching noise from the diodes D22, D23, each stage 207 includes a snubbing circuit comprising respective resistors R118, Rll9 and capacitors C88, C89. Further filtering of the PlSVI and N1SVI output rails is provided by respective inductors L8, L9 and capacitors C20, C23.

As shown in Fig. 4, the secondary winding 214 is utilized to create the P15V and Nl5V and the P30V output rails which are referenced to ground. The rectifier circuit 208 comprises a diode D49 and a capacitor C30 for producing the P15V output rail. To damp the switching noise in the diode D49, a snubber circuit comprising resistor R117 and capacitor C91 is provided. Similarly for generating the N1SV output rail, the rectifier circuit 208 includes a diode D27 and a capacitor C29. To damp the switching noise in the diode D27, another snubber circuit comprising resistor R115 and capacitor C90 is provided.

Further filtering of the P15V and N15V output rails is provided by respective inductors L10, L13 and capacitors C31, C32 connected as shown in Fig. 4. Diodes D7 and D9 are connected to the respective P1SV and N15V outputs for providing floating output rails P1SVF and N1SVF. The floating output rails P1SVF and N1SVF are referenced to common AGND, whereas the output rails P15V and N15V are referenced to GND.

Referring again to Fig. 4, the P30V output rail is generated from the P15V rail by the voltage doubler 210.

The voltage doubler 210 comprises a transistor Q4, a capacitor C27 and a switching network 211. The switching network 211 controls the switching of the transistor Q4 to double the voltage on the capacitor C27. As shown in the switching network 211 comprises diodes D25, D26, D28, D29, resistors R22, R42 and capacitor C26. A snubber circuit comprising resistor 116 and capacitor C92 is provided to damp switching noise in diode D25. Through the action of the transistor Q4 and the diode path D28 and D29, the output capacitor C27 is charged to 30 Volts, i.e. double the 15 Volt level on the P15V output rail. Further filtering the P30V output rail is provided by inductor L11 and capacitor C28.

In summary, the present invention provides a power supply capable of operating over a wide range of input voltages including both DC and AC.

The present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. Therefore, the presently discussed embodiments are considered to be illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

Claims (5)

1. CLAIMS 1. A switching power supply for generating one or more output voltage levels, said switching power supply comprising: (a) an input stage having means for receiving a supply voltage and means for converting said supply voltage to a DC level; (b) a first stage coupled to said input stage for receiving said DC level and said first stage having means for producing an output voltage from said DC level; and (c) a second stage coupled to said first stage and having means for receiving said output voltage produced by said first stage and means for generating one or more output voltage levels, and said second stage including means for isolating said first stage.
2. 2. A switching power supply for generating one or more output voltage levels, said switching power supply comprising: (a) an input stage having means for receiving a supply voltage and means for converting said supply voltage to a DC level; (b) a first stage coupled to said input stage for receiving said DC level and said first stage having means for producing an output voltage from said DC level; (c) a second stage coupled to said first stage and having means for receiving said output voltage produced by said first stage and means for generating one or more output voltage levels, and said second stage including means for isolating said first stage; and (d) a start-up stage coupled to said first stage and said input stage, said start-up stage including means for starting said power supply during a low power period.
3. 3. The switching power supply as substantially described herein.
4. 4. The switching power supply as substantially depicted herein.
5. 5. The method for operating the switching power supply as substantially described herein.