GB2331415A - Radio communications system - Google Patents

Abstract

A low power radio frequency transmitter, for use at 140 to 225 Mhz and output power of 1 to 20mW, includes a phase locked loop circuit 22 supplying a carrier which is modulated at 27 by data before application to a transmitting aerial via a muttipole filter 29 to remove unwanted signals. The use of a PLL enables the carrier frequency to be stable through wide variations in environment conditions without need for special crystals or SAW filters. The transmitter may use analog frequency shift keying(AFSK). A receiver (fig.5 not shown) suitable for use with the transmitter may include an input narrow band tuned filter, a BiFet pre-amplifier, a signal mixer and a pair of decoders to obtain an RF signal, an anlog output and a signal applied to a data slicer to recover data.A paging system responsive to data received from a computer for producing paging signals is also described.

Description

is -I- RADIO FREQUENCY TRANSMITTERS AND RECEIVERS The present invention

relates to low power radio frequency transmitters and receivers, and in particular, but not exclusively, to low power transmitters and receivers which are suitable for use in security systems.

Radio frequency transmitters and receivers are commonly used for security systems which can remotely protect buildings etc. using a variety of sensors. Groups of sensors communicate with a local base station, and groups of local stations communicate with a central system.

Radio frequency systems that are for use in such security systems are generally of the type that do not require licensing by the radio authorities, because the output powers are low. In the UK, for example this means output powers of 1OmW or less, and in the US 1mW or less.

An additional requirement of security systems is that they are cost effective since it is likely that many sensing units and local base stations will be required. Thus, only simple low power radio frequency circuits that use basic unsophisticated designs and components are considered suitable for such uses.

However, previously used transmitter and receiver circuit designs have many inherent disadvantages that cannot be overcome by simply adjusting the current designs.

Figure 1 of the accompanying drawings shows a previously used overtone RF transmitter 1 including a crystal oscillator 10 which produces an oscillating signal at a predetermined frequency. The overtone crystal oscillator typically uses a crystal which is cut so that it oscillates at an odd harmonic frequency of the crystal's fundamental frequency The transmitter also includes an amplifier 11 for 2331415 amplifying the oscillating signal, and an output filter 12. The output filter 12 is intended to remove unwanted frequency harmonics from the oscillating signal before the signal is output 13 to an antenna (not shown).

Transmitters of the type shown in Figure 1 suffer from significant disadvantages. For example, if configured as a third overtone oscillator (ie. one that oscillates at the third harmonic of the crystal fundamental frequency), all of the harmonics of the fundamental frequency and overtone frequencies can appear at the aerial terminal because the output filter cannot remove all the unwanted frequencies without over attenuating the main frequency. The design relies on is the rejection of the aerial to bring the output within statutory licence limits.

Such overtone transmitters also suffer from variation in output deviation of greater than 300% for the change of frequency for a given voltage applied to the modulation input. For example, the deviation can vary from 1 volt/kHz to 4.5 volts/kHz. In addition, the output power can vary significantly for a given supply voltage, for example from 10 dBm to 5 dBm from unit to unit. These variances make manufacture of a product with repeatable performance very difficult.

Typically, the transmitter of Figure 1 includes an amplifier having a variable capacitance diode. In that case the design suffers from DC linking, which means that if an output digital signal train is not DC balanced, then the receiving data slicer (i.e. a device which converts a degraded digital signal into a clear signal) cannot track the incoming data signal. DC linking is required in order to give the required deviation, but the absolute deviation reduces with output bit rate.

Previously used transmitters generally only work is if a 0 to +5 volt signal is applied to the modulation input. If the modulation signal is insufficient, the RF deviation from centre frequency (f,) is reduced, thereby introducing data errors at lower noise levels. Specifically, this means that conversion must be made from TTL logic to high-speed CMOS (HC) logic (CMOS has insufficient slew rate) for digital modulation. If HC logic is used, then a resistive divider must be used in order to skew the edge and reduce the deviation. Such a resistive divider impairs performance, and therefore requires buffering in order to bring the transmitter into useful operating parameters.

Any attempt to use the units for transmitting analogue signals requires an operational amplifier to shift the DC value of the signal to mid rail in order to overcome the DC offset problems.

The RF output of the old module was MPT (telecommunications authority) approved only with certain aerials. This limited the design, performance and use of the unit. If present Europeanwide CE mark requirements are to be met, then subsequent filtering using, for example, a surface acoustic wave (SAW) component and inductors is required. This results in further expense and a minimum of -4dB insertion loss. Emitted radiated power is then generally reduced from the 8 to 10 dBm specification to around 2 to 4 dBm. Thus, previously-considered transmitters rarely achieve the performance required for modern applications and therefore can typically have a high effective failure rate of around 80%.

Thus, there is a need to provide a compact but accurate radio frequency transmitter which can meet present CE test limits, and which can overcome the significant problems of the previously used modules.

According to a first aspect of the present invention there is provided a low power radio frequency -4 is transmitter comprising:

reference oscillator providing a signal having a first predetermined frequency; phase lock loop circuit for producing an output signal at a second predetermined frequency on the basis of the first predetermined frequency; mixing means for modulating the output signal with a data signal for providing a modulated output signal; and output means for outputting the modulated output signal from the transmitter.

The main components of the phase lock loop circuit are preferably provided by a telecommunications (GSM) chipset. Such integrated circuits are designed for use between BOOMHz and 1.2GHz, but transmitters embodying the first aspect of the present invention can make use of these components.

Figure 4 shows a block diagram of a previouslyconsidered RF receiver, for example for use at 173.225 MHz in a security system. The receiver comprises an aerial 41 for receiving an incoming signal, and a conventional tamper detection circuit 42 for providing a tamper output 49.

A surface acoustic wave (SAW) filter 43 receives the input signal from the aerial 41 and serves to filter the incoming signal to remove unwanted signals. Thus, the output from the SAW filter 43 is intended to include only the signal of interest. However, the SAW component is not particularly suited to an incoming frequency in the range 140 - 225 MHz, and is easily saturated at higher input powers which causes all frequencies to be passed by the filter.

This is then amplified by an amplifier 44 before being passed to an intermediate frequency decoder 45. The IF decoder receives a local oscillator signal from a local oscillator 46 and provides analogue and data outputs.

SAW filters can only be used at single designated frequencies, and so are not suited to filtering signals in a range, for example 140 to 225 MHz. Manufacturers currently only produce SAW filters at 173.225 MHz.

Present designs of SAW filter units were produced before the introduction of the CE tests and so cannot meet the new requirements. In particular, the 10 volt/metre test applied from 80 MHz to 1 GHz floods the first stage, resulting in no recognizable signal reaching the output. In addition, the data slicer of the previously-considered receiver suffered from DC offset, such that if a 501 mark to space ratio signal is applied to the receiver, this was recovered as a 60% signal. This led to altering phase shifts on the recovered digital signal dependent on the DC balance of the transmitted signal. Thus, external circuitry had to be used for any timing sensitive data transfer.

There is therefore a need to provide a receiver which overcomes these drawbacks.

According to a second aspect of the present invention, there is provided a low power radio frequency receiver comprising: receiver means for receiving a transmitted radio frequency signal having a carrier frequency, and including an input filter for producing a filtered signal, and a BiFet amplifier for amplifying the filtered signal, and for substantially isolating the input filter from the remainder of the receiver; oscillator means for producing an oscillating signal having a frequency related to the carrier frequency; mixing means for mixing the received signal and the oscillating signal to produce a mixed signal; and decoder means, operable to decode the mixed signal and to produce an output data signal therefrom.

According to a third aspect of the present invention, there is provided a low power radio communications systems comprising:

a transmitter including: a reference oscillator providing a signal having a first predetermined frequency; a phase lock loop circuit for producing an output signal at a second predetermined frequency on the basis of the first predetermined frequency; mixing means for modulating the output signal with a data signal for providing a modulated output signal; and output means for outputting the modulated output signal from the transmitter; and a receiver including:

receiver means for receiving a transmitted radio frequency signal having the second predetermined frequency, the receiver means including an input filter for producing a filtered signal and a BiFet amplifier for amplifying the filtered signal and for substantially isolating the input filter from the remainder of the receiver; oscillator means for producing an oscillating signal having a frequency related to the carrier frequency; mixing means for mixing the received signal and the oscillating signal to produce a mixed signal; and decoder means, operable to decode the mixed signal and to produce an output data signal therefrom.

For a better understanding of the invention, and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompanying drawings, in which:

Figure 1 shows a block diagram of a previously considered RF transmitter; is Figure 2 shows a block diagram of an RF transmitter embodying one aspect of the present invention; Figure 3 shows a circuit diagram of the transmitter of Figure 2; Figure 4 shows a block diagram of a previouslyconsidered RF receiver; Figure 5 shows a block diagram of an RF receiver embodying another aspect of the present invention; Figures 6, 7 and 8 show circuit diagrams of various parts of the receiver of Figure 4; and Figure 9 shows a circuit diagram of a pager device for a computer.

Figure 1 has been described above, and shows a previously-considered RF transmitter suitable for low power uses at frequencies around 173.225 MHz.

Figure 2 shows a block diagram of a radio frequency (RF) transmitter embodying the present invention, and Figure 3 shows a circuit diagram thereof. The transmitter 2 includes a transistor controlled crystal oscillator (TCXO) 21 which produces an oscillating signal at a first predetermined frequency. This reference signal is supplied to a phase lock loop (PLL) circuit 22. The PLL circuit 22 includes a reference divider 221 which operates to produce a reference signal which is reduced in frequency in comparison with the reference signal from the oscillator 21.

A main signal divider 222 receives part of the final output signal of the PLL by way of a signal splitter 226 as will be described in more detail below. The signal divider 222 provides a reduced frequency signal from the output signal for comparison with the divided oscillator frequency supplied by the reference divider 221. A phase comparator 223 receives the divided main output and reference signals so as to -8 is compare those signals. The output from the phase comparator 223 is fed to a low pass filter 224 which serves to filter out unwanted high frequency components.

The output of the low pass filter 224 is used to control a voltage/current controlled oscillator (VCO) 225. The output of the WO 225 serves as the output of the PLL 22, and has a frequency controlled by the input signal to the W0. The signal splitter 226 supplies part of the WO output to the signal divider 222 to provide a feedback loop for the phase lock loop.

Thus, by comparing the oscillating output of the WO with a reference oscillator, and adjusting the output of the WO as necessary by way of the LPF 224, a locked frequency can be produced.

The WO output signal is passed to a transmit mixer 26 where it is modulated with transmit data 27.

This modulated output signal is then amplified by a power amplifier 28 and filtered by a suitable multipole filter 29 which removes all unwanted frequency components from the output signal. The filtered signal is supplied to an output aerial (not shown) for transmission.

Figure 3 shows a circuit diagram of an example of the transmitter of Figure 2. The circuit can be conveniently divided into five sections:

a) b) c) d) e) main oscillator (21) phase lock loop (22) output amplifier (28) output filter (29) control processor (30) The main oscillator 21 is a fundamental frequency crystal controlled oscillator using crystal X2 as a reference amplified by a transistor Q4. The transistor Q4 serves to control the output of the crystal X2, in order to provide a reference frequency for the phase is locked loop 22.

The main components of the phase locked loop 22 are preferably provided by a PhillipsTm GSM chipset based on the UMA 1021 (U1) integrated circuit. As described, the PLL 22 uses frequency divided signals to provide a fixed frequency output.

As shown in Figure 3, the PLL circuit, which includes the main divider, reference divider and phase comparator in the integrated circuit U1 are controlled by the central processor 30, which in this example is an AT89C2051 integrated circuit. The LPF circuit 224 is provided by the components C9, CIO and R11. These component values are chosen in order to set the response and timing characteristics of the integrated circuit Ul.

The voltage controlled oscillator (VCO) 225 is provided by the variable capacitor W1, an inductance L1 and a capacitor C5.

The output amplifier is coupled to the phase lock loop by a buffer transistor Q5. The transistor Q5 provides an emitter-follower connection which enables a high impedance to be provided between the oscillator and the output amplifier. This serves to prevent unwanted signals being transferred backwardly from the output stage to the previous stages.

The amplitude of the output amplifier is controlled by RVi, preferably between 1 and 20 milliwatts. The central processor 30 controls the output of the transmitter by way of transistor Q2 so that the output amplifier is only turned on when the PLL is locked on to the desired frequency.

The multipole output filter 29 is provided by the components VC3, L3, L4, L6, C15, C16 and C25, and provides the necessary output filtering to meet the MPT requirements. The values for this filter are selected according to the required output frequency.

is The control processor 30 provides initial codes to the integrated circuit U1 in order to set the initial divider values for the phase lock loop. When the PLI, is lock on to the desired frequency, power is applied to the output stage. If the unit should fall out of a lock as detected at U2. 16, the divider data values are re-applied. The processor runs each time the circuit is started.

The transmitter is designed to be compatible with the footprints of existing industry standard modules. A transmitter embodying the present invention can provide sufficient power for the wide range of antenna used in this field, even those not matched for 50 ohms, for example a rubber covered helical antenna. The unit is able to provide a required emitted radiated power (e.r.p.) which is still reasonable and within MPT requirements. In one embodiment, the output power is variable from 20 mW to imW, with most European applications being 10 mW and US requirements being 1

MW.

The output filter is sufficient to filter out spurious harmonics to be low enough to allow CE certification without the need for an aerial having extra rejection characteristics. Two possible variants of the design can be used for FSK and AFSK; the FSK having deviation set to 1 Khz/5 volt modulation and the AFSK having the deviation set to 3 Khz/150 millivolt rms.

Since the transmitter is a fully synthesised PLL module, it will remain on frequency through wide variations in environment conditions, such as temperature. The integrated logic will not permit power output if the unit is out of frequency.

Transmitters embodying the present invention can usefully provide outputs in the range 140 MHz to 225 MHz, without the need for special crystals or SAW filters, since a PLL is used. The initial divider values provided by the central processor 30 are chosen to adjust the response of the PLL circuit 22 in order to provide the desired output frequency. The LPF 24 components are chosen in accordance with the performance required from the IC Ul.

Examples of permitted frequencies in various countries are shown below:

FREQUENCY COUNTRY FREQUENCY COUNTRY 140.437 Spain EE 173.225 Italy 142.250 Finland 173.225 Spain 142.475 Norway 173.225 USA 146.0125 UK (Police) 173.250 Switzerland is 146.4 Singapore NLA 173.280 Belgium 146.812 Denmark 173.500 Austria 153.812 Holland 174.200 Canada 154.050 Holland 183.8875 UK (R/M) 155.550 Portugal 191.5 Singapore NKA 169.387 Sweden 224.500 France 173.050 Spain 173.225 UK One transmitter embodying the present invention provides a 173.225 MHz RF transmitter. As described, the unit is designed as a Phase Locked Loop (PLL) synthesised frequency transmitter as before having a reference oscillator at 8 MHz. The comparison frequency is 25kHz; the reference signal being divided by 320 and the output signal by 6929. It can be specifically tuned for analog frequency shift keying (AFSK) and has sufficient output power to radiate 10 milliwatts from a quarter wave aerial. The output is adjustable to maintain this power on mis-matched aerials up to 100 ohms.

is The transmitter is preferably configured in one of two variants: one for FSK with deviation set to 1 Khz/5 volt modulation and the other for AFSK with the deviation set to 3 Khz/150 millivolt rms.

The unit is designed to pass MPT 1344 regulations and CE approvals to ETS 300.683 and ETS 300.339.

The specification of a 173.225 MHz transmitter is shown below

Transmitter Specification

Output Frequency:

Deviation:

Supply Voltage Supply Current Output Power Output Impedance Spurious & Harmonic content Modulation Bandwidth 400 Modulation input - 100K impedance:

Notes 173.225 MHz +/-50 Hz -01 +/-1 KHz/5 volt modulation -02 +/-3 KHz/150 millivolt modulation Min Nom Max Units 4.5 5.0 6.0 V +8 +10 50 10K -60 -57 dBM mA +12 dBm 0 11500 Hz 7500 Hz Q 1 2 3 @ 5v 4 Variant -02 Variant -01 Operating Temperature -20 20 70 0C range:

Storage Temperature -40 - 85 0C range:

Time delay to lock 2 - 14 millisecs Variant -01 - 30 millisecs Variant -02 Notes:

1. In this module design, the frequency is factory-adjustable between 140 MHz and 225 MHz. Any individual frequency selection requires appropriate choice of output filter components. The frequency is programmable in 12.5 KHz steps and the choice would usually be made by the manufacturer who would produce a range of preprogrammed devices.

2. -01 unit is digital modulation variant.

3. -02 unit is AFSK modulation variant 4. output power is preset for 1/4 wave aerials of 50 ohm impedance, at 5 volt supply. The units may be reset for use up to 20 mW for licensed use on industrial sites. All spurious harmonics remain below -54 dBm (defined for W55022B).

embodying following 1. throttled As will be readily appreciated, a transmitter the present invention can provide the technical improvements: The transmitter unit is a 20 milliwatt output back to, for example, 10 mW hence: Unit is able to give a genuine licence exempt 10 mW radiated power from a 50 ohm aerial. Spurious harmonics are reduced to -60 dBm at the aerial terminal, well below current requirements. Spurious emissions are reduced to current CE requirements.

The transmitter module includes a phase lock loop (PLL) synthesised signal hence:- 3.

Units will perform repeatably from unit to unit.

4. The transmitter can be easily adjusted to provide output frequencies from 140 - 225 MHz, thereby covering all European countries in a single footprint package.

Units are factory preset for respective band and country approvals. Specifically, the units are intended for sale either as analogue or digital variants, permitting correct filtering for modulation requirements.

5. Improved power output ensures MPT requirements are met, while retaining flexibility of choice of aerial systems.

6. Improved spurious emissions means lower is interference with other equipment.

7. Product will perform repeatably from unit to unit.

Figure 5 shows a block diagram of a receiver embodying the second aspect of the present invention suitable for use in a security system. Figures 6, 7 and 8 show circuit diagrams of various parts of the receiver.

The receiver is provided with an aerial 51 for receiving an incoming signal, and an anti-tamper circuit 42 for providing a tamper output 49, as before.

A narrow band tuned filter 52 receives the incoming signal and which is designed to be highly selective in order to remove unwanted signals.

A BiFet pre-amplifier 53 is provided in order to give improved rejection and also to protect the rest of the circuit from impulse loads to the aerial, such as lightning strikes.

The signal is then mixed by a mixer 54 with a local oscillator signal from a local oscillator 55 and then passed to a first intermediate frequency decoder 56. A second intermediate frequency decoder 57 is used to provide a radio frequency signal level output 58, an analogue output 59 and a data output 61 via a precision data slicer 60. The first intermediate frequency decoder also receives signals at the IF frequency and its harmonics. The second IF decoder superimposes a similar image in order to block those frequencies passed by the first decoder. This results in much improved rejection.

The receiver embodying the present invention will now be described in more detail with reference to -is- Figures 6, 7 and 8. Figure 6 shows a circuit diagram of the front end section of the receiver embodying the present invention. A filter 52 is provided by the components Cl, C2, C3, C4, Ll and L2. This precision filter is designed to remove unwanted signals from the incoming signal.

A BiFet transistor Q3 provides the main component of a pre-amplifier 53 in order to provide around 1 GO impedance to the incoming signal which protects the rest of the circuit.

The mixer 54 serves to combine the input signal with the local oscillator input 55. Typically the local oscillator signal can be around 100 gW. The local oscillator is shown in more detail in Figure 7 and includes a crystal Xl which is controlled by a transistor Q4. The local oscillator signal is mixed with the input signal of the receiver and undergoes a first downward conversion by use of the ceramic filter component FL1. The local oscillator output signal CON 1.0 is then provided to a impedance matching transformer Tl for supply to the circuit of Figure 8.

The Figure 8 circuit includes a Phillips' GSM integrated circuit Ul which receives the intermediate frequency high and low signals from the Figure 6 circuit. A reference oscillator X2 is provided, and a second frequency divider F2 further reduces the frequency of the signals. The circuit Ul operates to remove the carrier frequency signal from the input signal to provide an analogue output (AUDIO) or a digital data output (DATA 0/P) by way of the data slicer 60. The data slicer 60 is provided by an operational amplifier LMC 721 BIM in the example shown in Figure 8.

The component values shown in Figures 6, 7 and 8 provide a receiver embodying the present invention suitable for receiving a 173.225 MHz signal, although the general design is suitable for use with an input signal in the frequency range 140 - 225 MHz. The filter components and the various oscillator components are chosen in dependence upon the incoming frequency.

As will be readily appreciated, a receiver embodying the present invention can provide the following technical improvements over the previouslyconsidered devices:

1. Sensitivity maintained throughout spectrum from 80 MHz to 1 GHz for 10 volt/metre tests with permitted exclusion band.

2. Emitted radiation well below present CE limits.

3. One footprint unit can be adjusted to accept input frequencies from 140-225 MHz, thereby covering all European countries.

4. Improved sensitivity means that the receiver will work in areas of relatively high interference, i.e. near computers, laser printers, photocopiers, etc.

5. Reduced emitted radiation makes product cheaper as screening requirements are reduced.

6. The new unit has a BiFet amplifier protected by tuned input and output filters designed to reject out of band signals.

The local oscillator on the receiver embodying the present invention is fully screened and the voltage level produced on the board is 12 dB down on those generated by the previously-considered design. Both factors eliminate the radiation problems at this harmonic.

The new unit has a precision amplifier providing the data slicing function, which overcomes the above mentioned problems of the previouslyconsidered design.

Receivers embodying the present invention can be set to receive a frequency from 140 MHz to 225 MHz, simply by choosing the first and second intermediate decode values.

A receiver embodying the present invention is ideally compatible with the 173.225 MHz transmitter already described. It can be specifically tuned to receive both analog frequency shift keying (AFSK) and digital frequency shift keying.

The units have been designed to meet the CE test requirements of ETS 300 683 without further components.

A typical 173.225 MHz receiver specification is given below:

Receiver Notes Specification

Min Nom Max Units Supply Voltage 4.5 5.0 6.0 Volts Supply Current is 20 25 mA @ 5V RF Input sensitivity - -116 -113 dBm @12 dB Sinad Nominal RF Input - so - Impedance Image Rejection 60 65 - dB Adjacent channel 65 70 dB rejection Spurious emissions - -50 -45 dBm at aerial Frequency bandwidth 12.5 - Khz @-6dB AF Modulation 200 - 11500 Khz MB Analog Bandwidth Output Digital Modulation 400 - 7500 Khz 1% noise Bandwidth error digital AF output level - 30 - mV/KHz Distortion 1 2 @ 1 KHz RSSI output 0 - 4.5 V 2 Tamper Circuit 89 94 99 KQ Resistance Operating Temperature -20 20 70 0C range:

Storage Temperature 40 - 85 0C range:

Notes:

1. This design permits factory-selectable frequency in the range 140 MHz to 225 MHz. Any individual frequency selection requires appropriate factory choice of filter components.

2. The RSSI provides for a linear range from -129 dBm to -60 dBm, with a non linear range up to +10 dBm.

The receiver embodying the present invention is designed to be an industry standard unit, which will retain the same footprint and outline for any European harmonised frequency in the 140-224 MHz band.

The unit is designed to meet the CE test requirements. Specifically the unit will pass the test of simultaneous modulation input to the CE standards of test no. ETS 300 683, and still allow the module to decode information on the required band to the test no. ENV50141:1994. Such a test involves applying a 10 volt/metre signal to the filter of between 80 MHz and 1 GHz.

Figure 9 shows a circuit diagram of a pager module for a personal computer.

The unit is designed as an interface between a serial port on an PC and POCSAG communication to a RF linked pager. The module uses a switchable 458 MHz 100 milliwatt transmitter. A suitable

transmitter could be one embodying the first aspect of the invention, suitably modified for 458 MHz operation. The signal is recommended to be used with a NEC 26D 4 line pager. The system comprises the interface, cables, power supply, aerial, pager, and drivers for MSDOSO, Windows 3. ll') or Win 95').

The unit passes MPT 1329 and MPT 1361 regulations. The unit will pass CE approvals to ETS 300.683 and ETS 300.339 for conducted and radiated emissions.

Specification:

Notes Output Frequency: 458.835 MHz 1 Deviation: 4.5 Khz 2 Min Nom Max Units Supply Voltage 1: 4.5 5.0 6.0 V Supply Current 1: 20 30 mA @ 5v Supply Voltage 2: 8.5 12.0 14 V 3 Supply Current 2: 10 70 100 mA 12v Output Power 95 100 MW 4 Output Impedance 25 50 100 0 Spurious & Harmonic - -60 -57 dBm Conducted content - -50 dBm Emitted at ENV 50140 Operating Temperature -10 20 55 0C range:

Storage Temperature 30 - 70 0C range:

Notes:

1. Standard Module Frequency. Design permits frequency to be factory selectable within the 458.5125 to 458.90 Mhz band for use under MPT 1329 or MPT 1361.

2. Deviation set for use with NEC 26D pager.

3. Normal current during idle and transmission. Peak current taken at the beginning of transmission. Permitted ripple voltage during transmission is 100 mV.

4. Output power is preset for 1/4 wave aerials of 50 ohm impedance, at 12 volt supply. Standard aerial supplied is 1/4 wave aerial with BNC connection.

5. Unit can be supplied either as an external unit powered from an external unregulated 12V PSU, or supplied for mounting inside the PC when the power is provided through the 4 pin molex connectors from the PC power supply.

The circuit for the pager can be considered to be an intelligent switch between the input and output data from a personal computer serial or parallel port to a RF link. This is used to convert serial data from the computer to the industry standard pager protocol called POCSAG (In practice the reference used for the communication standard created by the Post Office Code Standardisation Advisory Group - now called the Radio Paging Code Standards Group).

This is an economic pager interface for sale into the computer add-on market, nurse call systems, factory call systems or domestic security use. It is designed to meet the market competitively priced providing through fixed options immediate plug and play to the user.

is -21 is

Claims (17)

1. A low power radio frequency transmitter comprising:

reference oscillator providing a signal having a first predetermined frequency; phase lock loop circuit for producing an output at a second predetermined frequency on the basis of the first predetermined frequency; mixing means for modulating the output signal with a data signal for providing a modulated output signal; and output means for outputting the modulated output signal from the transmitter.

2. A transmitter as claimed in claim 1, wherein the output power supplied from the output means is in the range from 1 to 20 milliwatts.

3. A transmitter as claimed in claim 1 or 2, wherein the output power from the output means is in the range 1 to 10 milliwatts.

4. A transmitter as claimed in claim 1, 2 or 3, wherein the second predetermined frequency is in the range 140 to 225 MHz.

5. A transmitter as claimed in any one of the preceding claims, wherein the second predetermined frequency is equal to 173.225 MHz.

6. A transmitter as claimed in any one of the preceding claims, wherein the first predetermined frequency is 8 MHz.

7. A low power radio frequency transmitter, substantially as hereinbefore described with reference to, and as shown in, Figures 2 and 3 of the accompanying drawings.

8. A low power radio frequency receiver comprising:

receiver means for receiving a transmitted radio frequency signal having a carrier frequency, and is including an input filter for producing a filtered signal, and a BiFet amplifier for amplifying the filtered signal, and for substantially isolating the input filter from the remainder of the receiver; oscillator means for producing an oscillating signal having a frequency related to the carrier frequency; mixing means for mixing the received signal and the oscillating signal to produce a mixed signal; and decode means, operable to receive the mixed signal and to produce an output data signal therefrom.

9. A receiver as claimed in claim 8, wherein the carrier frequency is in the range 140 to 225 MHz.

10. A receiver as claimed in claim 8 or 9, wherein the carrier frequency is equal to 173.225 MHz.

11. A receiver as claimed in claim 8, 9 or 10, wherein the decode means comprise:

a first frequency divider, for frequency dividing the mixed signal to produce a lower frequency signal; and a second frequency divider for frequency dividing the lower frequency signal to produce an output signal.

12. A low power radio frequency receiver substantially as hereinbefore described with reference to, and as shown in, Figures 5, 6, 7 and 8 of the accompanying drawings.

13. A low power radio frequency communications system including a transmitter as claimed in amy one of claims 1 to 7, and a receiver as claimed in any one of claims 8 to 12.

14. A low power radio communications systems comprising:

a transmitter including:

a reference oscillator providing a signal having a first predetermined frequency; a phase lock loop circuit for producing an output signal at a second predetermined frequency on the basis of the first predetermined frequency; mixing means for modulating the output signal with a data signal for providing a modulated output signal; and output means for outputting the modulated output signal from the transmitter; and a receiver including: receiver means for receiving a transmitted radio frequency signal having the second predetermined frequency, the receiver means including an input filter for producing a filtered signal and a BiFet amplifier for amplifying the filtered signal and for substantially isolating the input filter from the remainder of the receiver; oscillator means for producing an oscillating signal having a frequency related to the carrier frequency; mixing means for mixing the received signal and the oscillating signal to produce a mixed signal; and decoder means, operable to decode the mixed signal and to produce an output data signal therefrom.

15. A security system including a low power radio communications systems comprising:

a transmitter including: a reference oscillator providing a signal having a first predetermined frequency; a phase lock loop circuit for producing an output signal at a second predetermined frequency on the basis of the first predetermined frequency; mixing means for modulating the output signal with a data signal for providing a modulated output signal; and output means for outputting the modulated output signal from the transmitter; and is a receiver including: receiver means for receiving a transmitted radio frequency signal having the second predetermined frequency, the receiver means including an input filter for producing a filtered signal and a BiFet amplifier for amplifying the filtered signal and for substantially isolating the input filter from the remainder of the receiver; oscillator means for producing an oscillating signal having a frequency related to the carrier frequency; mixing means for mixing the received signal and the oscillating signal to produce a mixed signal; and decoder means, operable to decode the mixed signal and to produce an output data signal therefrom.

16. A paging system for producing paging signals in response to data received from a computer substantially as hereinbefore described.

17. A paging system for a computer substantially as hereinbefore described with reference to, and as shown in, Figure 9 of the accompanying drawings.