GB2331414A

GB2331414A - Monitoring a current-regulating stage

Info

Publication number: GB2331414A
Application number: GB9824419A
Authority: GB
Inventors: Marcel Hachmeister
Original assignee: Robert Bosch GmbH
Current assignee: Robert Bosch GmbH
Priority date: 1997-11-12
Filing date: 1998-11-06
Publication date: 1999-05-19
Anticipated expiration: 2018-11-06
Also published as: JP4298827B2; GB2331414B; GB9824419D0; DE19851732A1; JPH11327666A

Abstract

A method of monitoring at least two current-regulating stages (100, 101-109) for electrical loads (L), wherein the stages each comprise switching means (S) and a current regulator (140) and are each operable so that the respective load conducts current determined by a keying ratio and regulated towards a target value (I 1 , I 2 - I 1 ), comprises the steps of forming the ratio between the keying ratio and the target value of the current-regulating stage to be monitored, and comparing the formed ratio with a comparison value.

Description

1 21331414 METHOD OF AND MONITORING MEANS FOR MONITORING A

CURRENT-REGULATING STAGE 1 The present invention relates to a method of and monitoring means for monitoring at least one current - regul ati ng stage.

A method and a device for monitoring current- regulating stages are known from DE-4 012 109 (US 5 31 138), in particular the monitoring of an output stage in which a load conducts a keyed current with a presettable keying ratio. For fault monitoring. the drive control signal and the voltage present at the junction between the output stage and the load are evaluated. Also known are methods and devices for the monitoring of output stages. in which a current evaluation is carried out.

The determination of threshold values at which faults are recognised entails problems. since the current conducted by a load depends on different parameters. Such parameters are, in particular, operating voltage. operating temperatures of individual components, impedance in the load circuit and other influences. for example contact resistance of plug connections, wiring harness impedance. impedance of the load, measurement resistance and impedance of the output stage. If these tolerances are not taken into consideration, the monitoring becomes very unreliable. but if the tolerances are taken into consideration the monitoring becomes very expensive.

There is therefore a need for a inethod and monitoring means for monitoring current- regulating stages whereby a simple and reliable recognition of faults may be possible.

According to a first aspect of the invention there is provided a method of monitoring at least one current- regulating stage for an electrical load, which stage comprises at least one switching means and a current regulator, wherein the loads are flowed through by a current determined by a keying ratio and the current can be regulated to a target value by the current regulator, characterised in that the keying ratio andlor a magnitude derived from the 2 keying ratio is compared with a threshold value for the monitoring and a fault is recognised in the case of a deviation.

Preferably, a ratio is formed of the keying ratio and the target value and compared with a comparison value, or a current value is determined starting out from the keying ratio and the voltage and compared with a comparison value. For preference, the comparison value is preset starting from at least the ratio between the keying ratio and the target value of at least one of the remaining current-regulating stages. Alternatively, the comparison value is preset starting from the keying ratios and the target values of all remaining currentregulating stages, or is preset starting from the ratio between the sum of the initial keying ratios of all current - regulating stages and the sum of the current target values of all current- regulating stages, or is preset starting from the ratio between the sum of the initial keying ratios of all currentregulating stages and the sum of the current target values of all currentregulating stages with the exception of the values of the current - regulating stage to be checked.

Expediently. the keying ratio is presettable in dependence on the comparison between the target value for the current and an actual value for the current which flows through the load.

According to a second aspect of the invention there is provided a device for monitoring at least two current- regulating stages for electrical loads, which stages each respectively comprise at least one switching means and a current regulator. wherein the loads are each flowed through by a current determined by a keying ratio and the current regulator regulates the current to a target value, characterised in that means are provided which, for the monitoring of a current - regul ati ng stage, form the ratio between the keying ratio and the target value and compare it with a comparison value.

3 The test accuracy in the self-diagnosis of current- regulating stages may be able to be substantially improved by a method exemplifying the invention.

Examples of the method and embodiments of the monitoring means of the present invention will now be more particularly described with reference to the accompanying drawings. in which:

Fig. 1 Fig. 2 Fig. 3 is a schematic block diagram of current-regulating stages for loads and associated monitoring means for monitoring the stages; is a flow chart illustrating steps in monitoring such a stage by a first method exemplifying the invention:

is a flow chart illustrating steps in monitoring such a stage by a second method exemplifying the invention; Figs. 4 and 5 are flow charts illustrating steps in the determination of magnitudes for use in the method of Fig. 3; and Fig. 6 is a flow chart illustrating steps in monitoring such a stage by a third method exemplifying the invention.

Referring now to the drawings. there is shown in Fig. 1 monitoring means for monitoring current- regulating stages used in transmission control, but the method is not restricted to this application and can be used for currentregulating stages for other loads, for example electromagnetic valves by which the fuel feed in an internal combustion engine and/or the flow of a hydraulic fluid, in particular in the case of ABS, ASR or FM systems. is or are regulated. The procedure is applicable preferably when two equal or similar current-regulating stages are present.

In the illustrated embodiment. three current- regulating stages 100, 101 and 109 are shown. The dotted line connecting stages 101 and 109 signifies that any 4 desired number of current- regulating stages can be provided. Also present is a microcontroller 110. which acts on the first currentregulating stage 100 by a first current target value Il, the second current- regulating stage 101 by a second current target value 12 and the third current- regul ati ng stage 109 by a third current target value 11. The microcontroller receives a signal nl from the stage 100, a signal n2 from the stage 101 and a signal nl from the stage 109.

The principal elements of such a current- regulating stage are illustrated in more detail for the stage 100, the other stages being correspondingly formed. The stage 100 comprises a load circuit 120, a signal preparation block 130 and a current regulator 140.

The load circuit comprises a load 1, which is connected.by a first terminal with a supply voltage UB and by a second terminal with a first terminal of a measuring resistance R. The second terminal of the resistance R is connected with a first terminal of switching means S, a second terminal of which is connected with ground. The load L, the resistance R and the switching means S are connected in series. The illustrated sequence of the elements is only by way of example. The anode of a diode D, the cathode of which is connected to the supply voltage UB, is connected to the first terminal of the switching means S.

The second terminal of the load 1 stands in connection with the signal preparation block 130. Both terminals of the resistance R are connected with the regulator 140. The regulator 140 acts on a control terminal of the switching means S by drive control signals. The current target value I1 produced by the microcontroller is applied to the regulator 140. The signal nl. which is processed by the microcontroller, is produced by the signal preparation block 130.

In use, the microcontroller 110 presets the target value I1 for the current regul ator 140. Starting from the voltage drop across the resistance R. the regulator 140 determines the actual value of the current flowing through the load L. On the basis of comparison of this actual value and the target value Il. the regulator 140 determines the drive control signal for the switching means 5. In this case, a keyed drive control preferably takes place. i.e. the switching means S is acted on by a keyed signal at a certain keying ratio. The keying ratio thus depends on the comparison between the target value and the actual value for the current. In dependence on the keying ratio. a corresponding current flows through the load.

The keying ratio can be the ratio between the time during which the switching means S is closed, and the total drive control duration. However, another suitable magnitude can also be used as the keying ratio. for example, the ratio between the time during which the switching means S is closed and the time during which the switching means S is open.

The signal evaluation block 130 evaluates the voltage present at the second terminal of the load L and, starting from this signal, determines the keying ratio nl of the output stage. This keying ratio is termed initial keying ratio nl of the output stage.

This keying ratio is passed on by the block 130 as the signal nl to the microcontroller 110. The same applies to the other current- regulating stages 101 and 109.

Starting from the initial keying ratio nl. the actual value of the current flowing in the load L can be determined by the microcontroller 110. The accuracy with which this takes place, depends on different parameters, for example the operating voltage. the operating temperature of the individual components and the resistive impedance of the entire load circuit.

In a first embodiment, the ratio between the initial keying ratio nl and the target value I1 for the current are utilised for fault monitoring. Due to the significant tolerances of the initial keying ratio, this fault recognition 6 entai 1 s probl ems. Accordingly, voltage influences, temperature influences and impedance influences are eliminated by means of a relative weighting over several current - regulating stages in order to increase the test accuracy for the self-diagnosis of keyed currentregulating stages.

For preference, therefore, the ratio between the target value 11 and the initial keying ratio nI, of the current -regulating stage to be monitored is compared with a preset comparison value VR for the purpose of monitoring that stage. Thi s comparison value VR is formed starting from the target values and the keying ratios of the remaining currentregulating stages. Preferably, a mean value formation is carried out over all stages. Alternatively, the keying ratio of the drive control signal for the switching means S can be used.

It is in that case advantageous that the test accuracy is increased through evaluation of already present signals and data, so that increased expenditure due to additional components does not arise.

The microcontroller computes the relative magnitude nr/Ir according to the following formula from the measured initial keying ratios nk and the current target values Ik, which magnitude serves as a comparison value VR for the normalised initial keying ratio np/1p of the current - regul ati ng stage to be tested:

rik VR = nr = k=i Ir 1 1 Ik k=l This means that the reference value VR is computed from the ratio of the sum of the initial keying ratios nl to nl of all current- regulating stages and the sum of the current target values I1 to I] of all current- regulating stages.

Alternatively, the current target value Ip and the keying ratio np can be excluded from the computation for determination of the reference value VR. In this case, the following formula is used:

7 nr nk) - nP VR - = k=l Ir 1 (1 Ik) - Ip k=l This means that the reference value VR is computed from the ratio of the sum of the initial keying ratios nl to nI of all current -regulating stages and the sum of the current target values I1 to I] of all current - regul ati ng stages, with the exception of the values of the particular current -regulating stage to be monitored.

The normalised initial keying ratio VP = nplIp of the current- regulating stage to be monitored is compared with the reference value VR. If the magnitude np/Ip deviates by more than a permissible tolerance E from the reference value VR, a fault is recognised. In this case. the microcontroller takes appropriate measures in order to bring the system into a safe state.

The tolerance E can be kept small and the test sensitivity can thereby be kept high. The influencing magnitudes of operating voltage, operating temperature of the individual components and absolute impedance in the load circuit can be eliminated by this procedure. Faults, which can be detected with high sensitivity by this procedure, are, for example, impermissible currentregulating deviations or changes in the load circuit impedance due to component faults or ageing.

An example of the procedure is illustrated by way of the flow diagram of Fig. 2. In this example, a counter k is set to 1 in a first step 200. Subsequently, the value nk for the kth current- regulating stage is detected in a step 210. Subsequently. the target value Ik for the kt' stage is detected in a step 220 and the counter k is increased by 1 in a step 230. A subsequent interrogation step 240 checks whether the value k is equal to or greater than 1. The number 1 corresponds with the number of the current- regulating stages to be monitored. If the value k is not equal to or greater than 1, i.e. all values nk and Ik for 8 al 1 stages have not yet been detected. the program returns to the step 210. When all values nk and Ik are detected, a step 250 follows in which the counter p is set to 1. In a subsequent step 260. the ratio VR is computed according to one of the formulae indicated above.

The value Vp, i.e. the ratio between the initial keying ratio np and the current target value Ip of the pM current- regul ati ng stage to be checked, is determined in a subsequent step 265.

A subsequent interrogation step 270 checks whether the amount of the difference between VR and Vp is less than a threshold value c. If this is the case. the counter p is increased by 1 in a step 280. A subsequent interrogation step 285 checks whether the counter p is greater than or equal to 1, thus checks whether all current- regulating stages have been tested. If this is not the case, the program returns to the step 260. If this is the case, the program returns to the step 200. If the interrogation step 270 recognises that the values VR and Vp deviate from each other by more than F_ a fault is recognised in a step 290.

As already mentioned. the load circuit consists of a series connection of an inductive and resistive load R, a measurement resistance R and switching means S. In the case of the load being driven by a rectangular voltage U, the following relationship applies for the steady current I that arises:

I = U/RnK, wherein the keying ratio of the rectangular voltage is represented by magnitude n. In that case. the frequency f of the rectangular voltage, which results from the keying ratio n, must be sufficiently great by comparison with the time constant of the inductance. The total resistance of the load circuit 120 is represented by the value R. The magnitude K is a correction factor which takes into consideration the non-linearities, the deviations from the ideal drive control and the influence of non- linear components. for example freewheel di odes.

9 The resistance R comprises all resistive components of the entire arrangement. This is in particular the resistive component of the load L, the measuring resistance, the contact resistances as well as further resistances. These components are subject to tolerances and as a rule are dependent on temperature. When the temperature is known, these can be taken into consideration. The tolerances of the resistive components essentially determine the height of the recognisable current deviation. This means that for small tolerances. i.e. for small change in dependence on the temperature, faults can be recognised even with small deviations.

For the monitoring of the load circuit, the procedure is as follows: If the keying ratio n and the current I are known, the resistance R is obtained by the fol 1 owi ng formul a:

R = UlIM It is particularly advantageous when the current I is not measured, but the target value is used for the current, which target value is present as internal magnitude in the microcontroller 110.

Starting from the deviation between the target resistance RS and the actually measured resistance R, a fault is recognised when this deviation exceeds a threshold value AR. This means that checking of the resistance takes place with knowledge of the current. Changes in the load circuit can thus be recognised.

This procedure is illustrated in greater detail as a flow diagram by Fig. 3. The keying ratio n, the actually flowing current I or the target value and the voltage U are detected in a first step 300. The supply voltage UB, which as a rule is present in the microcontroller 110. preferably represents the voltage U. The current 1 is the target value Il, which is preset for the current - regul ati ng stage by the microcontroller. The keying ratio n is the keying ratio reported back by the signal preparation block 130.

In a subsequent step 310, the actual resistance R is determined according to the above formula. Subsequently, the deviation AR is determined in a step 320, i.e. the amount of the difference between the computed resistance R and the target resistance RS. This means that the ratio of the keying ratio n and the current I is compared with a comparison value.

A subsequent interrogation step 330 checks whether the difference AR is greater than a threshold value SW. If this is not the case, the program returns to the step 300. If the deviation is greater than the threshold value. a fault is recognised in a step 340.

The target resistance RS is usually dependent on different boundary conditions, in particular on temperature. and therefore is not known with high accuracy. It is consequently particularly advantageous that a value, which is determined starting out from the resistances of the remaining loads, for example setting members. subject to the same boundary conditions, is used as target resistance.

It is also advantageous if, when several loads are present, all resistances are detected and a mean value is formed from these values. Preferably, the resistance, which is checked, is not taken into consideration for the mean value formation. This means that a comparative test takes place, i.e. the resistance value of one load is compared with the resistance values of the remaining loads.

How such a mean value is ascertained is illustrated by the flow chart of Fig. 4. A counter K is set to 1 in a first step 400. In a next step 410, the resistance RK of the Kt' setting member is determined according to the formula:

RK = nkUIIK.

In this case. the current flowing through the Kt' setting member is denoted by IK and the keying ratio acting on the C setting member is denoted by nK.

11 Subsequently, the counter is increased by the value 1 in a step 420. The interrogation step 430 checks whether the counter K is greater than the value L. The value L indicates the number of setting members. If this is not the case, the step 410 is repeated.

If the counter K is greater than 1. which means that the values RK of all setting members have been ascertained. the target resistance RS is computed in a step 440 according to the formula:

L 2: Rk RS = k-1 L It is particularly advantageous if the target resistance RS is learned and/or adapted and optionally also filed in non-volatile manner. Preferably, the ascertaining of the target resistance RS takes place only in the presence of certain conditions. such as when the voltage UB assumes certain values. Moreover, the ascertaining of the resistance preferably takes place when the current I, which flows through the load, lies between a lower and an upper threshold value. Furthermore, it is advantageous to ascertain the target resistance only in a certain temperature range.

This means that the value of the resistance is compared with a measurement value at a selected measurement point.

The ascertaining of the target resistance RS is illustrated by the flow chart of Fig. 5. The program starts in the presence of the certain conditions in a step 500. Subsequent to the detection of the magnitudes N, I and U in a step 510, the target resistance RS is computed in a step 520 according to the formula:

RS = nU/I.

12 After computation of the target resistance RS, the value RS is stored in nonvolatile manner in a step 530.

A particularly advantageous refinement results when the resistance values R is known. so that the actually flowing current I can be computed according to the formul a:

I = nU/R.

Faults can be deduced from the deviation between the current L which was thus computed, and the target value IS for the current. If the deviation is greater than a threshold value, a fault is recognised.

In this example, the ratio between keying ratio n and the voltage U is compared with a comparison value.

In this case, the procedure is as illustrated in Fig. 3. but the magnitude I is replaced by the magnitude R and the magnitude RS by the magnitude I. Consequently, checking of the current takes place with knowledge of the resistance.

In steady operation, i.e. when the voltage U and the target current IS assume constant values, a steady keying ratio n similarly sets in. It is particularly advantageous if the measured keying ratio n in steady operation is compared with the keying ratio previously measured and a fault is recognised in the event of a deviation.

In that case, the difference between the actual keying ratio and a steady keying ratio nS is ascertained. This means that the keying ratio n is compared with a comparison value. The steady keying ratio nS is preferably computed as a function of the preceding keying ratios. Preferably, this takes place by a mean value formation by way of the keying ratios of the last measurements.

13 A corresponding example is illustrated in Fig. 6.

In a first step 600, a counter with value K is set to 1. The keying ratio nK is then detected in a step 610. In a subsequent step 620, the steady keying ratio nS is computed as a function f of the keying ratio nK, the keying ratio nKA and further keying ratios at preceding measurements.

The deviation An between the actual keying ratio nK and the steady keying ratio nS is ascertained in a step 630. The amount of the difference between nK and nS is used as deviation An. A subsequent interrogation step 640 checks whether the deviation An is greater than a threshold value SW. If this is the case. a fault is recognised in a step 650. If this is not the case, the value nK-1 is written over by the value K in the step 600 and the new value nK is detected subsequently in the step 610.

In the case of a particularly simple method, a value nS for the keying ratio is preset starting from different parameters. The actual keying ratio nK is compared with this value. If the two values deviate by more than a threshold value from each other, a fault is recognised. This means that the step 610 is omitted and a fixed value nS is preferably read out from a storage device in the step 620.

It is particularly advantageous if the magnitude K, i.e. the nonlinearity in the relationship between the current I, the resistance R and the voltage U, is taken into consideration. This is advantageous especially for the procedure according to Fig. 3.

14

Claims

1. A method of monitoring a current -regul ati ng stage for an electrical load which conducts current determined by a keying ratio and regulated by the current-regulating stage in dependence on a target value, the method comprising the steps of comparing at least one of the keying ratio and a magnitude dependent thereon with a predetermined threshold value and recognising a fault in dependence on the comparison result.

2. A method as claimed in claim 1, wherein said magnitude is the difference between a predetermined comparison value and the ratio of the keying ratio and the current target value.

3. A method as claimed in claim 1, wherein said magnitude is the difference between a predetermined comparison value and a current value determined in dependence on the keying ratio and voltage.

4. A method as claimed in claim 2 or claim 3. wherein the method is for monitoring a selectable one of a plurality of such stages and the comparison value is the ratio of the keying ratio respective to the selected stage and the current target value respective to another one of the stages.

5. A method as claimed in claim 2 or claim 3, wherein the method is for monitoring a selectable one of a plurality of such stages and the comparison value is predetermined in dependence on the keying ratios and current target values respective to all of the stages except the selected stage.

6. A method as claimed in claim 2 or claim 3, wherein the method is for monitoring a selectable one of a plurality of such stages and the comparison value is predetermined in dependence on the ratio of the sum of the keying ratios respective to all of the stages and the sum of the current target values respective to all of the stages.

7. A method as claimed in claim 2 or claim 3. wherein the method is for monitoring a selectable one of a plurality of such stages and the comparison value is predetermined in dependence on the ratio of the sum of the keying ratios respective to all of the stages except the selected stage and the sum of the current target values respective to all of the stages except the selected stage.

8. A method as claimed in any one of the preceding claims, wherein the keying ratio is the difference between the current target value and the actual value of current conducted by the load.

9. A method substantially as hereinbefore described with reference to Fig. 1 and any one of Figs. 2 to 6 of the accompanying drawings.

10. Monitoring means for monitoring a current- regul ati ng stage for an electrical load which conducts current determined by a keying ratio and regulated by the current- regulating stage in dependence on a target value, the monitoring means being arranged to compare at least one of the keying ratio and a magnitude dependent thereon with a predetermined threshold value and to recognise a fault in dependence on the comparison result.

11. Monitoring means as claimed in claim 10. wherein the magnitude is the difference between a predetermined comparison value and the ratio of the keying ratio and the current target value.

12. Monitoring means substantially as hereinbefore described with reference to Fig. 1 and any one of Figs. 2 to 6 of the accompanying drawings.