GB2330208A

GB2330208A - Integrated circuit with a built-in test mode activation system

Info

Publication number: GB2330208A
Application number: GB9721253A
Authority: GB
Inventors: Kuo-Cheng Yu; Bao-Shiang Sun; Rong-Dzung Tsai
Original assignee: Holtek Microelectronics Inc; Utek Semiconductor Corp
Current assignee: Holtek Microelectronics Inc; Utek Semiconductor Corp
Priority date: 1996-12-23
Filing date: 1997-10-08
Publication date: 1999-04-14
Also published as: DE19747448A1; GB9721253D0

Abstract

An integrated circuit (IC) 30 comprises a test mode activation system 301 which compares two signals S32, S35. A signal S31 is processed in a section 3011 formed within the IC 30 to provide one of the signals S32 whilst the other signal S35 is not processed within the IC. The signals S32, S35 are compared by a section 3012 formed within the IC to establish if they have a predetermined relationship and if they do the system activates the test mode section 302 of the IC 30. The test mode activation system 301 may be enabled by a signal S36 input on a reset terminal of the IC 30. The predetermined relationship may be that the signals are the same or are the inverse of one another. The processing performed in section 3011 of the IC may be some form of encoding possibly involving flip-flop or delay devices. A signal S31 may be generated internally or externally of the IC 30 and external processing means 31 may be involved in providing the other signal S35. The signals S31, S35 may be digital or analog AC signals. The invention prevents accidental and / or unauthorized enabling of the IC into its test mode.

Description

SYSTEM AND METHOD FOR DETECTING A TEST MODE The present invention relates to a method and device for determining on activating a test mode, particularly a test mode of an IC (integrated circuit), in order to provide a high reliability of preventing the IC from entering the test mode during normal application.

In order to assure quality, mass-produced IC usually must be subjected to testing before being put in market for normal application or when confirmation of circuit performance is requested by customers, hence test mode of the mass-produced IC must be activated to enable fast and accurate testing of internal circuits of the mass-produced IC.

In spite of the conveniency to build a test circuit inside an IC for implementing a test mode, extremely special attention must be paid to the prevention of the IC from entering the test mode when it is in normal application.

Although various schemes have been adopted in prior an to provide an IC with a function of distinguishing test mode from normal application, the prior arts leave users in the hope of a better device or scheme because of more or less of their inadequacy. The present invention provides an IC with more stable and more reliable schemes for distinguishing a test mode from normal application.

In prior arts, very often one or more pins are provided for switching between normal application and test mode. For example, an IC will be switched from normal application to test mode when a test pin which is fixed at a certain voltage level (high or low) for n-ormal application is forced to be at another voltage level (low or high). Entering a test mode, the test circuit inside the IC starts to output internal signals and to allow external controlling on internal circuits/signals, so that an external test unit can test the function and/or performance of internal circuits by testing the internal signals outputted from the IC and/or by inputting control signals to the IC.

The advantage of the above prior arts is that the distinction between test mode and normal application is so clear that normal application is unlikely to enter an unexpected test mode, and the disadvantage is the need of extra pin/pins for the switching operation.

It is especially a dilemma when designing an IC of small package, because each pin of an IC of small package usually has to be used for normal application. Moreover, because it is easy to access internal signals through entering test mode by just applying a certain voltage on the test pin, circuit structure of the IC can be easily exposed.

To improve the disadvantage of requiring one or more extra pins according to these prior arts, a scheme of inputting a signal through a certain pin has been adopted for enabling the IC to distinguish when it shall enter the test mode. That is, the test mode of the IC can be activated only if the signal is received and is recognized to meet a certain criterion. With the advantage of requiring no extra pin, however, the scheme is facing a challenge of how to constitute, in order to prevent the IC from entering an unexpected test mode during normal application, such a signal that can't exist or arise under normal application. Because of the variety of operating signal under normal application, it is very hard to assure that no operating signal may happen to be equal to the signal , and hence the scheme is not qu; reliable.

Another scheme suggested by prior arts is to activate the test mode of an IC by enabling the IC to detect if an oscillator is operating, and to activate a test circuit inside the IC according to the detected status of the oscillator. With no much difference from those as described above, the scheme also suffers the danger that an IC may enter an unexpected test mode during normal application.

An object of the present invention is to provide a device and method for activating the test mode of an IC, while preventing, in a reliable way, the IC from entering the test mode during normal application.

Another object of the present invention is to provide a device and method for activating the test mode of an IC, while assuring good security of preventing circuit structure of the IC from being exposed.

A further object of the present invention is to provide a device and method for determining on activating the test mode of an IC without need of an extra pin.

The present invention is related to a recognizing device and recognizing method associated with a test unit, for recognizing a test request of activating a test mode which is applicable to an IC. The test unit is usually set beside the IC for measuring the characteristics and quality of the IC (integrated circuit). The recognizing device is designed to recognize the test request according to a 1st Regenerated Signal and a 2nd Data Signal, and to activate the test mode when and only when the 1 sot Regenerated Signal and the 2nd Data Signal received thereat meet a preset requirement such as a specific relation between the 1st Regenerated Signal and the 2nd Data Signal. For example, the specific relation may be that one is equal to another, or one is a multiple of another, or one is the integrator of another, or one is the complement of another. Clearly the simplest relation is that one is equal to another.

The recognizing device is configured to comprise: a first process circuit for converting the 2nd Data Signal received thereat into a 2nd Regenerated Signal ; and a detection circuit for detecting the relation between the 1 sot Regenerated Signal and 2nd Regenerated Signal received thereat, and for activating a test mode when and only when the detected relation between the I st Regenerated Signal and the 2nd Regenerated Signal meets a preset requirement such as that the 1st Regenerated Signal is equal to the 2nd Regenerated Signal , whereby the test mode is unlikely activated by operating signals arising from normal application. For example, the 2nd Data Signal is the complement of the 1st Regenerated Signal and the first process circuit is a complement circuit (such as a logic inverter), the 1st Regenerated Signal shall be equal to the 2nd Regenerated Signal. Of course the system can be so configured that the 1 sot Regenerated Signal and the 2nd Regenerated Signal are digital signals.

The first process circuit is characterized by its function of converting the 2nd Data Signal into the 2nd Regenerated Signal through partially or entirely delaying, encoding, decomposing and/or reorganizing the 2nd Data Signal, to assure that a signal arising from normal application or applied externally for some reasons is unlikely equal to the 2nd Regenerated Signal. The test unit may comprise a second process circuit for converting a 1st Data Signal applied thereto into the 1 st Regenerated Signal. The second process circuit of the test unit may be characterized by its function of providing the 1 sot Regenerated Signal through partially or entirely encoding. decomposing and/or reorganizing the signal. The detection circuit is characterized by its function of detecting the 1st Regenerated Signal and the 2nd Regenerated Signal received by the recognizing device, and recognizing the relation between the two signals, and outputting an Test Start-Up Signal for activating a test circuit in the IC if and only if the relation between the 1st Regenerated Signal and the 2nd Regenerated Signal meets a preset requirement such as that the 1 sot Regenerated Signal is the same as the 2nd Regenerated Signal It may also be so designed that the first process circuit and detection circuit are enabled to operate when and only when a Enabling Signal is received by the recognizing device, whereby the first process circuit and detection circuit can operate and consume operating power only when the Enabling Signal is received, and of course can not output the 2nd Regenerated Signal and the Test Start-Up Signal unless the Enabling Signal is received and at the same time the detected relation between the I st Regenerated Signal and the 2nd Regenerated Signal does meet the preset requirement, whereby the recognition of a test request for activating the test circuit becomes more accurate and reliable, and less power is consumed.

It must be pointed out that the pin for inputting the Enabling Signal may be the reset pin of the IC which is ordinarily used to input a reset signal for resetting the operation of the IC, and the reset signal may be used as the Enabling Signal if the IC is so designed that another type of input status (such as a transition of voltage level either High to Low or Low to High at the reset pin) can be used to replace the reset signal for an ordinary IC.

It can be understood that the preset requirement for the relation between the 1st Regenerated Signal and the 2nd Regenerated Signal is not limited to "equality", it may also be "multiple" or any condition based on that one can be acquired by processing another through a predetermined circuit such as an integrator or a differentiator or a logic circuit. Obviously the simplest preset requirement for the relation is "equality", and hence the detection circuit can be a comparator for comparing the 1st Regenerated Signal and the 2nd Regenerated Signal (or particularly a digital comparator when the 1st Regenerated Signal and the 2nd Regenerated Signal are digital signals) and for outputting the Test Start-Up Signal when the 1st Regenerated Signal and the 2nd Regenerated Signal are equal (or the same), the Test Start-Up Signal is for driving a test circuit in the IC to activate the test mode of the IC.

It can also be understood that the recognizing device may include a signal generator to be enabled by the Enabling Signal for providing the 2nd Data Signal, and the 1st Data Signal which is inputted to the test unit to be converted into the 1st Regenerated Signal by the second process circuit in the test unit. Obviously it is realizable the 1st Data Signal can also be used as the 2nd Data Signal to be converted into the 2nd Regenerated Signal by the first process circuit. That is, the 1 sot Data Signal may be the same as the 2nd Data Signal.

The second process circuit in the test unit may be configured to complement the first process circuit (such as that the output of the second process circuit is the inverse of the output of the first process output or vice versa), whereby when a 1st Data Signal complementing the 2nd Data Signal is inputted to the second process circuit, the 1st Regenerated Signal provided by the second process circuit in response to the 1st Data Signal is the same as the 2nd Regenerated Signal provided by the first process circuit in response to the 2nd Data Signal.

For example, if the 2nd Data signal = 0101 and the 1st Data Signal = 1010, then it may turn out that the 1st Regenerated Signal is the same as (or equal to) the 2nd Regenerated Signal.

It is obvious that the recognizing device may be installed inside the IC, and the first process circuit may include flip-flops, the first of which inputs the 2nd Data Signal as its clock signal for producing a first output, the second of which inputs the first output for producing a second output, the third of which inputs the second output for producing a third output and so on. No matter how many flip-flops there are, their outputs may constitute the 2nd Regenerated Signal.

Actually the first process circuit may comprise a group of N (N: integer and N > l) flip-flops in which the first flip-flop for inputting the 2nd Data Signal and for producing a first output signal in response to the 2nd Data Signal , and the Mth (M: integer and 1 < M < N) flip-flop for inputting the (M-l)th output signal and producing a Mth output signal in response to the (M- I )th output signal, whereby the first output signal and the (M-l)th output signal as well as the Mth signal constitute the 2nd Regenerated Signal Similarly the second process circuit may include flip-flops of the same connection to input the 1st Data Signal and convert it into the 1st Regenerated Signal. For example, the first process circuit may comprise a group of N (N: integer and N > 1) flip-flops in which the first flip-flop for inputting the 1 sot Data Signal and for producing a first output signal in response to the 1st Data Signal , and the Mth (M: integer and I < M < N) flip-flop for inputting the (M-l)th output signal and producing a Mth output signal in response to the (M-l)th output signal, whereby the first output signal and the (M- l)th output signal as well as the Mth signal constitute the 1st Regenerated Signal.

It is also obvious that 1 sot Regenerated Signal and 2nd Regenerated Signal can be either serial type or parallel type, and either the flip-flops in the first process circuit or those in the second process circuit may be of T type. Surely these flip-flops are not limited to T type and all the signals referred to in the embodiment are not limited to either serial type or parallel type.

The recognizing device may further comprise a multiplexer for enabling at least one pin of the IC to be shared by the test mode and normal application of the IC. For example, a pin of the IC outputs, during normal operation, an oscillating signal produced by an oscillator therein the IC while switches, when and only when the Enabling Signal is received by the multiplexer, to output the 1st Data Signal generated by the signal generator which is installed inside the IC. The 1st Data Signal is in turn inputted to the second process circuit in the test unit and converted into the 1st Regenerated Signal.

The signal generator included in the recognizing device and enabled by the Enabling Signal to provide the 2nd Data Signal and the 1st Data Signal may comprise: a primary circuit for producing a primary signal; a status generator for converting the primary signal into a status signal; a signal encoder for converting the status signal into the 2nd Data Signal and the 1st Data Signal by encoding the status signal.

It must be noticed that- one of the other aspects of the present invention is a recognizing device including the test unit.

It shall be realizable the present invention can be embodied as a method comprising the following steps: a first conversion step for converting the 2nd Data Signal into a 2nd Regenerated Signal ; a detection step for detecting the relation between the 1st Regenerated Signal and the 2nd Regenerated Signal ; and an activate step for activating, when the detected relation between the 1 sot Regenerated Signal the 2nd Regenerated Signal meets a preset requirement such as that the 1 sot Regenerated Signal is the same as the 2nd Regenerated Signal the test mode of the integrated circuit.

The method may further comprise an enabling step of providing a Enabling Signal to enable the first conversion step and the detection step, and a preparatory conversion step of generating a 1 st Data Signal and converting the 1 sot Data Signal into the 1 st Regenerated Signal Obviously it can be so designed that the detection step activates the test mode of the integrated circuit when the 1st Regenerated Signal and the 2nd Regenerated Signal detected by the detection step are equal, and that the detection step further comprises a step of providing a signal to a test circuit inside the integrated circuit to activate the test mode of the integrated circuit.

It can be understand the method may further comprise one step of switching one pin of the integrated circuit between the modes of outputting the I st Data Signal and outputting an operating signal used for normal application.

The present invention may best be understood through the following description with reference to the accompanying drawings, in which: Fig. 1 shows block diagrams of the first preferable embodiment of the present invention.

Fig. 2a and Fig. 2b illustrate the first process circuit and second process circuit of the first preferable embodiment of the present invention.

Fig. 2c illustrate the signal wavefonns for the inputs and outputs of the first process circuit and second process circuit of the first preferable embodiment of the present invention.

Fig. 3 shows block diagrams of the second preferable embodiment of the present invention.

Fig. 4 illustrates the circuit of the signal generator of the second preferable embodiment of the present invention.

Fig. 5 shows block diagrams of the third preferable embodiment of the present invention.

Fig. 6 shows the flow chart for the first preferable embodiment of the present invention.

Fig. 7 shows the flow chart for the second preferable embodiment of the present invention.

INTRODUCTION TO SOME REFERENCE NUMERALS or SYMBOLS In Fig. 1: 10 = integrated circuit; 101 = recognizing device as a first preferable embodiment according to the present invention; sll = 2nd Data Signal , externally applied to 101; s12 = 2nd Regenerated Signal (signal provided by first process circuit); s13 = 1 sot Data Signal , externally applied to second process circuit; s14 = 1st Regenerated Signal from second process circuit to detection circuit; s15 = Enabling Signal (signal for enabling detection circuit and first process circuit); s16 = Test Start-Up Signal outputted from detection circuit to activate test circuit; In Fig. 2a: FF 1, FF2, FF3 are respectively first flip-flop, second flip-flop, third flip-flop in the second process circuit; QO, Q1, Q2 are respectively the outputs of first flip-flop, second flipflop, third flip-flop; SE = enabling signal provided by test unit to enable QO, Q1, Q3; s13 = 1st Data Signal s13 inFig. 1; s14 = 1st Regenerated Signal s14 in Fig. 1.

In Fig. 2b: FF4, FF5, FF6 are respectively fourth flip-flop, fifth flip-flop, sixth flip-flop of the first process circuit; Q3, Q4, Q5 are respectively the outputs of fourth flip-flop, fifth flipflop, sixth flip-flop; sIl =2nod Data Signal sll in Fig.l; s12 = 2nd Regenerated Signal s12 in Fig. I; s15 = Enabling Signal s15 in Fig. 1.

In Fig. 2c: sll = 2nd Data Signal sll in Fig. 1; Q3 = output of the flip-flop FF4 in Fig. 2b; Q4 = output of the flip-flop FF5 in Fig. 2b; Q5 = output of the flip-flop FF6 in Fig. 2b; In Fig. 3: 20 = integrated circuit; 201 = recognizing device as a second preferable embodiment according to the present invention; s2 1 = 2nd Data Signal , provided by signal generator; s22 = 2nd Regenerated Signal (signal provided by first process circuit); s23 = 1st Data Signal , applied to second process circuit from signal generator; s24 = 1 sot Regenerated Signal, from second process circuit to detection circuit; s25 = Enabling Signal (signal for enabling detection circuit and first process circuit as well as signal generator); s26 = Test Start-Up Signal outputted from detection circuit to activate test circuit; In Fig. 4: s27 = primary signal generated by the signal generator shown in Fig. 3; s28 = status signal; s21/s23 = 2nd Data Signal /1sot Data Signal shown in Fig. 3, both are generated by signal generator shown in Fig. 3; In Fig. 5: 30 = integrated circuit; 301 = recognizing device as a third preferable embodiment according to the present invention; s31 = 2nd Data Signal, provided by signal generator 3013, one branch is applied to first process circuit, another branch is applied to second process circuit; s32 = 2nd Regenerated Signal (signal provided by first process circuit); s33 = selection signal, applied to multiplexer 3014 for switching output pin P32 between normal application and test mode (or activating test mode) of the IC; s34 = an operating signal for normal application of the IC; s35 = 1st Regenerated Signal, outputted from second process circuit to detection circuit; s36 = Enabling Signal (signal for enabling detection circuit and first process circuit as well as signal generator); s37 = Test Start-Up Signal outputted from detection circuit to activate test circuit.

Fig. 1 shows block diagrams for a test unit 11, and an IC (integrated circuit) 10 comprising a recognizing device 101 and a test circuit 102. Recognizing device 101 includes a first process circuit 1011 with an input port Pull, and a detection circuit 1012. IC 10 further comprises an input pin P12 capable of inputting an enabling or reset signal S15. The test unit 11 to be used for testing the internal quality and features of IC 10 includes a second process circuit 111 with an input pin P13. Operation of the block diagrams in Fig. 1 is described hereinafter.

The recognizing device 101 starts to work when and only when signal S1 5 is inputted to IC 10 and received by first process circuit 1011 and detection circuit 1012, therefore recognizing device 101 can be prohibited from operating (specifically activating test mode ofIG10) when signal SIS is not applied to pin P12. When signal Sl5 is applied to pin P 12 and received by first process circuit 1011, first process circuit 1011 is enabled to receive si I inputted at P1 l, and to convert si 1 into a s12, and to output s12 to detection circuit 1012. On the other hand, When signal S15 is applied to pin P12, it is also received by detection circuit 1012, and hence detection circuit 1012 is enabled to receive s12 from first process circuit 1011 and s14 from second process circuit 111 through pin (port in case s14 is a parallel signal) P17, and to detection if s12 is the same as s14 (or if the relation between s12 and s14 meets a preset requirement), and to output a s16, when and only when s12 is the same as s14 (or when the relation between s12 and s14 meets a preset requirement), for activating test circuit 102 which in turn enables IC10 to enter test mode. S14 is formed in second process circuit 111 by converting a s13 inputted at pin Pl3. Of course IC 10 shall be always in normal applicatin unless test circuit 102 is activated by s16. Signal S14 or s12 can be either serial type or parallel type, and detection circuit 1012 may choose one or more bits of s12 and s14 for comparing if they meet the "equality" relation. It can be seen that s12 and s14 are unlikely the same unless second process circuit 111 in test unit 11 and first process circuit 1011 of recognizing device 101 installed in IC 10 are specially designed.

For example, if sl 1 and s13 are the same, second process circuit 111 must be the same as first process circuit 1011 which is in IC 10.

Security to prohibit the IC from entering an unexpected mode is thus achieved. If second process circuit 111 and first process circuit 1011 are so designed that they complement each other (such as that one is the inverse of the other), and sl I and s13 also complement each other (such as that si 1 = 1101 and s13 = 0010), s12 and s14 can still turn to be the same to meet the preset requirement of equality between s12 and s14, and hence act as a test request for activating the test mode of IC 10, whereby the security to prohibit circuit structure from being exposed can thus be reinforced.

It can be realized the first process circuit may comprise an encode process circuit for converting the 2nd Data Signal into the 2nd Regenerated Signal by encoding the 2nd Data Signal . It can also be realized the first process circuit may comprise different circuits for converting the 2nd Data Signal into the 2nd Regenerated Signal by delaying, decomposing, encoding, and/or reorganizing the 2nd Data Signal . Of course the converting may also be the c.nbination of the delaying, decomposing, encoding, and/or the reorganizing.

Obviously the second process circuit may also con prise an encode process circuit for converting the 1 sot Data Signal into the 1 sot Regenerated Signal by encoding the 1 sot Data Signal . It can also be realized the second process circuit may comprise different circuits for converting the 1 sot Data Signal into the first signal by delaying, decomposing, encoding, and/or reorganizing the 1 sot Data Signal . Of course the converting may also be the combination of the delaying, decomposing, encoding, and/or the reorganizing.

An example to convert ? serial signal into a parallel signal in second process circuit 111 and first process circuit 1011 is shown in Fig. 2a and 2b from which the conversion of a signal into another signal through decomposing, encoding, and reorganizing can also be seen. Illustrated in Fig. 2a is second process circuit 111 comprising flip-flop FFl for inputting s13 as its clock signal and for outputting Q0 in response to s13; and FF2 for outputting Q 1 in response to QO received from OFF 1 as a clock input and FF3 for outputting Q2 in response to Q1 received from FF2 as a clock input. Signal QO, Q1, Qc can constitute s14 which is to be inputted to IC 10 through pin 17. Pin 17 is used to input an operating signal when the IC is in normal application. Configuration can be so made that these flip-flops are enabled to operate only when an enable signal SE provided by test unit 11 is received. Similarly flip-flops FF4, FF5, FF6 illustrated in Fig. 2b are included in first process circuit 1011 for converting sll into s12 under the condition the Enabling Signal slS is received. Based on the same structure as that shown in Fig. 2a, si 1 is inputted to FF4 as a clock input, and outputs Q4, Q5, Q6 of FF4, FF5, FF6 constitute s12 which in turn is sent to detection circuit 1012. All of these flip-flops may be of T type.

Shown in Fig. 2c is an example that sll of the serial form: 11001010 is converted into s12 through the circuit structure shown in Fig. 2b where Q3, Q4, Q5 constitute s12 of parallel form. Obviously the configuration provides better way to prohibit circuit structure from being exposed to those skilled in the art.

As mentioned above, pin P17 for inputting s14 and pin P12 for inputting s14 can be shared by normal application, and hence only pin P11 is the extra pin required solely for the test mode or activating the test mode. It can be seen now the present invention, without need of more extra pin than prior art, can provide good realibility of preventing an IC from entering unexpected test mode while offer good security of prohibiting the exposure of circuit structure.

Please refer to Fig. 3 now for another embodiment of the present invention. Shown in Fig. 3 are test unit 21 including second process circuit 211 with pin 23 to input s23, and IC 20 including test circuit 202 and recognizing device 201. Recognizing device 201 comprises detection circuit 2012, first process circuit 2011 with pin P21 for inputting s21, signal generator 2013, pin Pge for inputting s25 to signal generator 2013, and pin P22 for inputting Enabling Signal s25 to detection circuit 2012 and first process circuit 2011. Detection circuit 2012, first process circuit 2011, test circuit 202, second process circuit 211, s21, s24, s23, s25, s22, s26 are respectively equivalent to detection circuit 1012, first process circuit 1011, test circuit 102, second process circuit 111, s1 1, s14, s13, s15, s12, s16 shown in Fig. 1, and have no need to be explained again here.

Now please take notice of the difference between Fig. 3 and Fig. 1.

Recognizing device 201 in Fig. 3 further comprises signal generator 2013 installed outside of IC 20. In response to Enabling Signal s25, signal generator 2013 produces and outputs s2 1 and s23 to be respectively received by first process circuit 2012 and second process circuit 211, and in turn respectively converted into s22 and s24. Test Start-Up Signal s26 is outputted to test circuit 202 by detection circuit 2012 when s22 and s24 are detected as the same or the detected relation between s22 and s24 meets a preset requirement. Test mode of IC 20 is thus activated by Test Start-Up Signal s26 received by test circuit 202.

One embodiment of signal generator 2013 is shown in Fig.4 where signal generator 2013 includes a signal generating circu encoder 20133 for providing, through encoding s28, second process circuit 211 and first process circuit 2011 respectively with s23 and s2 1 Obviously it can so designed that s23 is the same as s2 1.

Shown in Fig. 5 is the third preferable embodiment of the present invention in which test unit 31, test circuit 302, first process circuit 3011 with port (instead of pin) P3 1 for inputting signal s31 which may be either parallel type or serial type, detection circuit 3012, pin P34 for inputting Enabling Signal s36, second process circuit 311 with port (instead of pin) P33 for inputting signal s3 1 which may be either parallel type or serial type, and signal generator 3013, respectively corresponds to test unit 21, test circuit 202, first process circuit 2011 with port for inputting s21, detection circuit 2012, pin P22 for inputting Enabling Signal s25, second process circuit 211 with port P23 for inputting s23, and signal generator 2013 of Fig. 3, and hence need no further discussion.

The difference between Fig. 3 and Fig. 5, however, must be explained. As can be seen from the two figures, the configuration that signal generator 2013 is installed outside IC 20 according to Fig. 3 is so changed that signal generator 3013 of Fig. 5 is now installed inside IC 30, and a multiplexer 3014 is further included in recognizing device 301 according to Fig. 5. Multiplexer 3014 is inside IC 30, and is configured for enabling the sharing of one pin P32 of IC 30 by both the outputting of s31 (required for test mode or for activating test mode) and the outputting of an operating signal s34 (required for normal application). In response to a selection signal s33 from signal generator 3013, multiplexer 3014 with s31 and s34 as input signals will select s31 to be outputted through pin P32 for test mode operation or activating test mode, while select s34 to be outputted through pin P32 for normal application.

Apparently if the signal outputted through pin P32 is s3 1, it may be the signal to be inputted to second process circuit 311 for converting into a signal s35 which in turn is sent to detection circuit 3012.

Meantime another branch of s31 is inputted to first process circuit 3011 for converting into another signal s32 to be received by detection circuit 3012. It must be pointed out that s31 in Fig. 5 functions as both of s21 and s23 in Fig. 3 or as both sll and s13 in Fig. I. Obviously s31 in Fig. 5 functions as both of 2nd Data Signal and 1 sot Data Signal.

It can be seen now that detection circuit 3012, under the condition it receives Enabling Signal s36, will be in normal operation to receive the two signal s s32 and s35 and to detect the relation between the two signal s, and to output Test Start-Up Signal s37 when the relation is "equality" for example, as preset. In case there's no Enabling Signal s36, detection circuit 3012 stops normal operation, and meantime signal generator 3013 either stops providing selection signal s33 or alters selection signal s33, to make multiplexer 3014 switch back to the selection of s34 for normal application. Test circuit 302 inside IC 30 is activated when receiving Test Start-Up Signal s37 which is outputted from detection circuit 3012 when and only when there is Enabling Signal s36 and the detected signal s s36 and s32 meet a preset relation such as "equality". One of the better schemes to configure the embodiment is that s34 is the oscillating signal provided by the oscillator of IC 30, and hence pin P32 is the output pin of the oscillator when IC 30 is in normal application.

No matter how the present invention is embodied, the test unit may or may not be included in the recognizing device.

Shown in Fig. 6 and Fig. 7 are flow charts to respectively illustrate the processes for implementing the first and the third embodiment of the present invention based on the recognizing devices respectively shown in Fig. 1 and Fig. 5. Obviously the difference between Fig. 6 and Fig. 7 can be realized by comparing the block diagrams shown in Fig. 1 and Fig. 5. Reference numerals/symbols in Fig. 6 and Fig. 7 are illustrated as follows: In Fig. 6: step 61 = is the Enabling Signal (Enabling Signal s15 in Fig. 1) being received ? step 62 = input the 2nd Data Signal (sl l in Fig. 1) and convert it into the 2nd Regenerated Signal (signal s12 in Fig. 1); step 63 = input the 1st Regenerated Signal (s14 in Fig. 1); step 64 = detect if the relation between 2nd Regenerated Signal s12 and 1st Regenerated Signal s14 meets a preset requirement (such as that 2nd Regenerated Signal s12 is the same as 1st Regenerated Signal s14)? step 65 = enter test mode; step 66 = maintain normal application.

In Fig. 7: step 71 = is the Enabling Signal (Enabling Signal s36 in Fig. 5) being received? step 72 = generate the 1 sot Data Signal which is the same as the 2nd Data Signal (s31 in Fig. 5); step 73 = generate a selection signal ( s33 in Fig. 5); step 74 = switch the common pin of the IC to the mode of outputting the I st Data Signal s31 from that of outputting a normal operating signal s34; step 75 = output 1st Data Signal s31 to a test unit 31 to be converted into the 1st Regenerated Signal (s35 in Fig. 5); step 76 = input the 1st Regenerated Signal s35 from the test unit; step 77 = convert the 2nd Data Signal (the same as the 1st Data Signal s31 shown in Fig. 5) into the 2nd Regenerated Signal s32; step 78 = detect if the relation between 2nd Regenerated Signal s32 and 1st Regenerated Signal s35 meets a preset requirement (such as that 2nd Regenerated Signal s32 is the same as 1 sot Regenerated Signal s35)? step 79 = enter test mode; step 80 = maintain normal application.

It can be realized the step 62 in Fig. 6 and/or the step 75 in Fig. 7 and/or the step 77 in Fig. 7 may comprise one or more steps selected from among delaying, encoding, decomposing, and reorganizing its input signal.

It is clear now from the above description, that the present invention provides, without need of increasing significant cost, improvements on the disadvantages inherent in the conventional art which is usually subjected to the problems such as need of extra pin/pins, poor circuit confidence protection, and lower reliability.

While the invention has been described in terms of what are presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.

Claims

CLAIMS 1. A recognizing device for determining, according to a 1st Regenerated Signal provided by a test unit and a 2nd Data Signal applied thereto, on activating the test mode of an integrated circuit, comprising: a first process circuit for converting said 2nd Data Signal into a 2nd Regenerated Signal; a detection circuit for receiving and comparing said 1st Regenerated Signal and said 2nd Regenerated Signal , and for activating the test mode of said integrated circuit when said 1 sot Regenerated Signal is equal to said 2nd Regenerated Signal.
2. The recognizing device according to claim 1 wherein said 1st Regenerated Signal and said 2nd Regenerated Signal are digital signals.
3. The recognizing device according to claim 1 wherein said detection circuit is a digital comparator.
4. The recognizing device according to claim 1 wherein said first process circuit comprises an encode process circuit for converting said 2nd Data Signal into said 2nd Regenerated Signal by encoding said 2nd Data Signal.
5. The recognizing device according to claim 1 wherein said first process circuit comprises a reorganize circuit for converting said 2nd Data Signal into said 2nd Regenerated Signal by decomposing and reorganizing said 2nd Data Signal.
6. The recognizing device according to claim 1 wherein said first process circuit comprises a reorganize circuit for decomposing said 2nd Data Signal into a component signal and encoding said component signal into said 2nd Regenerated Signal.
7. The recognizing device according to claim 1 wherein said first process circuit comprises at least one flip-flop for inputting said 2nd Data Signal and for producing said 2nd Regenerated Signal in response to said 2nd Data Signal.
8. The recognizing device according to claim 1 wherein said first process circuit comprises a group of N (N: integer and N > 1) flip-flops in which the first flip-flop for inputting said 2nd Data Signal and for producing a first output signal in response to said 2nd Data Signal, and the Mth (M: integer and 1 < MsN) flip-flop for inputting said (M-l)th output signal and producing a Mth output signal in response to said (M-l)th output signal, whereby said first output signal and said (M I)th output signal as well as said Mth signal constitute said 2nd Regenerated Signal.
9. The recognizing device according to claim 8 wherein said flip-flops are T type of flip-flops.
10. The recognizing device according to claim 1 wherein said 1 sot Regenerated Signal is a signal of serial type.
11. The recognizing device according to claim 1 wherein said 2nd Regenerated Signal is a signal of serial type.
12. The recognizing device according to claim 1 wherein said 1 sot Regenerated Signal is a signal of parallel type.
13. The recognizing device according to claim 1 wherein said 2nd Regenerated Signal is a signal of parallel type.
14. The recognizing device according to claim 1 wherein said detection circuit further for providing a Test Start-Up Signal when said 1st Regenerated Signal is the same as 2nd Regenerated Signal , said Test Start-Up Signal being for driving a test circuit in said integrated circuit to activate the test mode of said integrated circuit.
15. The recognizing device according to claim 1 receiving a Enabling Signal applied thereto for enabling said first process circuit to convert said 2nd Data Signal into a 2nd Regenerated Signal , and for enabling said detection circuit to receive and compare said 1st Regenerated Signal and said 2nd Regenerated Signal , whereby said first process circuit and said detection circuit consume operating power only when said Enabling Signal is received, and the test mode of said integrated circuit can be activated only when said Enabling Signal is received, whereby the normal application of said integrated circuit can be very reliably prevented from entering unexpected test mode.
16. The recognizing device according to claim 1 wherein said 1st Regenerated Signal is provided by a second process circuit in said test unit, said second process circuit complements said first process circuit, whereby when said 2nd Data Signal is inputted to said first process circuit to be converted into said 2nd Regenerated Signal, and a 1 st Data Signal complementing said 2nd Data Signal is inputted to said second process circuit to be converted into said 1st Regenerated Signal, said 1 sot Regenerated Signal is equal to said 2nd Regenerated Signal.
17. The recognizing device according to claim 16 further comprising a signal generator for providing said 2nd Data Signal to said first process circuit and said 1 st Data Signal to said second process circuit.
18. The recognizing device according to claim 15 wherein said signal generator comprises: a primary circuit for producing a primary signal; a status generator for converting said primary signal into a status signal; a signal encoder for converting said status signal into said 2nd Data Signal and said 1st Data Signal by encoding said status signal.
19. The recognizing device according to claim 15 being installed inside said integrated circuit.
20. The recognizing device according to claim 19 receiving said Enabling Signal through the reset pin of said integrated circuit.
21. The recognizing device according to claim 17 receiving a Enabling Signal applied thereto for enabling said signal generator to provide said 2nd Data Signal and said 1 st Data Signal.
22. The recognizing device according to claim 20 wherein said Enabling Signal received through said reset pin is a voltage of a certain level applied to said reset pin.
23. The recognizing device according to claim 21 further comprising a multiplexer for enabling one common pin of said integrated circuit to be shared by the test mode and the normal application of said integrated circuit.
24. The recognizing device according to claim 23 wherein said multiplexer enables said common pin to output said 1st Data Signal only when said Enabling Signal is received by said recognizing device.
25. The recognizing device according to claim 23 further comprising an oscillator for generating an oscillating signal, and wherein said multiplexer enables said common pin to output, for normal operation, said oscillating signal.
26. The recognizing device according to claim 1 further comprising a test unit capable of providing said 1 sot Regenerated Signal.
27. The recognizing device according to claim 26 wherein said test unit comprises a second process circuit for inputting a 1 sot Data Signal applied thereto and for converting said 1st Data Signal into said 1st Regenerated Signal.
28. The recognizing device according to claim 27 wherein said second process circuit comprises an encode process circuit for converting said 1 sot Data Signal into said 1st Regenerated Signal by encoding said 1st Data Signal.
29. The recognizing device according to claim 27 wherein said second process circuit comprises at least one flip-flop for inputting said 1 sot Data Signal and for producing said 1st Regenerated Signal in response to said 1 st Data Signal.
30. The recognizing device according to claim 27 wherein said second process circuit comprises a group of N (N: integer and N > 1) flip-flops in which the first flip-flop for inputting said 1 St Data Signal and for producing a first output signal in response to said 1st Data Signal , and the Mth (M: integer and l < McN) flip-flop for producing a Mth output signal in response to said (M-l)th output signal, whereby said first output signal and said (M-l)th output signal as well as said Mth output signal constitute said I st Regenerated Signal
31. The recognizing device according to claim 30 wherein said flipflops are T type of flip-flops.
32. A method for determining, according to a 1st Regenerated Signal and a 2nd Data Signal , on activating the test mode of an integrated circuit including a test circuit therein, comprising a first conversion step for converting said 2nd Data Signal into a 2nd Regenerated Signal; a detection step for comparing said 1st Regenerated Signal and said 2nd Regenerated Signal; an activate step for activating, when said 1 sot Regenerated Signal is the same as said 2nd Regenerated Signal , the test mode of said integrated circuit.
33. The method according to claim 32 further comprising an enabling step of providing a Enabling Signal to enable said first conversion step and said detection step.
34. The method according to claim 32 further comprising a preparatory conversion step of generating a 1 sot Data Signal inside said integrated circuit and converting, outside said integrated circuit, said 1st Data Signal into said 1st Regenerated Signal
35. The method according to claim 34 wherein said 1st Regenerated Signal , said 2nd Data Signal , said 2nd Regenerated Signal , and said Enabling Signal are digital signals of serial type.
36. The method according to claim 34 wherein said 1st Regenerated Signal , said 2nd Data Signal, said 2nd Regenerated Signal , and said Enabling Signal are digital signals of parallel type.
37. The method according to claim 32 wherein said detection step further comprises a step of converting said 1 sot Regenerated Signal into a signal of parallel type if said 1st Regenerated Signal is a signal of serial type and said 2nd Regenerated Signal is a signal of parallel type.
38. The method according to claim 32 wherein said detection step further comprises a step of converting said 1 st Regenerated Signal into a signal of serial type if said 1 sot Regenerated Signal is a signal of parallel type and said 2nd Regenerated Signal is a signal of serial type.
39. The method according to claim 32 wherein said detection step further comprises a step of converting said 1 st Regenerated Signal and said 2nd Regenerated Signal into a signal of the same type, whereby said 1st Regenerated Signal and said 2nd Regenerated Signal can be compared.
40. The method according to claim 32 wherein said activate step further comprises a step of providing signal to said test circuit when said 1 sot Regenerated Signal is the same as said 2nd Regenerated Signal.
41. The method according to claim 34 wherein said 1st Data Signal is equal to said 2nd Data Signal.
42. The method according to claim 34 wherein said 1st Data Signal is different from said 2nd Data Signal.
43. The method according to claim 34 further comprising a step of switching one pin of said integrated circuit between the mode of outputting said 1 st Data Signal and the mode of outputting an operating signal used for normal application.
44. The method according to claim 34 wherein in said preparatory conversion step, the step of converting said 1st Data Signal into said 1st Regenerated Signal comprises a step of encoding said 1 sot Data Signal.
45. The method according to claim 34 wherein in said preparatory conversion step, the step of converting said I st Data Signal into said I st Regenerated Signal comprises a step of delaying said 1 sot Data Signal.
46. The method according to claim 34 wherein in said preparatory conversion step, the step of converting said 1 sot Data Signal into said 1 sot Regenerated Signal comprises a step of decomposing said 1 sot Data Signal.
47. The method according to claim 34 wherein in said preparatory conversion step, the step of converting said 1st Data Signal into said 1st Regenerated Signal comprises a step of decomposing said 1 st Data Signal into a component signal and reorganizing said component signal into said 1st Regenerated Signal.
48. The method according to claim 34 wherein in said preparatory conversion step, the step of converting said 1 sot Data Signal into said 1 sot Regenerated Signal further comprises a step of decomposing said 1 sot Data Signal into a component signal and encoding said component signal into said 1 st Regenerated Signal
49. The method according to claim 34 wherein in said preparatory conversion step, the step of converting said I st Data Signal into said 1 sot Regenerated Signal comprises at least two steps selected from among delaying, decomposing, encoding, and reorganizing said 1 sot Data Signal
50. The method according to claim 32 wherein said conversion step further comprises at least one step selected from among delaying, decomposing, encoding, and reorganizing said 2nd Data Signal.
51. The device substantially as hereinbefore described with reference to the accompanying drawings as shown.
52. The method substantially as hereinbefore described with reference to the accompanying drawings as shown.