GB2328773A - Addressing a liquid crystal display - Google Patents

Abstract

A greyscale ferroelectric liquid crystal device is driven by a set of data signals each of which corresponds to a grey level. Each signal comprises first and second signal portions of opposite polarity which sum to substantially zero in order to provide d.c. balance. Each signal portion comprising first and second pulses having magnitudes V1 and V2 such that RMS voltage V1<2>+V2<2> is substantially constant for the different data signals. Such data waveforms provide a stable greyscale response and substantially uniform power consumption.

Description

"Matnx Array Bistable Device Addressings This invention relates to the addressing of matrix array bistable devices, such as ferroelectric liquid crystal display devices.

Liquid crystal devices incorporating ferroelectric smectic liquid crystal material (FLCD's) are suitable for use in displays and shutters in which their fast switching times and memory characteristics are of advantage. Furthermore they are particularly suitable for use in high resolution display applications including high definition television (HDTV) panels. However such applications require the display to be capable of producing a large number of grey levels, for instance 256 grey levels.

Although digital methods involving spatial dither (SD) and temporal dither (TD) are known for producing grey levels in FLCD's, such methods alone are not generally suitable for producing a such a large number of grey levels in a practical panel, for the reason that the use of SD and TD alone to produce such a large number of grey levels can give rise to problems due to the resulting increase in drive frequency or manufacturing complexity.

It is also possible to produce grey levels using analogue or multithreshold (MT) methods. MT methods make use of a number of discrete threshold levels within a picture element (pixel) whereas analogue methods use an essentially continuous threshold variation over a pixel. In order to limit the problems introduced by use of digital methods, therefore, it is advantageous to combine such analogue or MT methods with digital methods for producing grey levels so as to enable a large number of grey levels to be produced in a practical panel. For example two bits of TD weighted in the ratio 1:16 may be combined with sixteen linearly spaced grey levels produced by an analogue or MT method to provide the required total number of 256 grey levels.

However the introduction of such grey levels produced by analogue or MT methods can give rise to addressing problems. In a conventional display comprising a matrix of pixels formed at intersections between row and column electrodes extending on opposite sides of the liquid crystal material, strobe signals are applied sequentially to the row electrodes and data signals are supplied simultaneously to the column electrodes in synchronism with the strobe signals so that the image to be displayed is reproduced on the display a row at a time. During the period in which a given row is addressed, a strobe pulse is applied to the row and data pulses are applied to the columns with the switching state of each pixel along the row being determined by the resultant of the corresponding strobe and data pulses. In the simplest case, two data waveform types are used which, in combination with the strobe pulse, yield either a switching or a non-switching resultant. If analogue or MT grey levels are used within a pixel, it will be appreciated that more than two data waveform types are required.

Furthermore, before and after the addressing of each row, the pixels within it are subjected to arbitrary data pulses corresponding to the data waveforms used for addressing adjacent rows, and these can modify the switching characteristics of the pixels in dependence on the switching states of the pixels of the adjacent rows, that is in dependence on the pixel pattern. If the addressing scheme used has a narrow operating window, then for some pixel patterns the discrimination between the switching and non-switching states can be reduced or even lost. Where intermediate data waveform types are used to produce analogue grey levels, a wide operating window is required for proper discrimination and any narrowing of the operating window can cause lack of controllability of the intermediate grey levels. The drive frequency can also vary with variation in the pixel pattern which can in turn lead to temperature variation over the panel and further lack of controllability of the grey levels due to the strong temperature dependence of the driving characteristics of FLCD's.

European Patent Application No. 95307751.8 discloses an addressing method for an FLCD which is intended to reduce the pixel pattern dependence of the grey levels by using a set of data waveforms for addressing the different analogue grey levels in which each data waveform is d.c. balanced, and all the data waveforms have the same RMS voltage and the same polarity behaviour with time. However it has been found that the data waveforms proposed in that application do not allow sufficient controllability of the grey levels due to the strong monostability dependent on the data waveform type. This lack of controllability may be due to the asymmetrical shape and different polarity behaviour of the first half of each data waveform.

Furthermore the power consumption has been found to vary with the data waveform type which can cause temperature variation over the panel and further variation in the grey level displayed.

It is an object of the invention to provide an improved method of addressing a matrix array bistable device enabling a large number of transmission levels, e.g. grey levels, to be obtained in a controllable manner.

According to the present invention there is provided a matrix array bistable device comprising a plurality of strobe electrodes, a plurality of data electrodes, a matrix of modulating elements formed at intersections between the data electrodes and the strobe electrodes, a strobe signal generator for supplying strobe signals sequentially to the strobe electrodes, and a data signal generator for supplying any selected one of a plurality of different data signals to each data electrode to control the switching state of one of the modulating elements formed at the intersection of said data electrode and one of the strobe electrodes in association with the strobe signal supplied to said strobe electrode, wherein each of the data signals comprises first and second signal portions of opposite polarity which sum to substantially zero in order to provide d.c. balance, each signal portion comprising first and second pulses having magnitudes Vl and V2 such that the RMS voltage v,2 + V22 is substantially constant for the different data signals.

In order that the invention may be more fully understood, reference will now be made, by way of example, to the accompanying drawings, in which: Figure 1A is a diagrammatic section through a ferroelectric liquid crystal display device; Figure 1B shows the waveform of a typical data signal for use in such a display device in accordance with the invention; Figures 2A and 2B diagrammatically show two alternative sets of data waveforms which may be used to obtain 16 grey levels in such a display device; Figure 3 is a schematic diagram of such a display device; Figure 4 is a timing diagram showing typical strobe and data waveforms used in such a display device; Figure 5 is a graph of the transmission level against the normalised data voltage Vd in the first time slot in operation of such a display device; Figure 6 is a graph of the data voltage Vd against the strobe voltage Vs showing the drive window available in operation of such a display device, Figure 7 being a similar graph showing the pixel pattern dependence of the drive window; Figure 8 diagrammatically shows a set of data waveforms for obtaining 16 grey levels in a known display device; Figure 9 is a graph of the data voltage Vd against the strobe voltage Vs showing the drive window available in operation of such a known display device, Figure 10 being a similar graph showing the pixel pattern dependence of the drive window; Figure 11 is a graph showing variation of the transmittance with time in operation of both devices; and Figure 12 is a graph showing variation of the power index with the data waveform for both devices.

The preferred embodiments of the invention to be described below relate to a ferroelectric liquid crystal display (FLCD) device 10, as shown diagrammatically in Figure lA,comprising a layer 1 of ferroelectric liquid crystal in the smectic phase of the type having a minimum in its TV characteristic, such as SCE8 available from Hoechst AG, contained between two glass substrates 2 and 3 arranged parallel to one another and bearing first and second electrode structures on their inside surfaces. The first and second electrode structures comprise respectively a series of data and strobe electrodes 11 and 12 arranged in columns and rows and intersecting one another at right angles to form an addressable matrix of modulating elements (pixels). The electrodes may alternatively be arranged to form a polar coordinate (r,O) matrix, a seven bar numeric matrix or some other x-y matrix.

Furthermore alignment layers 4 and 5 are provided on insulating layers 6 and 7 applied on top of the data and strobe electrodes 11 and 12, so that the alignment layers 4 and 5 contact opposite sides of the ferroelectric liquid crystal layer 1 which is sealed at its edges by a sealing member 8. The thickness of the liquid crystal layer 1 is approximately 1.5 m with the parallel rubbed alignment layers 4 and 5 providing approximately 50 of surface tilt. The panel 10 is disposed between polarisers 9 and 9A having polarising axes which are substantially perpendicular to one another.

As is well known the pixels are addressable by the application of suitable data and strobe signals to the intersecting data and strobe electrodes 11 and 12 by means of a data signal generator 13 and a strobe signal generator 14. The data signal generator 13 has a data input 15 for receiving image data to be displayed on a row-by-row basis, a synchronising input 16 being provided to receive timing signals so as to control the timing of the supply of data signals to the data electrodes 11 and the timing of the supply of strobe signals to the strobe electrodes 12.

However it should be appreciated that the invention also has application to other forms of display device, as well as to other types of matrix array bistable device.

In the preferred embodiments of the invention to be described below the display device is addressed by data waveforms of the general form shown in Figure 1, that is comprising four rectangular pulses A, B, C and D in consecutive time subslots of equal duration, where the pulses A and B are of negative polarity, the pulses C and D are of positive polarity and the sum of all four pulses is substantially zero in order to provide d.c. balance. Also the voltage -Vl of the first pulse A is of equal magnitude but opposite polarity to the voltage V, of the third pulse C, and the voltage -V2 of the second pulse B is of equal magnitude but opposite polarity to the voltage V2 of the fourth pulse D. It will be appreciated that a set of such data waveforms having different values of Vl and V2 may be applied in order to display different grey levels.

However, the RMS voltage should remain the same for the different data waveform types, which relationship may be expressed as follows: V,2 + V22 = constant for all values of Vl and V2 of the different data waveform types.

Figure 2A is a diagram showing the form of a set of data waveforms which may be used for addressing such a display device to display 16 grey levels, numbered 1 to 16 in the figure, where 1 denotes the black state and 16 denotes the white state and the other waveforms produce intermediate grey states. In this case the voltage of the first pulse A increases in magnitude from 0.0 to -1.0 from the waveform 1 to the waveform 16, and the voltage of the third pulse C increases in magnitude from 0.0 to 1.0 from the waveform 1 to the waveform 16. On the other hand the voltage of the second pulse B decreases in magnitude from -1.0 to 0.0 from the waveform 1 to the waveform 16, and the voltage of the fourth pulse D decreases in magnitude from 1.0 to 0.0 from the waveform 1 to the waveform 16. Nevertheless, for each one of the 16 data waveform types, the basic relationships between the voltages of the pulses A, B, C and D and their magnitudes Vl and V2 referred to above continue to apply so as to provide d.c. balance within each waveform and so that the RMS voltage of the waveforms remains constant.

Figure 2B is a diagram showing the form of a set of data waveforms which may be used in an alternative embodiment of the invention to display 16 grey levels.

In this case the first and second pulses A and B are of positive polarity, and the third and fourth pulses C and D are of negative polarity. Furthermore the voltage of the first pulse A decreases in magnitude from 1.0 to 0.0 from the waveform 1 to the waveform 16, and the voltage of the third pulse C decreases in magnitude from -1.0 to 0.0 from the waveform 1 to the waveform 16, whereas the voltage of the second pulse B increases in magnitude from 0.0 to 1.0 from the waveform 1 to the waveform 16, and the voltage of the fourth pulse D increases in magnitude from 0.0 to -1.0 from the waveform 1 to the waveform 16. Since the waveforms of Figure 2B are simply inverted versions of the waveforms of Figure 2A, however, it will be appreciated that the same basic relationships apply to the voltages of the pulses A, B, C and D and their magnitudes V1 and V2 as are discussed above.

Figure 4 is a diagram illustrating the timing and waveforms of the data and strobe signals used in addressing of such a display device, with particular reference to the strobe and data waveforms for addressing four display pixels Pll, pal2, P21, and p, in adjacent columns and rows of a display panel comprising a large number of such pixels. The strobe signals Vsl, Vs2 are supplied sequentially to adjacent strobe electrodes 12 (scan lines) with the strobe signal Vs2 being delayed with respect to the strobe signal Vsl by the select period 17. Each strobe signal comprises a reset pulse 18 and a strobe pulse 19 separated by a null level. At the same time as the strobe signals are applied to the scan lines, data signals, such as Vdl, Vd2, are applied to the data electrodes 11 (the signal lines) with the data signals consisting of sequences of data waveforms of different types corresponding to the grey levels to be displayed by the pixels in consecutive scan lines, such as the pixels p11, P21. The strobe signal incorporates a reset pulse 18 at the beginning of each addressing frame which acts to set all the pixels along the scan line to the same initial state, that is to erase the previous states of the pixels. The application of the reset pulse 18 ahead of the strobe pulse 19 forces all the pixels along the scan line to switch from any preceding state to the dark state, independently of any preceding pixel pattern. Furthermore the application of the strobe pulse 19 some periods after the reset pulse 18 acts, in association with the data waveform 20 applied to the pixel during the corresponding select period 17, to produce a resultant voltage which is such as to switch the pixel to the state determined by the particular data waveform 20.

It will be appreciated that the data signals comprise data waveforms corresponding to the image data to be displayed on application of the strobe pulse 19 applied to a corresponding scan line during the select period 17. Thus, for example, the data signal may comprise a first data waveform in a time slot to to t, for controlling the state of a pixel along one scan line, a second data waveform in a time slot t, to t2 for controlling the state of a pixel along an adjacent scan line, a third data waveform in the time slot t2 to t3 for controlling the state of a pixel along a further scan line, and so on for further scan lines. Furthermore each time slot is divided into four equal subslots, corresponding to the four pulses A, B, C and D of each data waveform as shown in Figure 1. During its active time slot, the strobe signal has zero level for the first subslot and a predetermined level Vs for the second, third and fourth subslots.

It will be appreciated that, depending on the particular data waveform selected, for example from the set of waveforms shown in Figure 2A, the pixel is either maintained in its existing state or is changed to a different state such that the selected state of the pixel corresponds to any of the possible sixteen grey levels which may be displayed Figure 5 is a graph of the transmission level as a function of the normalised voltage Vd in the first time slot to to t, of Figure 4 using the data waveforms shown in Figure 2B. The voltage Vd is normalised with respect to the maximum data voltage.

In the case of data waveform 1 of Figure 2B denoting the black state, the normalised waveform consists of pulses of 1.0V, 0.OV, -1.0V and 0.0V so that the normalised voltage Vd in the first time slot is 1.0V. In this case, if the maximum data voltage is 5V, the actual voltages of the four pulses of the waveform 1 are 5.OV, 0.0V, -5.0V and 0.0V respectively. Furthermore, in the case of the waveform 16 denoting the white state, the actual voltages of the four pulses are 0.OV, 5.0V, 0.0V and -5.0V respectively, whereas the normalised voltage Vd in the first time slot is 0.0V. The further data waveforms between 1 and 16 have normalised voltages Vd in the first time slot having intermediate values between 0.0V and 1.or. For example the waveform 7 comprises pulses whose actual voltages are 3.0V, 4.0V, -3.0V and A.0V and has a normalised voltage Vd in the first time slot of 0.6V. As shown by the graph of Figure 5, the data waveform 7 produces a transmission level of about 14% (= 18/128). The transmission levels corresponding to the other waveforms are also shown in the graph of Figure 5. This graph demonstrates the greyscale obtainable in a controllable manner by use of such data waveforms. A similar greyscale is obtainable by use of the data waveforms of Figure 2A.

Figure 6 is a graph of the normalised data voltage Vd as a function of the strobe voltage Vs using the drive waveforms of Figure 4, as the voltage Vs is changed from 25V to 45V. During measurement of the data voltage Vd to obtain this graph, the select period (line address time) was fixed at 22 msec, and the display panel having 512 scan lines had an external temperature controlled at 300C. Two sets of measurements were used to obtain the 0% and 100% switching curves G and H, the curve H corresponding to the maximum Vd which will not completely switch the pixels even if the applied data waveform is that which is most likely to switch the pixels, and the curve G corresponding to the minimum Vd which will completely switch the pixels even if the data waveform applied is that which is least likely to switch the pixels. The graph shows the drive window available for switching between the 0% and 100% switching curves G and H.

Figure 7 shows the pixel pattern dependence of the drive window utilising four pixel patterns denoted PP-1, PP-2, PP-3 and PP4. The pixel pattern PP-1 denotes repeated application of the data waveform 16 for all frames, the pixel pattern PP-2 denotes repeated application of the data waveform 16 up to and including the select period followed by repeated application of the data waveform 1 after the select period for each frame, pixel pattern PP-3 denotes repeated application of the data waveform 16 prior to the select period followed by repeated application of the data waveform 1 beginning with the select period for each frame, and the pixel pattern PP9 denotes repeated application of the data waveform 1 for all frames.

For the purposes of comparison, Figure 8 shows a known set of data waveforms and uses the same references A, B, C and D as in Figure 1 to denote the four pulses in consecutive time subslots of each waveform (even though, as will be appreciated, the data waveforms of Figure 8 are of a generally different type to the waveforms of Figure 1). These known data waveforms are such that d.c. balance is maintained within each waveform, although the polarity behaviour of the waveforms differs and furthermore the RMS voltage varies between the different waveforms.

Figure 9 is a graph showing the data voltage Vd as a function of the strobe voltage Vs utilising the known data waveforms of Figure 8 but otherwise using similar operating parameters to the graph of Figure 6.

Comparison of the graph of Figure 9 using the known data waveforms with the graph of Figure 6 using the data waveforms of Figure 2B according to the invention indicates that the data waveforms of Figure 2B produce a wider drive window in the region of higher data voltage Vd in which the apparent tilt angle becomes large due to the ac. stabilisation effect and the contrast ratio increases. Figure 10 shows the pixel pattern dependence of the drive window when the known data waveforms of Figure 8 are used with pixel patterns denoted PP-1, PP-1', PP-2, PP-3, PP-3' and PPA. The pixel patterns PP-l' and PP-3' correspond to the pixel patterns PP-1 and PP-3 except that, in the latter case, different switching behaviour was observed due to the strobe pulses, so that the switching curves associated with PP-1 and PP-3 correspond to the switching behaviour due to the combined effect of the reset pulse and the strobe pulse, whereas the curves associated with PP-1' and PP-3' correspond to the switching behaviour due to the reset pulse only. Below the PP-1' and PP-3' curves, the resultant waveforms obtained by combining the reset pulse and the pixel patterns of the data waveforms were not able to completely initialise the states of the pixels. In this case the data waveform 1 consists of four pulses of 1.0V, 1.0V, -1.0V and -1.0V, and the data waveform 16 consists of four pulses of 0.0V, 0.0V, 1.4V and -1.4V. It will be noted that the known data waveforms give different drive windows depending on the particular pixel pattern. Similar pixel pattem dependence is observed for intermediate states obtained by partial switching within the intermediate region between the 0% and 100% switching limits.

Figure 11 shows, for both the data waveforms of Figure 2B and the known data waveforms of Figure 8, the variation of the transmittance (the optical transmission level expressed as a percentage of the maximum transmission level, that is the white state) over a sequence of addressing frames starting from an initial intermediate level corresponding to an intermediate data waveform at an operating temperature of 40 C.

In this graph the points denoting the transmittance in successive frames for the data waveforms of Figure 2B are indicated by X and the points denoting the transmittance in successive frames for the known data waveforms are indicated by Y. This graph clearly indicates the stability of the greyscale response of a display device using the data waveforms of Figure 2B.

Figure 12 shows the variation of the power index obtained in use of the data waveforms 1 to 16 of Figure 2B, as compared with the corresponding known data waveforms of Figure 8. Since the power consumption is proportional to the square of the voltage amplitude, the power index is the sum of the squares of the voltages of the constituent pulses of each waveform. In the case of a data waveform consisting of four pulses of voltages Vl, V2, V3 and V4 of the same width, the power index is defined as 2 2 (Vl V4)2 + (V2 - V1) + (V3- V2)2 + (V4 - V3)2. The power index provides a reasonable indication of the actual power consumption in use. Points denoting the power index corresponding to each waveform type of the data waveforms of Figure 2B are indicated by Z in the graph, whereas the points denoting the power index corresponding to the waveform types of the known data waveforms are indicated by W. It will be appreciated from this graph that the data waveforms of Figure 2B provide uniform power consumption for the different waveform types, whereas the power consumption will vary in dependence on the waveform type in the case of the known data waveforms of Figure 8.

Claims (11)

1. A matrix array bistable device comprising a plurality of strobe electrodes, a plurality of data electrodes, a matrix of modulating elements formed at intersections between the data electrodes and the strobe electrodes, a strobe signal generator for supplying strobe signals sequentially to the strobe electrodes, and a data signal generator for supplying any selected one of a plurality of different data signals to each data electrode to control the switching state of one of the modulating elements formed at the intersection of said data electrode and one of the strobe electrodes in association with the strobe signal supplied to said strobe electrode, wherein each of the data signals comprises first and second signal portions of opposite polarity which sum to substantially zero in order to provide d.c. balance, each signal portion comprising first and second pulses having magnitudes Vl and V2 such that the RMS voltage V12 + V22 is substantially constant for the different data signals.

2. A device according to claim 1, wherein the plurality of different data signals comprise n different data signals for switching the modulating elements between n different switching states, where n is an integer greater than 2.

3. A device according to claim 2, where the plurality of different data signals comprises 16 different data signals for switching the modulating elements between 16 different switching states.

4. A device according to claim 1, 2 or 3, wherein the first and second pulses of each signal portion of each data signal are of substantially equal duration.

5. A device according to claim 5, wherein the first and second signal portions of each data signal are of substantially equal duration, the first pulse of the first signal portion being of equal magnitude and duration to the first pulse of the second signal portion and the second pulse of the first signal portion being of equal magnitude and duration to the second pulse of the second signal portion.

6. A device according to claim 4 or 5, wherein the first pulse precedes the second pulse in each signal portion of each data signal.

7. A device according to any preceding claim, wherein each of the different data signals comprises a rectangular waveform.

8. A device according to any preceding claim, wherein the modulating elements constitute display pixels which are switchable between n different transmission levels, where n is an integer greater than 2.

9. A device according to claim 8, wherein the n different data signals for producing the n different transmission levels are such that, considering the data signals in order of increasing transmission level, the voltage of the first pulse of each signal portion decreases in magnitude and the voltage of the second pulse of each signal portion increases in magnitude over the different data signals.

10. A device according to any preceding claim, which is a ferroelectric liquid crystal display device.

11. A method of addressing a matrix array bistable device comprising a plurality of strobe electrodes, a plurality of data electrodes, and a matrix of modulating elements formed at intersections between the data electrodes and the strobe electrodes, the method comprising supplying strobe signals sequentially to the strobe electrodes and supplying any selected one of a plurality of different data signals to each data electrode to control the switching state of one of the modulating elements formed at said intersection of the data electrode and one of the strobe electrodes in association with the strobe signal supplied to said strobe electrode, wherein each of the data signals comprises first and second signal portions of opposite polarity which sum to substantially zero in order to provide d.c. balance, each signal portion comprising first 2 2 and second pulses having magnitudes Vl and V2 such that the RMS voltage V1 + V22 is substantially constant for the different data signals.