GB2327326A - Vertical dynamic focusing circuit for a multi-mode monitor - Google Patents

Vertical dynamic focusing circuit for a multi-mode monitor Download PDF

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Publication number
GB2327326A
GB2327326A GB9811973A GB9811973A GB2327326A GB 2327326 A GB2327326 A GB 2327326A GB 9811973 A GB9811973 A GB 9811973A GB 9811973 A GB9811973 A GB 9811973A GB 2327326 A GB2327326 A GB 2327326A
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United Kingdom
Prior art keywords
signal
resistor
amplifier
lamp
dynamic focusing
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB9811973A
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GB9811973D0 (en
Inventor
Sang-Yean Woo
Yun-Seong Hwang
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WiniaDaewoo Co Ltd
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Daewoo Electronics Co Ltd
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Publication of GB9811973D0 publication Critical patent/GB9811973D0/en
Publication of GB2327326A publication Critical patent/GB2327326A/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N3/00—Scanning details of television systems; Combination thereof with generation of supply voltages
    • H04N3/10—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
    • H04N3/16—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by deflecting electron beam in cathode-ray tube, e.g. scanning corrections
    • H04N3/26—Modifications of scanning arrangements to improve focusing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N3/00—Scanning details of television systems; Combination thereof with generation of supply voltages
    • H04N3/10—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
    • H04N3/16—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by deflecting electron beam in cathode-ray tube, e.g. scanning corrections
    • H04N3/22—Circuits for controlling dimensions, shape or centering of picture on screen
    • H04N3/23—Distortion correction, e.g. for pincushion distortion correction, S-correction
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N3/00—Scanning details of television systems; Combination thereof with generation of supply voltages
    • H04N3/10—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
    • H04N3/16—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by deflecting electron beam in cathode-ray tube, e.g. scanning corrections
    • H04N3/27—Circuits special to multi-standard receivers

Abstract

The vertical dynamic focussing circuit includes a ramp signal controlling section 100 for amplifying a first ramp signal CS1 in accordance with its frequency, thus generating a second ramp signal CS2. The second ramp signal CS2 passes to a vertical dynamic focusing signal generating section 200 having an amplifier 211 for amplifying the second ramp signal CS2, a signal integrating unit 220 for converting the amplified signal to an integrated, paraboloid signal and a superimposing unit 230 for superimposing the integrated signal on a direct voltage supplied from a flyback transformer and for outputting a vertical dynamic focussing signal.

Description

VERTICAL DYNAMIC FOCUSING CIRCUIT FOR A MONITOR BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a monitor, and more particularly to a vertical dynamic focusing circuit for a monitor capable of maintaining constant amplitude(peak to peak voltage of a vertical dynamic focusing signal.
2. Description of the Prior Art In a conventional monitor, an electron emitted from a cathode of a Cathode Ray Tube(CRT) is accelerated in accordance with a voltage applied to a grid terminal and then is deflected by a magnetic field generated by a deflection coil. The deflected electron collides with a phosphor screen, so a picture is formed.
The CRT is supplied with a heating voltage of about 6.3V, a focusing grid voltage and screen grid voltage both of which are supplied to a grid terminal for focusing the emitted electron, and a high voltage of about 25KV supplied to an anode terminal for accelerating the emitted electron.
At that time, the emitted electron is defocused at the edge of a picture, so the quality of the picture deteriorates.
In order to enhance the deteriorated quality of the picture, the CRT is supplied with a focusing signal of parabola.
The focusing signals are classified into a static focusing signal and a dynamic focusing signal. An amplitude of the static focusing signal is fixed in accordance with the fixed frequency of the horizontal synchronization signal and the amplitude of the dynamic focusing signal varies with the frequency of the horizontal synchronization signal changed.
Further, the amplitude of dynamic focusing signal increases as the size of the picture increases.
FIG.1 is a view for showing a construction of a vertical dynamic focusing circuit for a conventional monitor. In FIG.
1, reference numeral 1 denotes an amplifying unit for amplifying a lamp signal CS of sawtooth waveform which corresponds to the frequency of the horizontal synchronization signal. Further, reference numeral 2 denotes a signal converting unit for integrating the amplified signal of the amplifier 1 and for generating an integrating signal of parabola. Furthermore, reference numeral 3 denotes a superimposing unit for amplifying the integrating signal, for superimposing the amplified signal on a direct current (DC) voltage supplied from a flyback transformer(FBT), to thereby output a vertical dynamic focusing signal, and for supplying the vertical dynamic focusing signal to a mixing unit M.
The construction of the vertical dynamic focusing circuit for a conventional monitor will be described in more detail.
The lamp signal CS is supplied to one end of a capacitor C. The capacitor C blocks a component of direct current therethrough. The other end of the capacitor C is connected to one end of a resistor R, so that the output signal of the capacitor C flows through the resistor R. Further, the other end of the resistor R is connected to the positive side(+) of an amplifier 11 of the amplifying unit 1.
A voltage Vcc is supplied to one end of the resistor 12 for dividing the voltage Vcc, and the other end of the resistor 12 is connected to one end of a resistor 13. Also, the other end of the resistor 12 is connected to the negative side(-) of the amplifier 11 and the other end of the resistor 13 is grounded.
One end of a resistor 14 for determining an amplifying ratio of the amplifier 11 is connected between the one end of the resistor 12 and the output side of the amplifier 11. And the output side of the amplifier 11 is connected to one end of a resistor 15 for bypassing an amplified signal.
The other end of the resistor 15 is connected to the negative side(-) of an amplifier 21 of the signal converting unit 2. And an externally supplied voltage Vcc is supplied to one end of a resistor 22 for dividing the externally supplied voltage Vcc, and the other end of the resistor 22 is connected to one end of a resistor 23. The other end of the resistor 22 is connected to the positive side(+) of the amplifier 22.
Also, the other end of the resistor 23 is grounded.
Further, the output side of the amplifier 22 is connected to one end of a resistor 24 for bypassing the output signal of the amplifier 22, and the other end of the resistor 22 is connected to one end of a resistor 25 and one end of a capacitor 26 for converting the output signal of the resistor 24 to an integrating signal of parabola. The other end of the capacitor 26 is grounded, and the other end of the resistor 25 is connected to the negative side(-) of the amplifier 21.
In the meantime, one end of a capacitor 27 for determining the amplifying degree of the amplifier 21 is connected between the negative side(-) of the amplifier 21 and the output side thereof.
Further, the output side of the amplifier 21 is connected to one end of a capacitor 28 for blocking the direct component of the output signal of the amplifier 21, and the other end of the capacitor 28 is connected to one end of a resistor 29 for bypassing the output signal of the capacitor 28.
The input side of the externally supplied voltage Vcc is connected to one end of a resistor 31 of the superimposing unit 3 for superimposing the integrating signal on the voltage Vcc. And the other side of the resistor 31 is connected to the other end of the resistor 29.
Furthermore, the other end of the resistor 31 is connected to the base side of a transistor 32 for amplifying the integrating signal. The base side and emitter side of the transistor are connected to one end of each of the resistors 33 and 34, respectively. The other end of each of the resistors 33 and 34 is grounded.
A direct voltage DC supplied from a flyback transformer (not shown) is supplied to the anode of a diode 35 for rectifying the direct voltage DC, and the cathode of the diode 35 is connected to one end of a capacitor 36 and a resistor 37 for smoothing the output signal of diode 35. The other end of the capacitor 36 is grounded.
Further, the other end of the resistor 37 and the collector side of the transistor 32 are connected to a common point, and the common point is connected to one end of a capacitor 38 for superimposing the output voltage of the resistor 37 on the output signal of the transistor 32, for smoothing the superimposed signal, and for outputting the vertical dynamic focusing signal. And the one end of the capacitor 38 is connected to the mixing unit M for mixing the vertical dynamic focusing signal and a horizontal dynamic focusing signal and for supplying a mixing signal to the CRT.
FIG. 2A and FIG. 2H are views for showing output signals from each of the units of FIG. 1.
In connection with the conventional dynamic focusing circuit as described above, the amplitude of the lamp signal CS which is the sawtooth waveform is about 2.5 V, as shown in FIG. 2A, when the frequency of the vertical synchronization(Sync) signal is low(about 50Hz) and the amplitude of the lamp signal CS is about 2.5 V, as shown in FIG. 2B, when the frequency of the vertical synchronization(Sync) signal is high(about 120Hz).
Such lamp signal CS is supplied to the amplifier 11 of the amplifying unit 1 through the resistor R and the capacitor C, so the amplifier 11 amplifies the output signal of the resistor R in accordance with the magnitude of the voltage Vcc and the resistances of the resistors 12 and 13. The amplifying degree of the amplifier 11 is determined with the resistances of the resistors 13 and 14.
The amplitude of the amplified signal cf the amplifier 11 is about 2.5(1+R12/R13)V, as shown in FIG. 2C, when the frequency of the vertical sync signal is low(about 50Hz). And amplitude of the amplified signal of the amplifier 11 is about 2.5(1+R12/R13) V, as shown in FIG. 2D, when the frequency of the vertical sync signal is about 120Hz. Here, the R12 and the R13 denotes the resistances of the resistors 12 and 13, respectively.
The amplified signal of the amplifier 11 is supplied to the amplifier 21 through the resistor 15, so the amplifier 21 rectifies the amplified signal of the amplifier 21 in accordance with a limit voltage which is set by the resistance of the resistors 22 and 23.
The output signal of the amplifier 21 is supplied to the resistor 25 and the capacitor through the resistor 24, so the resistor 25 and the capacitor 26 integrate the output signal of the amplifier 21 and generate an integrating signal of parabola. The amplifying degree of the integrating signal is determined by the capacitance of the capacitor 27.
The amplitude of the integrating signal is about 14.5V, as shown in FIG. 2E, when the frequency of the vertical sync signal is low(about 50Hz). And amplitude of the integrating signal is about 5V, as shown in FIG. 2F, when the frequency of the vertical sync signal is about 120Hz The integrating signal of the amplifier 21 is supplied to the capacitor 28, so the capacitor blocks the direct component of the output signal of the amplifier 21. The output signal of the capacitor is supplied to the resistor 31 through the resistor 29, so the resistor 31 superimposes the output signal of the capacitor 28 on voltage Vcc. And the superimposed signal is supplied to the transistor 32 of the superimposing unit 3.
The transistor 32 inverts and amplifies the superimposed signal. The amplifying degree is determined by the resistances of the resistors 33 and 34.
In the meantime, the direct voltage DC supplied from the flyback transformer is supplied to a diode 35, so the diode 35 rectifies the output signal of the flyback transformer. The output voltage of the diode 35 is supplied to the capacitor 36, so the capacitor 36 smooths the output voltage of the diode 35.
Further, the output voltage of the capacitor 36 is superimposed on the output signal of the transistor 32 supplied through the resistor 37, and the superimposed signal is supplied to the capacitor 38, so the capacitor 38 smooths the superimposed signal and outputs the vertical dynamic focusing signal.
The amplitude of the vertical dynamic focusing signal is about 160V, as shown in FIG. 2G, when the frequency of the vertical sync signal is about 50Hz. And amplitude of the vertical dynamic focusing signal is about 60V, as shown in FIG. 2H, when the frequency of the vertical sync signal is about 120Hz.
The vertical dynamic focusing signal of the capacitor 38 s supplied to the mixing unit M, so mixing unit M mixes the smoothed signal of the capacitor 38 with the horizontal dynamic focusing signal. The mixed signal is supplied to the grid terminal of the CRT.
In other words, in order to enhance the quality of a picture at the right and left edges, the horizontal dynamic focusing signal, as shown in FIG. 3A, is supplied to the mixing unit M, and in order to enhance the quality of a picture at the up and down edges, the vertical dynamic focusing signal, as shown in FIG. 3B, is supplied to the mixing unit M. At that time, the amplitude of the vertical dynamic focusing signal is approximately 150V and the amplitude of the horizontal dynamic focusing signal is about 300V.
However, in a conventional vertical dynamic focusing circuit for a monitor, the amplitude of the vertical dynamic focusing signal is about 160V when the frequency of the vertical sync signal is about 50Hz, and the amplitude of the vertical dynamic focusing signal is about 60V when the frequency of the vertical sync signal is about 120Hz.
Accordingly, the higher the frequency that the vertical sync signal increases, the more the quality of the picture may deteriorate.
SUMMARY OF THE INVENTION Therefore, it is an object of an embodiment of the present invention to ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ provide a vertical dynamic focusing circuit for a monitor, wherein an amplitude of vertical dynamic focusing signal is hanged in accordance with the frequency of the vertical sync signal capabie of enhancing quality of a picture.
According to the present invention, vertical dynamic focusing circuit for a monitor includes a lamp signal controlling section for amplifying an externally supplied first lamp signal in accordance with the frequency of the first lamp signal and for outputting a second lamp signal; and a vertical dynamic focusing signal generating section having an amplifying unit for amplifying the second lamp signal in accordance with a second voltage, a signal converting unit for converting the amplified signal to an integrating signal of parabola, and a superimposing unit for superimposing the integrating signal on a direct voltage supplied from a flyback transformer and for outputting a vertical dynamic focusing signal.
According to the preferred embodiment of the present invention, the externally supplied first lamp signal is supplied to the lamp signal controlling section which increases lower the amplitude of the first lamp signal when the frequency of the vertical sync signal than that of the first lamp signal when the frequency of the vertical sync signal is high and outputs the second lamp signal.
Additionally, the second lamp signal is supplied to the vertical dynamic focusing signal generating section which converts the second lamp signal to the integrating signal of parabola and superimposes the integrating signal on a direct voltage supplied from flyback transformer and outputs the superimposed signal.
Consequently, the amplitude of the first lamp signal is changed in accordance with the frequency of the vertical sync signal, so the amplitude of the vertical dynamic focusing signal is constant. Therefore, the quality of a picture can be enhanced.
BRIEF DESCRIPTION OF THE DRAWINGS The above objects and other advantages of the present invention will become more apparent by describing in detail preferred embodiments thereof with reference to the attached drawings in which: FIG. 1 is a view for showing a construction of the conventional vertical dynamic focusing circuit for a monitor; FIG. 2A to FIG. 2H are waveform timing diagrams to aid in explaining the operation of the conventional vertical dynamic focusing circuit for a monitor; FIG. 3A and FIG. 3B are views for showing a horizontal dynamic focusing signal and vertical dynamic focusing signal supplied to a CRT in a conventional monitor; FIG. 4 is a view for showing a construction of the vertical dynamic focusing circuit for a monitor according to one embodiment of the present invention; FIG. 5A to FIG. 5N are waveform timing diagrams to aid in explaining the operation of the vertical dynamic focusing circuit for a monitor according to one embodiment of the present invention; FIG. 6 is view for showing a construction of the vertical dynamic focusing circuit for a monitor according to another embodiment of the present invention; and FIG. 7A to FIG. 7J are waveform timing diagrams to aid in explaining the operation of the vertical dynamic focusing circuit for a monitor according to another embodiment of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A vertical dynamic focusing signal for a monitor according to one embodiment of the present invention will be described in more detail with reference to the accompanying drawings.
FIG. 4 is a view for showing a construction of the vertical dynamic focusing circuit for a monitor according to one embodiment of the present invention. In FIG. 4, reference numeral 100 denotes a lamp signal controlling section for amplifying a first lamp signal CSl in accordance with the frequency of the first lamp signal CS1 and for generating a second lamp signal CS2.
Reference numeral 200 denotes a vertical dynamic focusing signal generating section having an amplifying unit 210 for amplifying the second lamp signal CS2 in accordance with a second voltage Vcc2, a signal converting unit 220 for converting the amplified signal to an integrating signal of parabola, and a superimposing unit 230 for superimposing the integrating signal on a direct voltage DC supplied from a flyback transformer.
Here, the lamp signal controlling section 100 comprises a pulse signal converting unit 110 for converting the first lamp signal CS1 of sawtooth waveform to a pulse signal, an oscillator 120 for receiving the pulse signal and for outputting an oscillating signal, a switching signal generating unit 140 for integrating the oscillating signal and for outputting a switching signal, and a second lamp signal generating unit 140 for switching on and off and for controlling the amplitude of the pulse signal in accordance with the frequency of the first lamp signal CSl to generate the second lamp signal.
The construction of the lamp signal controlling section 100 will be described in more detail.
The first lamp signal CS1 is supplied to the positive side(+) of a buffer 111 for delaying an output of the first lamp signal CS1, and the negative side(-) of the buffer 111 is coupled to the output side of the buffer 111.
The output side of the buffer 111 is connected to one end of a resistor 112 for bypassing the output signal of the buffer 111, and the other end of the resistor 112 is coupled to the positive side(+) of the amplifier 113 for converting the output signal of the buffer 111 to a pulse signal.
In the meantime, first voltage Vccl is supplied to one end of a resistor 114 for dividing the first voltage Vccl, and the other end of the resistor 114 is connected to the negative side(-) of the amplifier 113 and one end of a resistor 115.
The other end of the resistor 115 is grounded.
Further, output side cf the amplifier 113 Is coupled to the oscillator 120 for converting the frequency of the pulse signal to frequency of the first lamp signal CS1 and for outputting an oscillating signal. The output side of the oscillator 120 is coupled to one end of a resistor 131 of the switching signal generating unit 130 for bypassing the oscillating signal, and the other end of the resistor 131 is connected to one end of a capacitor 132 for integrating the oscillating signal and for outputting the switching signal.
And the other end of the capacitor 132 is grounded.
One end of the capacitor 132 is connected to one end of a resistor 133 for bypassing the switching signal, and other end of the resistor 133 is connected to the base of a transistor 141 of the second lamp signal generating unit 140 for switching on and off.
Furthermore, the output side of the buffer is connected to the positive side(+) of an amplifier 142 for amplifying the first lamp signal CS1. One end of the resistors 143 and 144 are connected to the emitter side of the transistor 141 and the collector side of the transistor 141, and one end of a resistor 145 is connected between the negative side(-) of the amplifier 142 and the output side of the amplifier 142. The amplifying degree of the amplifier 142 is determined by the resistances of the resistors 143, 144 and 145. And the other end of each the resistors 143 and 144 is grounded.
In the meantime, the vertical dynamic focusing signal generating section 200 includes amplifiers 211 and 221, resistors 212-215, 222-225, 231, 233-234 and 237, capacitors 226, 228 236 and 238, a transistor 232, and diode 235, as shown in FIG. 1.
In connection with this embodiment of the present invention construction as above, the operation and effect of the vertical dynamic focusing circuit for a monitor will be described with reference to the accompany drawings.
FIG. 5A to FIG. 5N are waveform timing diagrams to aid in explaining the operation of the vertical dynamic focusing circuit for a monitor according to one embodiment of the present invention. The amplitude of the first lamp signal CSl which is the sawtooth waveform is about 2.5 V, as shown in FIG. 5A, when the frequency of the vertical sync signal is low(about 50Hz) and the amplitude of the lamp signal CS is about 2.5 V, as shown in FIG. 5B, when the frequency of the vertical sync signal is high(about 120Hz).
Such first lamp signal CSl is supplied to the buffer 111 of the pulse signal converting unit 110, so the buffer 111 delays the output of the first lamp signal CS1. The output signal of the buffer 111 is supplied to the amplifier 113 through the resistor 112.
The first voltage Vccl is supplied to the resistors 114 and 115, so the resistors 114 and 115 divide the first voltage Vccl and the divided voltage is supplied to the amplifier 113.
The amplifier 113 amplifies the output signal of the resistor 112 in accordance with the divided voltage and outputs the pulse signal. The amplitude of the pulse signal is shown in FIG. SC, when the frequency of the vertical sync signal is about 50Hz. And the amplitude of the pulse signal is shown in FIG. 5D when the frequency of the vertical sync signal is about 120Hz.
The pulse signal and the first voltage ccl are supplied to an oscillator 120, so the oscillator 120 converts the frequency of the pulse signal corresponding to the frequency of the first lamp signal and outputs the oscillating signal.
At that time, the oscillating signal is shown in FIG. SE when the frequency of the vertical sync signal is about 50Hz, and the oscillating signal is shown in FIG. 5F when the frequency of the vertical sync signal is about 120Hz.
The oscillating signal is supplied to the capacitor 32 through the resistor 131 of the switching signal generating unit 130, so the capacitor 132 integrates the oscillating signal and outputs the switching signal. The amplitude of the switching signal is about 0.6V, as shown in FIG. 5G, when the frequency of the vertical sync signal is about 50Hz. And the amplitude of the switching signal is about 1.2V, as shown in FIG. 5H, when the frequency of the vertical sync signal is approximately 120Hz.
Further, the switching signal is supplied to the base side of the transistor 142 through the resistor 133. Since the amplitude of the switching signal is about C.6V when the frequency of the vertical sync signal is approximately 50Hz, the transistor 142 switches off.
In the meantime, the amplifier 143 which receives the first lamp signal CSl amplifies the first lamp signal and outputs the second lamp signal CS2. At that time, the amplifying degree of the amplifier 142 is determined by the resistance with the resistors 144 and 145.
In other words, the amplitude of the second lamp signal CS2 is proportional to the value of (1+ R144/R145). At that tie, the amplitude of the second lamp signal CS2 is about 2.5V, as shown in FIG. SI, when the frequency of the vertical sync signal is approximately 50Hz. Here, the R144 and R145 are the resistance of the resistors 144 and 145, respectively.
However, since the amplitude of the switching signal is about 1.2V when the frequency of the vertical sync signal is approximately 120Hz, the transistor 142 switches on.
In the meantime, the amplifier 143 which receives the first lamp signal CSl amplifies the first lamp signal and outputs the second lamp signal CS2. At that time, the mplifying degree of the amplifier 142 is determined by the resistance with the resistors 143, 144 and 145. In other words, the amplitude of the second lamp signal CS2 is proportional to a value of a T1, as shown in equation 1.
Equation 1) R145 > c(R143+R144)) R143xR144 At that time, the amplitude of the second lamp signal CS2 s about 3V, as shown in FIG. 5J, when the frequency of the vertical sync signal is approximately 120Hz. Here, the R143, R144, and R145 are the resistances of the resistors 143, 144 and 145, respectively.
Therefore, the amplitude of the second lamp signal CS2 when the vertical sync signal is about 50Hz is more than that of the second lamp signal CS2 when the vertical sync signal is about 50Hz.
Such second lamp signal CS2 is supplied to the amplifier 211 of the amplifying unit 210 through the resistor R and the capacitor C, so the amplifier 211 amplifies the output signal of the resistor R in accordance with the magnitude of the voltage Vcc and the resistances of the resistors 212 and 213.
The amplifying degree of the amplifier 211 is determined by the resistances of the resistors 214 and 215.
The amplified signal of the amplifier 211 is supplied to the amplifier 221 through the resistor 215, so the amplifier 221 rectifies the amplified signal of the amplifier 221 in accordance with a limit voltage which is set by the resistance with the resistors 222 and 223.
The output signal of the amplifier 221 is supplied to the resistor 225 and the capacitor 226 through the resistor 224, so the resistor 225 and the capacitor 226 integrate the output signal of the amplifier 221 and generate an integrating signal of parabola. The amplifying degree of the integrating signal is determined by the capacitance of the capacitor 227.
The amplitude of the integrating signal is about 11.8V, as shown in FIG. 5K, when the frequency of the vertical sync signal is low(about 50Hz). And amplitude of the integrating signal is about llV, as shown in FIG. 5L, when the frequency of the vertical sync signal is about 120Hz.
The integrating signal of the amplifier 221 is supplied to the capacitor 228, so the capacitor blocks the direct component of the output signal of the amplifier 221. The output signal of the capacitor 228 is supplied to the resistor 231 through the resistor 229, so the resistor 231 superimposes the output signal of the capacitor 228 on the first voltage Vcc. And the superimposed signal is supplied to the transistor 232 of the superimposing unit 230.
The transistor 232 inverts and amplifies the superimposed signal. The amplifying degree is determined by the resistances of the resistors 233 and 234.
In the meantime, the direct voltage DC supplied from the flyback transformer is supplied to a diode 235, so the diode 235 rectifies the output signal of the flyback transformer.
The output voltage of the diode 235 is supplied to the capacitor 236, so the capacitor smooths the output voltage of the capacitor 236.
Further, the output voltage of the capacitor 236 is superimposed on the output signal of the transistor 232 supplied through the resistor 237, and the superimposed signal is supplied to the capacitor 238, so the capacitor 38 smooths the superimposed signal and outputs a vertical dynamic focusing signal.
The amplitude of the vertical dynamic focusing signal is about 150V, as shown in FIG. 5M, when the frequency of the vertical sync signal is about 50Hz. And amplitude of the vertical dynamic focusing signal is about 130V, as shown in FIG. 5N, when the frequency of the vertical sync signal is about 120Hz.
The vertical dynamic focusing signal of the capacitor 38 is supplied.to a mixing unit M, so the mixing unit M mixes the vertical dynamic focusing signal of the capacitor 38 to the horizontal dynamic focusing signal. The mixed signal is supplied to the grid terminal of the CRT.
Hence, the amplitude of the vertical dynamic focusing signal becomes constant regardless of the frequency of the vertical sync signal.
FIG. 6 is a view for showing a construction of the dynamic focusing circuit for a monitor according to another embodiment of the present invention. In FIG. 6, reference numeral 300 denotes a lamp signal controlling section for amplifying a first lamp signal CSl in accordance with the frequency of the first lamp signal CSl and for generating a second lamp signal CS2.
Further, reference numeral 200 denotes a vertical dynamic focusing signal generating section having an amplifying unit 210 for amplifying the second lamp signal CS2 in accordance with a second voltage Vcc2, a signal converting unit 220 for converting the amplified signal to an integrating signal of parabola, and a superimposing unit 230 for superimposing the integrating signal on a direct voltage supplied from a flyback transformer and for outputting a vertical dynamic focusing signal. Here, the construction of the vertical dynamic focusing signal generating section 200 is shown in FIG. 4 and the detailed description of the construction thereof is omitted.
Here, the lamp signal controlling section 300 comprises a microprocessor 310 for receiving a vertical sync signal and for generating a pulse signal, a switching signal generating unit 320 for integrating the oscillating signal and for outputting a switching signal, and a second lamp signal generating unit 330 for switching on and off and for controlling the amplitude of the pulse signal in accordance with the frequency of the first lamp signal CS1 to generate the second lamp signal CS2.
The construction of the lamp signal controlling section 300 will be described in more detail.
The first lamp signal CSl is supplied to one end of the microprocessor 310 for receiving the vertical sync signal and for connected to the other end of the resistor 321 and one end of a resistor 323.
Further, the other end of the resistor 322 is connected to one end of a resistor 324 for superimposing the dividing voltage on the pulse signal and for bypassing the superimposed signal. The other end of the resistor 324 is connected to one end of a capacitor 325 for integrating the superimposed signal and for generating the switching signal. And the other end of the capacitor 325 is grounded.
Also, the one end of the capacitor 325 is coupled to the positive side(+) of an amplifier 326 for amplifying the switching signal and for outputting the amplified switching signal.
In the meantime, one end of resistor 327 for determining an amplifying degree of the amplifier 326 is connected between the output side of the amplifier 326 and the negative side(-) thereof. And the negative side(-) of the amplifier 326 is connected to one end of a resistor 328 for determining the amplifying degree of the amplifier 326 with the resistor 327.
The other end of the resistor 328 is grounded.
The output side of the amplifier 326 is connected to one end of a resistor 331 for bypassing the amplified switching signal and the other end of the resistor 331 is connected to the base side of a transistor 332 for swiching on and off in accordance with the amplified switching signal.
In the meantime, the first lamp signal CSl is supplied to the positive side(+) of an amplifier 333 for amplifying the first lamp signal CS1. One end of the resistors 334 and 335 are connected to the emitter side of the transistor 332 and the collector side of the transistor 332, respectively. And one end of a resistor 336 is connected between the negative side(-) of the amplifier 333 and the output side of the amplifier 333. The amplifying degree of the amplifier 333 is determined by the resistances of the resistors 334, 335 and 336. And the other end of the resistors 334 and 335 are grounded.
The operation and effect of another embodiment of the present invention as constructed above will be described with reference to the attached drawings.
FIG. 7A to FIG. 7J are waveform timing diagrams to aid in explaining the operation of the dynamic focusing circuit for a monitor according to another embodiment of the present invention.
To begin with, the vertical sync signal Vs is supplied to a microprocessor 310, so the microprocessor 310 receives the vertical sync signal Vs and outputs the pulse signal. At that time, the pulse signal is shown in FIG. 7A when the frequency of the vertical sync signal Vs is about 50Hz, and the pulse signal is shown in FIG. 7B when the frequency of the vertical sync signal Vs is about 120Hz.
In the meantime, the third voltage Vcc3 is supplied to the resistors 322 and 323, so the resistors 322 and 323 divide the third voltage Vcc3 and output the dividing voltage. The dividing voltage and pulse signal are superimposed and output Xhe superimposed signal. The amplitude of the superimposed signal is about 4V, as shown in FIG. 7C, when the frequency of the vertical sync signal Vs is about 50Hz. And the amplitude of the superimposed signal is about 3V, as shown in FIG. 7D when the frequency of the vertical sync signal Vs is about 120Hz.
The superimposed signal is supplied to the capacitor 325 through the resistor 324, so the capacitor 325 integrates the superimposed signal and outputs the switching signal. And the switching signal is supplied to the amplifier 326, so the amplifier 326 amplifies the switching signal. Here, the amplifying degree of the amplifier 326 is determined by the resistances of the resistors 327 and 328.
Since the amplitude of the switching signal is about 4V when the frequency of the vertical sync signal is approximately 50Hz, the transistor 332 switches off.
In the meantime, the amplifier 333 which receives the first lamp signal CS1 amplifies the first lamp signal and outputs the second lamp signal CS2. At that time, the amplifying degree of the amplifier 333 is determined by the resistance with the resistors 334 and 336.
In other words, the amplitude of the second lamp signal CS2 is proportional to a value of the (1+ (R336/R334)). At that time, the amplitude of the second lamp signal CS2 is about 2.5V, as shown in FIG. 7E, when the frequency of the vertical sync signal is approximately 50Hz. Here, the R334 and R 336 are the resistances of the resistors 334 and 336, respectively.
However, since the amplitude of the switching signal is about 3V when the frequency of the vertical sync signal is approximately 120Hz, the transistor 333 switches on.
Therefore, the amplifying degree of the amplifier 333 is determined by the resistance with the resistors 334, 335 and 336.
In other words, the amplitude of the second lamp signal CS2 is proportional to a value of a T, as shown in equantion 2.
Equation 2) 1+(R336X(R334+R335)) R334x R335 At that time, the amplitude of the second lamp signal CS2 is about 3V, as shown in FIG. 7F, when the frequency of the vertical sync signal is approximately 120Hz. Here, the R334, R335 and R336 are the resistances of the resistors 334, 335 and 336, respectively.
Therefore, the amplitude of the second lamp signal CS2 when the vertical sync signal is about 50Hz is more than that of the second lamp signal CS2 when the vertical sync signal is about 50Hz.
Such second lamp signal CS2 is supplied to the amplifier 211 of the amplifying unit 210 through the resistor R and the capacitor C, so the amplifier 211 amplifies the output signal cf the resistor R in accordance with the magnitude of the voltage Vcc and the resistances of the resistors 212 and 213.
The amplifying degree of the amplifier 211 is determined by the resistances of the resistors 213 and 214.
The amplified signal of the amplifier 211 is supplied to the amplifier 221 through the resistor 215, so the amplifier 221 rectifies the amplified signal of the amplifier 221 in accordance with a limit voltage which is set by the resistances with the resistors 222 and 223.
The output signal of the amplifier 221 is supplied to the resistor 225 and the capacitor through the resistor 224, so the resistor 225 and the capacitor 226 integrate the output signal of the amplifier 221 and generate an integrating signal of parabola. The amplifying degree of the integrating signal is determined by the capacitance of the capacitor 227.
The amplitude of the integrating signal is about 11.8V, as shown in FIG. 7G, when the frequency of the vertical sync signal is low(about 50Hz). And amplitude of the integrating signal is about 11V, as shown in FIG. 7H, when the frequency of the vertical sync signal is about 120Hz.
The integrating signal of the amplifier 221 is supplied to the capacitor 228, so the capacitor blocks the direct component of the output signal of the amplifier 221. The output signal of the capacitor is supplied to the resistor 231 through the resistor 229, so the resistor 231 superimposes the output signal of the capacitor 228 on the first voltage Vcc.
And the superimposed signal is supplied to the transistor 232 of the superimposing unit 230.
The transistor 232 inverts and amplifies the superimposed signal. The amplifying degree is determined by the resistances of the resistors 233 and 234.
In the meantime, the direct voltage DC supplied from the flyback transformer is supplied to the diode 235, so the diode 235 rectifies the output signal of flyback transformer. The output voltage of the diode 235 is supplied to the capacitor 236, so the capacitor smooths the output voltage of the capacitor 236.
Further, the output voltage of the capacitor 236 is superimposed to the output signal of the transistor 232 supplied through the resistor 237, and the superimposed signal is supplied to the capacitor 238, so the capacitor 38 smooths the superimposed signal and outputs a vertical dynamic focusing signal.
The amplitude of the vertical dynamic focusing signal is about 150V, as shown in FIG. 71, when the frequency of the vertical sync signal is about 50Hz. And amplitude of the vertical dynamic focusing signal is about 130V, as shown in FIG. 7J, when the frequency of the vertical sync signal is about 120Hz.
The vertical dynamic focusing signal of the capacitor 38 is supplied to the mixing unit M, so mixing unit M mixes the vertical dynamic focusing signal of the capacitor 38 to the horizontal dynamic focusing signal. The mixed signal is supplied to the grid terminal of the CRT.
Accordingly, the amplitude of the vertical dynamic focusing signal becomes constant regardless of the frequency of the vertical sync signal.
By employing the vertical dynamic focusing circuit for a monitor according to the embodiments of the present invention, the first lamp signal is amplified when the frequency of the vertical sync signal and the vertical dynamic focusing signal are generated in accordance with the amplified first lamp signal. Therefore, the vertical dynamic focusing signal becomes constant regardless of the frequency of the vertical sync signal, so the electron beam is focused at the edge of the picture, thereby the quality of picture can be enhanced.
While an embodiment of the present invention has been particularly shown and described, it will be understood by those skilled in the art that various changes in form and details may be affected therein without departing from the spirit and scope of the invention as defined by the appended claims. For instance, while the preferred embodiments of the present invention herein are described for a monitor, the present invention may be applied to every video signal processing system such as general VCRs.

Claims (9)

CLAIMS:
1. A vertical dynamic focusing circuit for a monitor, comprising: a lamp signal controlling means for amplifying a first lamp signal in accordance with a frequency of said first lamp signal and for generating a second lamp signal; and a vertical dynamic focusing signal generating means having an amplifying unit for amplifying said second lamp signal in accordance with a second voltage, a signal converting unit for converting said amplified signal to an integrating signal of parabola, and a superimposing unit for superimposing said integrating signal on a direct voltage supplied from a flyback transformer and for generating a vertical dynamic focusing signal.
2. The vertical dynamic focusing circuit for a monitor as claimed in claim 1, wherein said lamp signal controlling means includes: a pulse signal converting unit for converting said first lamp signal of sawtooth waveform to a pulse signal; an oscillator for receiving said pulse signal and for outputting an oscillating signal; a switching signal generating unit for integrating said oscillating signal and for outputting a switching signal; and a second lamp signal generating unit for switching on and off and for controlling the amplitude of said pulse signal in accordance with the frequency of said first lamp signal to generate said second lamp signal.
3. the vertical dynamic focusing circuit for a monitor as claimed in claim 2, wherein said pulse signal converting unit includes: a buffer for receiving said first lamp signal and for delaying an output of said first lamp signal, wherein the negative side(-) of the buffer is coupled to the output side of said buffer; a first resistor for inputting the output signal of said buffer and for bypassing the output signal of the buffer; a first amplifier for receiving the output signal of said buffer and for converting the output signal of said buffer to said pulse signal; second and third resistors for inputting a first voltage and for dividing said first voltage, wherein the one end of the second resistor is connected to the negative side(-) of said amplifier, the one end of said first resistor is connected to the positive side of said amplifier, and the other end of said third resistor is grounded.
4. The vertical dynamic focusing circuit for a monitor as claimed in claims 2 or 3, wherein said oscillator receives said pulse signal, converts a frequency of said pulse signal to the frequency of said first lamp signal, and outputs an oscillating signal.
5. The vertical dynamic focusing circuit for a monitor as claimed in any one of claims 2 to 4, wherein said switching signal generating unit includes: a fourth resistor for bypassing said oscillating signal; a first capacitor for receiving the output signal of said fourth resistor, for integrating said oscillating signal, and for outputting the switching signal, wherein the one end of said first capacitor is grounded; and a fifth resistor for bypassing said switching signal.
6. The vertical dynamic focusing circuit for a monitor as claimed in claim 3 or any of claims 4 or 5 as dependent on cla:n 3, wherein said second lamp signal generating unit comprises: a first transistor for receiving said switching signal and for switching on and off; a second amplifier for receiving said output signal of said buffer and for amplifying said first lamp signal; and sixth, seventh, and eighth resistors for determining an amplifying degree of said second amplifier, wherein one end of sixth and seventh resistors are connected to the emitter side of said first transistor and the collector side of said first transistor, one end of the eighth resistor is connected between the negative side(-) of said second amplifier and the output side of said second amplifier, and the other end of the sixth and seventh resistors are grounded.
7. The vertical dynamic focusing circuit for a monitor as claimed in any of claims 1 to 6, wherein said lamp signal controlling means includes: a microprocessor for receiving a vertical sync signal and for generating a pulse signal; a switching signal generating unit for integrating said pulse signal and for outputting a switching signal; and a second lamp signal generating unit for switching on and off and for controlling the amplitude of said first lamp signal in accordance with switching state to generate said second lamp signal.
8. The vertical dynamic focusing circuit for a monitor as claimed in claim 7, wherein said switching signal generating unit comprises: a ninth resistor for bypassing said pulse signal of said microprocessor; tenth and eleventh resistors for receiving a third voltage, for dividing said third voltage, and for outputting a dividing voltage, wherein said tenth and eleventh resistors are connected in series with respect to the third voltage, and the other end of the eleventh resistor is grounded; a twelfth resistor for receiving said dividing voltage and said pulse signal, for superimposing the dividing voltage and the pulse signal, and for bypassing the superimposed signal; a second capacitor for inputting said superimposed signal, for integrating the superimposed signal, and for generating said switching signal, wherein the one end of said second capacitor is grounded; a third amplifier for receiving said switching signal, for amplifying the switching signal, and for outputting an amplified switching signal; and thirteenth and fourteenth resistors for determining an amplifying degree of said third amplifier, wherein one end of the thirteenth resistor is connected between the output side of said third amplifier and the negative side(-) thereof, one end of the fourteenth resistor is connected to the negative side(-) of said third amplifier, and the other end of the fourteenth resistor is grounded.
9. A vertical dynamic focusing circuit substantially as hereinbefore described with respect to any one of Figures 4 to 7J of the accompanying drawings.
GB9811973A 1997-06-30 1998-06-03 Vertical dynamic focusing circuit for a multi-mode monitor Withdrawn GB2327326A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019970029771A KR100232920B1 (en) 1997-06-30 1997-06-30 Dynamic focus circuit of multi-sync. monitor

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GB9811973D0 GB9811973D0 (en) 1998-07-29
GB2327326A true GB2327326A (en) 1999-01-20

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KR (1) KR100232920B1 (en)
GB (1) GB2327326A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2340707A (en) * 1998-08-07 2000-02-23 Thomson Consumer Electronics Dynamic focus voltage amplitude controller

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5245254A (en) * 1992-07-15 1993-09-14 Gold Star Co., Ltd. Horizontal focus circuit in an image display
GB2319447A (en) * 1996-11-14 1998-05-20 Daewoo Electronics Co Ltd Dynamic focusing circuit for a multi-mode monitor
GB2320874A (en) * 1996-12-28 1998-07-01 Daewoo Electronics Co Ltd Multi-mode dynamic focus circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5245254A (en) * 1992-07-15 1993-09-14 Gold Star Co., Ltd. Horizontal focus circuit in an image display
GB2319447A (en) * 1996-11-14 1998-05-20 Daewoo Electronics Co Ltd Dynamic focusing circuit for a multi-mode monitor
GB2320874A (en) * 1996-12-28 1998-07-01 Daewoo Electronics Co Ltd Multi-mode dynamic focus circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2340707A (en) * 1998-08-07 2000-02-23 Thomson Consumer Electronics Dynamic focus voltage amplitude controller
GB2340707B (en) * 1998-08-07 2002-11-13 Thomson Consumer Electronics Dynamic focus voltage amplitude controller

Also Published As

Publication number Publication date
JPH1132231A (en) 1999-02-02
KR19990005559A (en) 1999-01-25
KR100232920B1 (en) 1999-12-01
GB9811973D0 (en) 1998-07-29

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