GB2325124A - Configuration and synchronisation of a digital network - Google Patents

Abstract

A network effectively providing multi-node communication of audio information has a number of node units (20, 40) interconnected to enable any node unit to send audio and/or control information to any other node unit. The connecting cable (6) interconnecting the node units (20, 40) has both transmit and receive pairs so that there is no requirement to form physical rings with return cables, but the node units (20, 40) are interconnected to form logical rings (RINGS 1-5). Because each node unit at the end of a ring has only a single one of its connection parts connected to other node units of that ring, each node unit (20, 40) on being connected into the network is able to identify whether it is an end, or a middle, node unit, such that, on formation of the network, the ring structure is configured automatically. Furthermore, one of the node units provides the reference clock for the whole of the network, and the remaining node units (20, 40) synchronise themselves to the clock source node unit automatically on set up. For example, one node unit (HUB 2) may be designated as the clock master unit on initialisation. The node unit (HUB 2) is established first of all as the clock master of a ring (RING 1), and thereafter, the rings communicate to set that node unit (HUB 2) as the clock master for the network.

Description

A DIGITAL NETWORK AND A METHOD OF FORMING A DIGITAL NETWORK The present invention relates to a digital network and to a method of forming a digital network.

There is a need for digital networks for audio applications. For example, it may be required to connect a number of audio sources such as microphones, CD players, and radios to a number of loudspeakers. Conventionally, audio data is communicated by point to point networks which have not enabled the creation of multi-point networks.

Of course, digital technology has produced multi-point data networks, for example, packet networks enabling data packets to be sent from one node on the network to one or more of the other nodes. However, if such conventional digital networks are used for audio information, substantial amounts of buffer memory have to be provided at each node to maintain precise synchronisation of the audio data. This has generally been at high cost, and has meant that long delays have been introduced, which are not acceptable for many audio applications.

A network of the present invention seeks to effectively provide for multinode communication of audio information without the problems of each of the conventional approaches. Furthermore, a network of the invention seeks to use unshielded twisted pair cabling and yet still provide the bandwidths required.

This invention is concemed with the passage of information around a network. In this invention, the information can be classified in two categories: isochronous data which is data in a continuous steady stream of bytes, and packet data which is data in discrete units of a number of bytes each.

Preferably, isochronous data is used for audio information, but it can also be used for other forms of information.

Preferably, packet data is used for control information, but it can also be used for other forms of information, and may indeed include audio data, especially if it is not required to process this in real time.

In the broadest aspects, the present invention is not limited to either the form or nature of the isochronous data, or to the form or nature of the packet data.

According to a first aspect of the present invention there is provided a digital network comprising a plurality of node units interconnected to enable the communication of information between node units, each node unit having at least two connection ports, wherein the network is comprised of one or more logical rings, each said ring having two ends, and each node unit at the end of a ring having only a single one of its connection ports connected to other node units of that said ring.

Preferably a selected one of said node units forms the clock source for the network.

In an embodiment, each node unit is connected to the next node unit in a ring by way of a single cable.

A digital network of the invention may be used to communicate any required information around a network. However, preferably, a digital network of the invention is arranged for the communication of audio information between node units.

In an embodiment two connection ports of a node unit are selectively connectable by way of a switching network to an input and an output of an associated audio module of the node unit.

For example, when only one of the two connection ports associated with an audio module of a node unit is connected to another node unit, the input and output of said audio module are connected to said one connection port.

Preferably, a data repeater is associated with the audio module of a node unit, and wherein when both of the two connection ports associated with the audio module of said node unit are connected to another node unit, the switching network selectively connects inputs and outputs both of said audio module and of said data repeater to said two connection ports.

In an embodiment, each said audio module has two paths between its input and its output, the path taken by incoming information being selectively determinable.

In a preferred embodiment, each said audio module has its input connected to its output such that any audio module which is not arranged as a clock source can pass information straight through from its input to its output.

There are considerable advantages to enabling each audio module to pass information straight through from its input to its output. In particular, this avoids the addition of delay to the information and is particularly convenient where the information being passed is not required for use by the audio module concerned.

According to a further aspect of the present invention there is provided a method of forming a digital network, comprising the steps of connecting a number of node units such that each node unit is connected to at least one other node unit, and on initialisation, causing said node units to communicate with one another to configure a selected one of the node units as the clock source for the formed network.

Preferably each said node unit has at least two connection ports, and the network is comprised of one or more logical rings, the method further comprising the steps of, on initialisation, enabling end node units to generate set up signals, an end node unit having only a single one of its connection ports connected to other node units of the same ring.

In an embodiment, on receiving a set up signal, a node unit which has an extemal reference clock is enabled to designate itself as the clock source and to generate signals to prevent other node units becoming clock sources.

For example, the set up signals generated by end node units are compared and, as a result of the comparison, one end node unit is selected, and wherein said set up signal to which said clock source node unit is responsive is generated by said selected end node unit.

According to a further aspect of the present invention there is provided a method of forming a digital network, comprising the steps of connecting a number of node units such that each node unit is connected to at least one other node unit, and causing each node unit to route connections from its inputs to its outputs in dependence upon the number of node units to which it is connected.

A method of this implementation of the invention enables the network to be configured automatically on setup.

In an embodiment, each node unit has two connection ports each having a receive terminal and a transmission terminal, and wherein, when only one connection port is connected, the node unit connects the receive and transmission terminals of said one connection port by way of a processing module of the node unit.

In a further embodiment, when both connection ports are connected, the node unit connects the receive terminal of each connection port to the transmission terminal of the other connection port.

Preferably, the receive terminal of one connection port is connected to the transmission terminal of the other connection port by way of a processing module of the node unit, and wherein the receive terminal of the other connection port is connected to the transmission terminal of the one connection port by way of a data repeater.

The present invention also extends to a digital network formed by one or more of the methods defined above. Such a digital network may incorporate each or any of the network features defined above.

The present invention also extends to a method of communicating information between node units interconnected to form a network, the method comprising the steps of transferring the information around the network in one or more frames, where the information incorporated in each frame comprises both isochronous data and packet data, and incorporating in each frame a count representing the destination address for the packet data in the frame, and the method further comprising the steps of incrementing or decrementing the count at each successive node unit, and delivering the packet data to the node unit whose address corresponds to the count incorporated in an arriving frame.

In a preferred embodiment, the count is decremented at each node unit, and the packet data is delivered to the node unit at which it arrives when the count in the frame reaches zero.

Embodiments of the present invention will hereinafter be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 illustrates one embodiment of a network of the invention, Figure 2 is a sequence enabling a node unit of a network to designate itself as the clock master, Figure 3 shows schematically a physical implementation of a station node unit, Figure 4 shows schematically a physical implementation of a node unit forming a hub unit, Figure 5 is a block diagram of a customised chip in the node unit of Figure 3 or Figure 4, Figure 6 shows an audio module in the chip of Figure 5, Figure 7 indicates the delay which may be imposed on data signals transferred around a network of the invention, Figure 8a shows schematically a frame of information as transferred around the network, and Figure 8b shows the format of a packet concatenated from several fields of packet data from sequential frames.

The invention is described and illustrated with reference to a network for passing audio signals. In this respect there are particular difficulties in networking audio signals as the network must deal with every sample in a reasonable time and a network of the invention is able to do this. However, although exemplified as an audio network, the invention is not limited to such an application and a network of the invention can be used to deal with other information if required.

Figure 1 shows one embodiment of a network of the invention. In this network, a number of node units 20, 40 are interconnected by cables 6. The node units 20 are daisy chain units or stations, and each have two connection ports only. These connection ports may be provided, for example, by jack connectors. The other node units 40 are hub units and have a larger number of connection ports, perhaps eight. Again, it is preferred that each connection port is a substantially conventional jack connector.

The node units 20, 40 and the network resulting from their interconnection, are arranged to require no particular topology. Thus, a network of node units 20, 40 will operate to enable any node unit to send audio and/or control information to any other node unit, as long as every node unit is connected to at least one other node unit.

In this respect, the overall network, as shown in Figure 1, is configured as one or more rings. However, each connecting cable 6 has both transmit and receive pairs so that there is no requirement to arrange the units 20, 40 as a physical ring with a retum cable. Rather, the network is arranged to form one or more logical rings.

The network shown in Figure 1 is made up of five interconnected rings.

Thus, the first ring, RING 1 is comprised of STATIONS 1 and 2 and the HUB 2, RING 2 is made up of STATION 3 and HUB 2, RING 3 comprises STATION 4 and HUB 2, RING 4 comprises HUBS 1 and 2, and RING 5 comprises STATIONS 5 and 6 and HUB 1.

It will be seen from Figure 1 that each ring may comprise two or more node units 20, 40. However, each ring has two ends, and each end unit 20, 40 of each ring only has a single connection port interconnected with that ring.

In this respect, and as described below, each node unit 20, 40 is, on being connected into the network, able to identify whether it is an end node unit or a middle node unit. This means that on formation of the network the node units sense their status such that the ring structure is configured automatically.

Furthermore, one of the node units of the network is designated as the clock source and provides the reference clock for the whole of the network. The remaining node units 20, 40 synchronise themselves to the clock source node unit. The designation of the clock source node unit, or clock master is also performed automatically on set up of the network.

For example, in the network shown in Figure 1, the node unit HUB 2 can be designated as the clock master unit for the network on initialisation. In this respect, the node unit HUB 2 is established first of all as the clock master of a ring, say RING 1, and thereafter, the rings communicate to set the clock master for the network.

Let us consider the designation of the node unit HUB 2 as the clock master for RING 1 on initialisation of that ring.

In this respect, during power up, the node units 20, 40 of RING 1 are arranged to communicate by signals which do not carry audio information. The individual units, therefore, can insert messages into the signals. On power up, all of the node units 20, 40 emit a datastream of constant zeros. This enables the two node units 20, 40 at each end of RING 1, in this case, HUB 2 and STATION 2, to identify themselves. Thereafter, one of the end units HUB 2, STATION 2 is designated as dominant for the purposes of set up.

During set up, the clocks associated with all of the node units 20, 40 are fixed at their centre frequency. Each end node unit HUB 2, STATION 2 identifies itself as an end unit, by identifying that it only has signal on one of its connection ports, and then uses its clock as a reference. Thus, each end node unit HUB 2, STATION 2 sets itself into clock master mode but clears an outgoing reconfiguration flag. Each end unit HUB 2, STATION 2 then enables its connected port and sends a data packet, SET UP PACKET #1. SET UP PACKET #1 contains only a control word to identify the packet and a unique serial number. At this stage, all the node units 20, 40 which have established that they are not end units set themselves to clock slave mode. Every unit in clock slave mode receiving a valid packet from an end unit enables its output so that SET UP PACKET #1 is passed straight through.

When SET UP PACKET #1 reaches another end node unit 20, 40, this end unit examines the unique serial number it has received. Thus, HUB 2 will examine the unique serial number from STATION 2. Of course, HUB 2 will have similarly produced a SET UP PACKET #1 with its own unique serial number and transmitted this to STATION 2. Thus, each end unit HUB 2 and STATION 2 compares the two unique serial numbers. It is determined that the end unit generating the largest unique serial number will become dominant, or initiate the next phase.

The end unit HUB 2 or STATION 2 which has been selected as the dominant end unit, at this stage, sets itself as a clock master. The other end unit, which had the lower unique serial number, sets itself as a slave.

Any node unit 20, 40 which is at one end of a ring and which has an external reference clock can become the source of clock signals for that ring.

Accordingly, the selected, dominant, end unit next transmits a further data packet SET UP PACKET #2. This has a master clock bit at zero. The first node unit with an external reference clock which receives SET UP PACKET #2 with the clock master bit set at zero becomes the clock source for the ring. That unit, on receiving SET UP PACKET #2, changes the clock master bit from zero to one. The data packet then continues around the ring but without the capability of designating any further node units as the clock source.

The unit which has been selected as the clock source by receiving SET UP PACKET #2 with a zero clock master bit then generates SET UP PACKET #3. When this is received by the end node unit which generated SET UP PACKET #2, that end unit sets itself as a slave. However, if after a predetermined period, the end unit which generated SET UP PACKET #2 does not receive SET UP PACKET #3, then that end unit has to designate itself as the clock source or master unit. This sequence is shown in Figure 2.

Once the ring has been configured, it can then be used to transmit data signals from node unit to node unit under the control of the clock signal from the clock source or master unit, say HUB 2. However, if one of the end node units HUB 2 or STATION 2 detects the appearance of a signal on its previously unconnected port, it will transmit a reconfigure control to the remainder of the ring to start a new initialisation routine.

It will be appreciated from the above that each individual ring of the network will have its own clock master unit. However, the network will have a single clock master unit and all of the clock sources of the rings will be slaved to the clock master for the network. This is achieved on set up of the network in a similar manner to the selection of the clock master for each ring and therefore need not be described further.

Figure 3 shows schematically the physical implementation of a node unit 20 having two connection ports 50 only. As indicated in Figure 3, each connection port 50 is connected by two wires and appropriate interface circuitry 52 to a customised chip 54 which is controlled by a microprocessor 51. As described earlier, each connection port 50 is arranged to deal with both incoming and outgoing signals.

A node unit 40 could comprise a plurality of the modules indicated in Figure 3. However, it is presently preferred that each node unit 40 is configured as shown in Figure 4. Thus, and as shown, each customised chip 54 is connected by way of an appropriate interface circuit 52 to one connection port 50. In addition, each said chip 54 is interconnected with other chips of the node unit 40 by way of an interconnection circuit 53. A microprocessor 51 is also provided in the node unit 40 to control the chips 54.

Figure 5 shows the configuration of one of the customised chips 54. In this respect, connections are made to the chip 54 by way of two pairs of terminals 56, 58. For example, in a node unit 20 of Figure 3, each connection port 50 is connected to a respective one of the pairs of terminals 56, 58. Each terminal 58 is a receive terminal and is connected by way of a demodulator 64 to a data input 60 and a clock input 62 of a switching network 74. A data output 66 of the switching network 74 is connected to each output terminal 56.

On each chip 54 there is a main audio module 70 and a data repeater 72.

It will be seen that each of the audio module 70 and of the data repeater 72 have input and output terminals. The chip 54 also carries the switching network 74, for example, configured by multiplexing means, for selectively connecting the inputs and outputs of the main audio module 70 and of the data repeater 72 to the inputs and outputs 60, 62, and 66 of the switching network.

In the embodiment shown in Figure 5, the connections between the terminals 56,58 and the audio module 70 and the data repeater 72 are those set up by the chip 54 when it senses that both of its connection ports 50 are connected to adjacent node units. Thus, it will be seen that the connection port 50 on the left hand side of Figure 5 as illustrated has its receive terminal 58 connected by way of the data input 60 to the input NETI of the audio module 70 whose output NETO is connected to the transmit terminal 56 of the other connection port 50. There is therefore a path through the chip 54 for received data at the left hand connection port 50. Similarly, the receive terminal 58 of the connection port 50 indicated on the right hand side of the chip 54 in Figure 5 is in communication with the transmit terminal 56 of the left hand connection port 50 by way of the repeater 72. The presence of the path through the repeater 72 ensures the formation of the logical ring.

If the chip 54 as shown in Figure 5 were in an end node unit having only a single one of its connection ports 50 connected to another node unit, the switching network 74 would configure the routings differently. In this respect, if the connection port 50 on the left hand side of the chip as shown were the one connected, its receive terminal 58 would be routed to the input to the audio module 70 as illustrated. However, the output NETO of the audio module 70 would be routed via the output 66 to the transmit terminal 56 of the left hand connection port 50. Where there is only a single connection port 50 which is connected therefore, the data repeater 72 is omitted from the circuit.

As indicated in Figure 5, the main audio module 70 also has inputs and outputs for receiving local audio signals as well as a control interface.

Figure 6 shows one construction of the audio module 70 as indicated in Figure 5. The audio module 70 receives information input by way of a connection port 50 at an input NETI and outputs information to a connection port 50 by way of an output NETO. It will also be apparent that there are effectively two data paths through the audio module 70. The first is a direct path from NETI to NETO by way of a logic circuit 82. This data route is used where audio module 70 is set in clock slave mode. The second route through the audio module from NETI to NETO is by way of input shift registers and latches 84, an audio RAM 86, and output shift registers 88. This routing is used where the audio module is in a node unit acting as a clock master.

Information is transferred around the network in a succession of frames.

As shown schematically in Figure 8a, each frame commences with a synchronising nibble S and a stream count nibble C and then incorporates isochronous data 1, an error check parity byte E, and packet data P. For example, in a preferred embodiment each frame is 16 bytes. The number of bytes reserved for isochronous data can be varied as the stream count nibble C carries information as to the relative size of the isochronous data and the packet data. Additionally and/or alternatively, a packet of packet data can be split between several frames.

In a preferred embodiment, and as shown in Figure 8b, several fields of packet data P from sequential frames are concatenated to form a packet (PAC) whose format is shown. The packet (PAC) includes address information A identifying the destination of data D incorporated within the packet (PAC). In addition, the packet (PAC) includes flags F, information N as to the number of bytes in the packet (PAC), padding bytes (PAD) to enable the packet to fit exactly in a number of fields of packet data P, and packet error check bytes CRC.

The address information A may comprise a count. It will be appreciated from Figure 5 that as the frames travel around the network, each frame is output to the output NETO of an audio module 70 by way of its logic circuit 82. This circuit preferably includes a decrementer to decrease the count. This enables the packet data in a frame to be delivered to the node unit at which the frame arrives when the count is zero.

The isochronous data carried by the frames is delivered to appropriate node units under the control of the microprocessor of the appropriate node unit.

Thus, for example, the flags F of packet data delivered to a node unit may identify for the node unit audio information to be utilised at the node unit. The microprocessor may then retrieve the identified isochronous data from the arriving frames.

It will be appreciated that audio information is time critical and also that the frames of information are delayed as they are transferred around the network. The delays which can be introduced are illustrated in Figure 7 which shows the relative timing of three frames transmitted through a ring from a master node unit and back to that master unit by way of two slave node units.

Figure 7a represents three successive frames each preceded by a sync pulse S as outputted by the network output NETO of the master node unit. Figure 7b shows the delay which might be introduced by the cables connecting the master node unit to the slave unit and 7c shows additional delay attributable to the passage of the signals through slave 1. 7d and 7e similarly show the delays experienced by passage through the second slave unit. In one of the slaves the signals will pass through a data repeater 72. The final, consequent, delay which has been imposed on the signal is shown at 7f which shows the return signal arriving at the input NETI of the master node unit.

It will be apparent from Figure 6 that the signal 7a output from the master NETO has been produced from the audio module 70 of the master node unit by outputting isochronous data from the audio RAM 86 by way of the output shift register 88. On returning to the audio module 70 of the master unit the signal is routed into the audio RAM 86 again. This enables successive isochronous data to be output again in frames having synchronising bits S determined by the master clock. What is more, logic circuitry associated with the audio module 70 is able to determine the delay which is introduced, for example, by incrementing a counter each time a packet of data arrives.

Whilst it is inevitable that delay will be experienced by the frames as they travel around the ring, as indicated graphically in Figure 7, the configuration of the slave units which pass on the signal directly from NETI to NETO keeps the delays to a minimum. Thus, the signals take the shortest, and therefore the quickest, possible path through each slave unit.

The frames are passed through a slave unit directly even if they carry information for use by that slave unit. In this case, the input frames are not only received but acted upon by the audio RAM 86 and logic circuitry associated therewith.

The frames generally include parity bits enabling each audio module to check the accuracy of the information received. Where an error is found the information in the outgoing signal at NETO can be overwritten by way of the output logic circuit 82.

It will be appreciated that modifications in and variations to the embodiments as described and illustrated may be made within the scope of the appended claims.

Claims (27)

1. A digital network comprising a plurality of node units interconnected to enable the communication of information between node units, each node unit having at least two connection ports, wherein the network is comprised of one or more logical rings, each said ring having two ends, and each node unit at the end of a ring having only a single one of its connection ports connected to other node units of that said ring.

2. A digital network as claimed in Claim 1, wherein a selected one of said node units forms the clock source for the network.

3. A digital network as claimed in Claim 1 or Claim 2, wherein each node unit is connected to the next node unit in a ring by way of a single cable.

4. A digital network as claimed in any preceding claim, arranged for the communication of audio information between node units.

5. A digital network as claimed in any preceding claim, wherein two connection ports of a node unit are selectively connectable by way of a switching network to an input and an output of an associated audio module of the node unit.

6. A digital network as claimed in Claim 5, wherein, when only one of the two connection ports associated with an audio module of a node unit is connected to another node unit, the input and output of said audio module are connected to said one connection port.

7. A digital network as claimed in Claim 5, wherein a data repeater is associated with the audio module of a node unit, and wherein, when both of the two connection ports associated with the audio module of said node unit are connected to another node unit, the switching network selectively connects inputs and outputs both of said audio module and of said data repeater to said two connection ports.

8. A digital network as claimed in any of Claims 5 to 7, wherein each said audio module has two paths between its input and its output, the path taken by incoming information being selectively determinable.

9. A digital network as claimed in Claim 8, wherein each said audio module has its input connected to its output such that any audio module which is not arranged as a clock source can pass information straight through from its input to its output.

10. A method of forming a digital network, comprising the steps of connecting a number of node units such that each node unit is connected to at least one other node unit, and on initialisation, causing said node units to communicate with one another to configure a selected one of the node units as the clock source for the formed network.

11. A method as claimed in Claim 10, wherein the network is tightly synchronised, isochronous data being synchronised to said clock source which distributes clock pulses around the whole formed network.

12. A method as claimed in Claim 10 or Claim 11, wherein each said node unit has at least two connection ports, and the network is comprised of one or more logical rings, the method further comprising the steps of, on initialisation, enabling end node units to generate set up signals, an end node unit having only a single one of its connection ports connected to other node units of the same ring.

13. A method as claimed in Claim 12, wherein, on receiving a set up signal, a node unit which has an external reference clock is enabled to designate itself as the clock source and to generate signals to prevent other node units becoming clock sources.

14. A method as claimed in Claim 13, wherein the set up signals generated by end node units are compared and, as a result of the comparison, one end node unit is selected, and wherein said set up signal to which said clock source node unit is responsive is generated by said selected end node unit.

15. A method of forming a digital network, comprising the steps of connecting a number of node units such that each node unit is connected to at least one other node unit, and causing each node unit to route connections from its inputs to its outputs in dependence upon the number of node units to which it is connected.

16. A method as claimed in Claim 15, wherein each node unit has two connection ports each having a receive terminal and a transmission terminal, and wherein, when only one connection port is connected, the node unit connects the receive and transmission terminals of said one connection port by way of a processing module of the node unit.

17. A method as claimed in Claim 15 or Claim 16, wherein each node unit has two connection ports each having a receive terminal and a transmission terminal, and wherein, when both connection ports are connected, the node unit connects the receive terminal of each connection port to the transmission terminal of the other connection port.

18. A method as claimed in Claim 17, wherein, the receive terminal of one connection port is connected to the transmission terminal of the other connection port by way of a processing module of the node unit, and wherein the receive terminal of the other connection port is connected to the transmission terminal of the one connection port by way of a data repeater.

19. A digital network formed by a method as claimed in any of Claims 10 to 18.

20. A digital network as claimed in Claim 19, and arranged as claimed in any of Claims 1 to 9.

21. A method of communicating information between node units interconnected to form a network, the method comprising the steps of transferring the information around the network in one or more frames, where the information incorporated in each frame comprises both isochronous data and packet data, and incorporating in each frame a count representing the destination address for the packet data in the frame, and the method further comprising the steps of incrementing or decrementing the count at each successive node unit, and delivering the packet data to the node unit whose address corresponds to the count incorporated in an arriving frame.

22. A method as claimed in Claim 21, further comprising the steps of decreasing the count by one at each node unit, and delivering the data to the node unit at which the count incorporated in an arriving frame is set at zero.

23. A method as claimed in Claim 21 or Claim 22, further comprising the steps of checking parity bits of each frame at each successive node unit, and replacing the information incorporated in the frame when the parity bit checks indicate the existence of an error.

24. A method as claimed in any of Claims 21 to 23, wherein each frame commences with a synchronising bit provided by a node unit designated as the clock source, and wherein all frames transferred around the network are applied to said clock source node unit for resynchronisation.

25. A digital network substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.

26. A method of forming a digital network substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.

27. A method of communicating information between node units interconnected to form a network substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.