GB2322210B - Processor having multiple instruction registers - Google Patents

Processor having multiple instruction registers

Info

Publication number
GB2322210B
GB2322210B GB9810670A GB9810670A GB2322210B GB 2322210 B GB2322210 B GB 2322210B GB 9810670 A GB9810670 A GB 9810670A GB 9810670 A GB9810670 A GB 9810670A GB 2322210 B GB2322210 B GB 2322210B
Authority
GB
United Kingdom
Prior art keywords
processor
multiple instruction
instruction registers
registers
instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB9810670A
Other versions
GB9810670D0 (en
GB2322210A (en
Inventor
Shunsuke Kamijo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP5352824A external-priority patent/JPH07200289A/en
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of GB9810670D0 publication Critical patent/GB9810670D0/en
Publication of GB2322210A publication Critical patent/GB2322210A/en
Application granted granted Critical
Publication of GB2322210B publication Critical patent/GB2322210B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016Decoding the operand specifier, e.g. specifier format
    • G06F9/30167Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145Instruction analysis, e.g. decoding, instruction word fields
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3818Decoding for concurrent execution
    • G06F9/3822Parallel decoding, e.g. parallel decode units
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
GB9810670A 1993-12-28 1994-11-29 Processor having multiple instruction registers Expired - Fee Related GB2322210B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP5352824A JPH07200289A (en) 1993-12-28 1993-12-28 Information processor
GB9424058A GB2285322B (en) 1993-12-28 1994-11-29 Processor having multiple instruction register

Publications (3)

Publication Number Publication Date
GB9810670D0 GB9810670D0 (en) 1998-07-15
GB2322210A GB2322210A (en) 1998-08-19
GB2322210B true GB2322210B (en) 1998-10-07

Family

ID=26306059

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9810670A Expired - Fee Related GB2322210B (en) 1993-12-28 1994-11-29 Processor having multiple instruction registers

Country Status (1)

Country Link
GB (1) GB2322210B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020032558A1 (en) * 2000-03-10 2002-03-14 Paul Strong Method and apparatus for enhancing the performance of a pipelined data processor

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1271127A (en) * 1968-10-31 1972-04-19 Hitachi Ltd A digital electronic computer including an instruction buffer
EP0490524A2 (en) * 1990-12-07 1992-06-17 International Business Machines Corporation Pipelined apparatus and method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1271127A (en) * 1968-10-31 1972-04-19 Hitachi Ltd A digital electronic computer including an instruction buffer
EP0490524A2 (en) * 1990-12-07 1992-06-17 International Business Machines Corporation Pipelined apparatus and method

Also Published As

Publication number Publication date
GB9810670D0 (en) 1998-07-15
GB2322210A (en) 1998-08-19

Similar Documents

Publication Publication Date Title
GB2296354B (en) Multithreaded processor
EP0509245A3 (en) Branch instruction processor
GB2278940B (en) Floating point arithmetic unit
GB9502864D0 (en) Cryptographic reduced instruction set processor
DE69424096T2 (en) Image processor
FR2705804B1 (en) Multi-tasking processor architecture.
EP0653849A3 (en) Efficient utilization of present state/next state registers.
EP0492968A3 (en) Multiple instruction issue
IL118823A0 (en) Computer processor
GB2283060B (en) Fan
GB9413501D0 (en) Pipelined simd-systolic array processor
GB2286265B (en) selectable processing registers
GB9311935D0 (en) Processor
DE69424086T2 (en) Image processor
GB9514433D0 (en) Computer instruction execution
DE69413447T2 (en) Processor
GB2293901B (en) Information processor
GB9405729D0 (en) Software execution systems
GB9206126D0 (en) Parallel vector processor architecture
DE69424980T2 (en) Processor
DE69416138D1 (en) SCALAR INTERRUPT ACKNOWLEDGE SYSTEM
GB2285322B (en) Processor having multiple instruction register
EP0620533A3 (en) Vector processor.
DE69427663D1 (en) Image processor
GB9416896D0 (en) Multi-compatible computer

Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20041129