GB2319442A - Filter reduces interference on cable - Google Patents

Abstract

An electrical filter (F1) can be remotely switched on demand in order to specifically route communications signals and thereby reduce the electrical loading and interference affects from electrical machinery (M1) as well as signal loading affects resulting from impressed electrical loads (L1) connected to any cable network.

Description

MAINS ADDRESSABT h TELEMETRY FILTER /BUFFER This invention relates to telemetry systems using mains cable as the electrical medium for the transmission and reception of electrical signals between devices connected to the mains cable.

Such systems operate using various methods to discriminate between carrier frequencies impressed onto the mains cable as well as interference or noise sources.

It has long been recognised that interference and/or the load impedance associated with the connection of plant or machinery to the mains system can adversely affect the performance of mains signalling systems.

According to the invention, there is provided an addressable electrical filter and impedance buffer which is intended to be placed in certain sections of mains cable forming a network of power and communication links within a buildings mains wiring system. The circuitry forming the impedance buffer is permanently connected in series with the mains cable while a secondary electrical filter can be switched in or out of circuit in parallel with the impedance buffer. The switching function can be wholly or partly controlled by a remote controlling device or devices which pass a frequency encoded unique address and associated control function to the filter switch. Additionally it is anticipated that it might be an advantage to provide a secondary method of ensuring that the filter switch reverts to the open condition (such as a timer) in the event that interference or cable loading conditions are such as to prevent communication to the switch from the remote controlling device or devices, in this way, sections of cable with an open filter switch will no longer degrade the signal path to remaining sections of cable.

The invention will now be described in greater detail, by way of example with reference to the accompanying schematic drawings of one embodiment of the buffer/ filter switch according with the invention.

Figure 1 is a block diagram showing the outline connection of a master control unit and a number of slave units. Non-ohmic connection between phases may be achieved through the provision of high voltage capacitors as illustrated by C1.

In order that signals within the transmission band may pass between the master and a given slave, any filter-buffer connected between the two units will have to be switched into the on state so as to provide a low impedance signal path for the in band transmissions. When the switch is in the off state, all electrical connections following beyond the filterbuffer will appear to be of a high impedance nature with considerably attenuated noise levels as seen by the transmission band circuitry.

For example, for communication between the master (M) and slave 1 (S 1) , filter-buffers F1 and F2 will have to be sequentially switched into the on state. The loading affects of the unswitched branches due to any low impedance load (LOAD 1) connected to those branches or sub branches will effectively be removed as far as operation within the transmission band is concerned. Most of the energy generated by master or slave is then available for communication between the two units.

Figure 2 shows a method of switching the transmission band signals across the buffer circuitry. Low voltage transmission band signals are isolated from the mains voltage by components C27,L5 and C28,L8 via a common point that is a reference to the logic control voltages, analogue supply voltages and the analogue voltages induced by the transformers.

When one ore more analogue gates SW1,SW2,SW3 or SW4 are closed due to the control inputs EN1,EN2,EN3 or EN4 asserted high (+5V), induced transmission band signal current can circulate in the primary coil of each transformer . As a result of this current, a secondary induced voltage will develop across transformer L8 as an output Conversely, when a slave is transmitting to a master , transformer L8 becomes the input and transformer L5 becomes the output. More than one analogue switch is shown in the example since a plurality of analogue switches will present a lower combined resistance to induced currents than a single switch. Capacitor C25 and C29 can be used to tune the two transformers for parallel resonance at mid transmission band frequencies if wide band signalling is not required. Diodes D19,D20,D21, and D22 can be used to afford protection to the analogue gates from transient voltages exceeding the analogue supply voltages.

The buffer circuitry comprises L6,L7,L9, L10 and C26 The buffer circuit has little affect on the mains transmission characteristics of the mains cable while at the same time providing a relatively large impedance and attenuation to transmission band signals.

Figure 3 shows one frequency domain method of demodulating the FM data stream and decoding the demodulated information into a packet of binary data which contains the address and other data as required.

FM data current transmitted by the master is induced into the primary coil of transformer L1 which can be tuned to operate as a tuned filter. The transmission band voltages forming across L1 primary winding sources AC. currents into the input of lOla which provides non linear amplification. IClb provides further amplification and ensures that the voltage wave form at the real time clock counter (rtcc) of IC2 slews fast enough to trigger the clock counter on each positive or negative transition.

In the example provided, a negative transition is required. Since the clock counter is only required to count voltage transitions, It is not important for the preceding non-linear amplifiers to preserve signal fidelity only the frequency of maximum and minimum voltage excursions is required.

IC2 samples the rtcc count at fixed intervals terminated by IC2 output B7 driving active low thus inhibiting any further inputs to the rtcc during the period required to read data from the rtcc file to another memory file, the rtcc file is then cleared and the output of B7 is either driven active high or placed in a tri state condition until the end of the next timing period. At a typical carrier of 125 KHz a typical timing period could be 200 micro seconds which would produce approximately 25% bit time jitter at 1200 baud. Bit jitter is transparent to the data manipulation within IC2 as the data is "clocked" synchronously with each rtcc timing period.

When either the appropriate address and/or command data is detected by the micro controller IC2, the output shown in this case on output B5.

(SW CTRL) is set high thus activating the analogue switches. Turning off is accomplished either by reception of the appropriate code or a certain time elapsing without a valid address received. This period being programmed into the micro controller as either a fixed delay or an adaptive delay algorithmically based on the rate of successful packets of data received.

The Filter Switch may also transmit data to the master or to other slaves. In this case, Currents output from the micro controller IC2 (IX~MOD) are fed to the drive amplifier Thi which drives the transformer to induce the transmission carrier current onto the mains circuit. When the Filter Switch is in receive mode no drive current is sourced to the base of the resulting in a high impedance connection between the collector of the and the received signal source via R1.

Figure 4 shows a time domain method of demodulating the FM data stream and decoding the demodulated information into a packet of binary data which contains the address and other data as required.

In this case, The current circulating in the primary of the isolating transformer sources carrier signals to the input of IC4 which is principally a phase locked loop. The demodulated signals are output from IC2 and fed to the input of a data port RXDTA of IC5 a micro controller. The micro controller is programmed to sample the logic level presented to the RXDTA input at a rate which is high compared to the baud rate.

When either the appropriate address and/or command data is detected by the micro controller IC5, the output shown in this case on output B5. (SWS RL) is set high thus activating the analogue switches.

Turning off is accomplished either by reception of the appropriate code or a certain time elapsing without a valid address received. This period being programmed into the micro controller as either a fixed delay or an adaptive delay algorithmically based on the rate of successful packets of data received.

The Filter Switch may also transmit data to the master or to other slaves. In this case, Currents output from the VCO IC4 (pins 8 and 9) are fed to the drive amplifier TR4 which drives the transformer to induce the transmission carrier current onto the mains circuit When the Filter Switch is in receive mode no drive current is sourced to the base of TR4 resulting in a high impedance connection between the collector of TR4 and the received signal source via R25.

It will be appreciated that various electricaVelectronic variations of the above electronic circuits could be employed by persons skilled in the art to attain the results and modus operandi described above.

Claims (8)

CLAIMS.

1. An electrical filter/ buffer and addressable switching means capable of remote operation to reduce the electrical loading characteristics and interference affectsof electrical equipment presented to frequency modulated signals and associated equipment when placed between electrical machinery or electrical load / loads and any specified length of mains powered connecting cable.

2. An apparatus as claimed in claim 1 incorporating electronic timing means to initiate the opening of a bypass shunt for frequency modulated signals across the electronic filter/buffer

3. An apparatus as claimed in any preceding claim wherein the initiation of the signal bypass shunt is modified algorithmically based on the rate of successful packets of data received.

4. An apparatus as claimed in any preceding claim incorporating electronic means to generate frequency modulated electrical signals capable of communicating data to a master control or other fm receiver.

5. An apparatus as claimed in claim 4. incorporating a means of data collection relating to the monitoring of performance or status of other equipment.

6. An apparatus as claimed in any preceding claim wherein the apparatus comprises one ore more electrical outputs for transmitted data or for the control of external electrical machinery or circuits.

7. An apparatus as claimed in claim 6. incorporating a means of data collection relating to the monitoring of performance or status of the apparatus itself.

8. An apparatus as claimed in any preceding claim intended for use in any specified electrical cable which is not intended for mains power connection or distribution