GB2317775A - Binarizing compensation apparatus and method - Google Patents

Abstract

An apparatus and a method compensates a binarized image signal of the printed circuit board taken by a CCD camera. First and second memories 602a, 602G store an initial binarizing reference brightness level and a reference sum of a number of pixels with respect to an electronic component to be binarizing compensated therein, respectively. A comparator circuit 604 firstly compares each of brightness levels of pixels of an image signal of the electronic component binarized by an analog-to-digital converter with the initial binarizing reference brightness level. A counter circuit 606 counts a number of the pixels having brightness levels higher than the initial binarizing reference brightness level based on the first comparison result. A second comparator 608c compares the number of the pixels counted by the counter circuit 606 with the reference sum of a number of pixels stored in the second memory 602G to control the initial binarizing reference value based on the second comparison result 608G. The apparatus binarizes image signals from a printed circuit board by varying a binarizing reference brightness level to thereby have efficiency which is not influenced by change of a periphery environment.

Description

BINARIZING CONPENSATION APPARATUS AND METHOD Backaround of the Invention 1. Field of the Invention The present invention relates to an image processing system, more particularly, to an apparatus and a method for compensating a binarized image signal of the printed circuit board(PCB) taken by a camera.

2. Description of the Prior Art Generally, an image processing system is a system which receives an image with respect to the components by using a camera and adjusts positions of the electronic components based on the received image after electronic components are mounted on a PCB by a chip mounter.

U.S. Patent No. 4,903,316 issued to Yasuo Hongo on February 20, 1990 discloses a binarizing apparatus for line graphic images for use in optical character readers, character-and-pattern input devices, or the like. The conventional binarizing apparatus is used for optical character readers or character-and-graphic input devices, in which a sharp binary image can be obtained even from low-contrast character lines (or line segments) by discriminating a line graphic from stains wider than the character lines or from blurs in the background thereof. Eight surrounding subwindows are disposed around a target subwindow enclosing a target pixel, the surrounding subwindows being separated from each other at a distance larger than the character line width, and each of the subwindows having 3x3 pixels. The average density value of the respective subwindow is calculated to thereby compare the respective density values of the target subwindow and each surrounding subwindow or compare the density values of the respective surrounding subwindows.

Consequently, whether the target pixel belongs to character line or whether it does not belong thereto, is judged to thereby perform binarizing. However, in the patent of Yasuo Hongo, as a periphery environment varies during binarizing the image of the adjusting component, the absolute reference value should be adjusted.

FIG. 1 shows a construction of a conventional image processing apparatus 10. FIG. 2 shows an image of the adjusting component. FIG. 3 shows a relation between a sum of pixel number and brightness level of the image with respect to the adjusting component on which is mounted PCB according to the conventional image processing apparatus 10 of FIG. 1. FIG. 4 shows an image of the adjusting component binarized by means of the conventional image processing apparatus 10 of FIG. 1.

The conventional image processing apparatus 10 includes a charge coupled device (CCD) camera 102, an analog-to-digital converter (ADC) 104, a sync separator 106, an address counter 108, a frame memory 110, a digital-analog converter (DAC) 112, a monitor 114, and a microprocessor 116.

The CCD camera 102 takes analog images of an adjusting component on which is mounted a PCB and feeds the analog images to A/D converter 104 and the sync separator 106.

Suppose that the adjusting component has a image as shown in FIG. 2 and has brightness characteristics and an absolute reference value RT as shown in FIG. 3.

The A/D converter 104 converts the analog images of the adjusting components from the CCD camera 102 into digital images of the adjusting components on the basis of an absolute reference value RT1. That is, a first image less than brightness level 200 is inverted into logical 0 and a second image which is equal to or higher than brightness level 200 is inverted into logical 1. At this time, if a periphery environment varies during binarizing the image of the adjusting component, the image of the adjusting component can be binarized into an image shown in FIG. 4 different from the original image of FIG. 2. The A/D converter 104 also stores the binarized images in the frame memory 110.

The sync separator 106 separates a synchronizing signal from the analog images of the adjusting components from the CCD camera 102 and supplies the separated synchronizing signal to the address counter 108, the frame memory 110, and DAC 112. The address counter 108 counts the synchronizing signal from the sync separator 106 to generate a memory address in order to store the binarized image signal from the ADC 104 to the frame memory 110, and feeds the memory address thereto. The frame memory 110 stores the binarized images from the ADC 104 in the address generated from the address counter 108 under a control of the microprocessor 116.

The D/A converter 112 converts the binarized images which are stored in the frame memory 110 into analog signals synchronously with a synchronizing signal from the sync separator 106 and feeds the analog signals to the monitor 114. The monitor 114 displays the analog signals from the D/A converter 112. The microprocessor 116 controls an operation of the frame memory 110.

The conventional image processing apparatus binarizes the image of the adjusting component taken by the CCD camera on the basis of the absolute reference value. As a periphery environment varies during binarizing the image of the adjusting component, the absolute reference value should be adjusted to thereby delay the binarizing process. When the resolute threshold value is not adjusted, the image of the adjusting component can be binarized into an image shown in FIG. 4 different from the original image of FIG. 2.

Summary of the Invention Therefore, it is an object of the present invention, for the purpose of solving the above mentioned problems, to provide a binarizing compensation apparatus and method thereof for compensating a binarized image of an electronic component including a plurality of pixels which are not influenced by a change of a periphery environment.

In order to accomplish the above object, there is provided a binarizing compensation apparatus, the apparatus comprising: first and second memories for storing an initial binarizing reference brightness level and a reference sum of a number of pixels with respect to an electronic component to be binarizing compensated, respectively; a comparator circuit for firstly comparing each of brightness levels of pixels of an image signal of the electronic component binarized by an analog-to-digital converter with the initial binarizing reference brightness level; a counter circuit for counting a number of the pixels having brightness levels higher than the initial binarizing reference brightness level based on the first comparison result; and a controller for secondly comparing the number of the pixels counted by the counter circuit with the reference sum of a number of pixels stored in the second memory to control the initial binarizing reference value based on the second comparison result.

Also, there is provided a binarizing compensation method, the method comprising the steps of: (a) storing an initial binarizing reference brightness level and a reference sum of a number of pixels with respect to an electronic component to be binarizing compensated; (b) receiving a binarized image signal of the electronic component, and firstly comparing each of brightness levels of pixels of the binarized image signal with the initial binarizing reference brightness level; (c) counting a number of the pixels having brightness levels higher than the initial binarizing reference brightness level based on the first comparison result of step (b); (d) secondly comparing the reference sum of a number of pixels stored in step (a) with the number of pixels counted in step (c); and (e) controlling the initial binarizing reference brightness level based on the second comparison of step (d).

The present invention binarizes image signals from a printed circuit board by varying a binarizing reference brightness level to thereby have efficiency which is not influenced by change of a periphery environment.

Other objects and further features of the present invention will become apparent from the detailed description when read in conjunction with the attached drawings.

Brief Description of the Drawings The above objects and advantages of the present invention will become more apparent by describing in detail a preferred embodiment thereof with reference to the attached drawings in which: FIG. 1 is a block diagram showing a construction of a conventional image processing apparatus; FIG. 2 is a view for showing an image of a component to be binarized; FIG. 3 is a view for showing a brightness characteristic of the image of FIG. 2 in order to explain a binarizing method according to the conventional image processing apparatus 10 of FIG. 1; FIG. 4 is a view for showing a binarized state of an image of the component binarized by means of the conventional image processing apparatus of FIG. 1.

FIG. 5 is a block diagram showing a configuration of an image processing system including a binarizing compensation apparatus according to an embodiment of the present invention; FIG. 6 is a circuitry diagram for showing an example of a binarizing compensation apparatus shown in FIG. 5; FIG. 7 is an operating timing chart of the binarizing compensation apparatus shown in FIG. 6; FIGs. 8(A) and (B) are views for showing a brightness characteristic of the image of FIG. 2 before and after compensating the image according to the binarizing compensation apparatus shown in FIG. 6, respectively; FIGs. 9(A) and 9(B) are views for showing a binarized state of the image of FIG. 2 before and after compensating the image according to the binarizing compensation apparatus shown in FIG. 6, respectively; and FIG. 10 is a flow chart for illustrating a binarizing compensation method according to an embodiment of the present invention.

Description of the Preferred Embodiment A description will be given below in detail, with reference to the accompanying drawings, of an embodiment of the present invention. FIG. 5 shows a configuration of an image processing system including a binarizing compensation apparatus 50 according to an embodiment of the present invention. The image processing apparatus 50 includes a charge coupled device (CCD) camera 502, an analog-to-digital converter (ADC) 504, a sync separator 506, an address counter 508, a binarizing compensation apparatus 60, a frame memory 510, a digital-analog converter (DAC) 512, a monitor 514, and a microprocessor 516.

The CCD camera 502 takes analog images of a component to be binarized on which is mounted a PCB (not shown) and feeds the analog images to ADC 504 and the sync separator 506.

The A/D converter 504 converts the analog images of the components from the CCD camera 502 into binary images of the component. The ADC 504 also feeds the binarized images to binarizing compensation apparatus 60. The sync separator 506 separates a synchronizing signal including horizontal and vertical synchronizing signals from the analog images of the adjusting components from the CCD camera 502 and supplies the separated synchronizing signal to the address counter 508, the binarizing compensation apparatus 60, and DAC 512.

The binarizing compensation apparatus 60 compensates for the binarized images from the ADC 504 in synchronism with the synchronizing signal separated from the sync separator 506 and outputs the compensated images to the frame memory 510. The frame memory 610 stores the binarized images from the ADC 104 in the address generated from the address counter 108 under a control of the microprocessor 516. The D/A converter 112 converts the binarized images which are stored in the frame memory 110 into analog signals synchronously with a synchronizing signal from the sync separator 506 and feeds the analog signals to the monitor 514. The monitor 514 displays the analog signals from the D/A converter 512. The microprocessor 516 controls an operation of the frame memory 510.

FIG. 6 shows a configuration of a binarizing compensation apparatus 60 shown in FIG. 5. The binarizing compensation apparatus 60 includes a first and second memories 602a and 602b, a comparator circuit 604, a counter circuit 606, and a control section 608.

The first memory 602a stores an initial binarizing reference brightness level IR with respect to an electronic component to be binarizing compensated therein. The second memory 602b stores a reference sum PS of a number of pixels with respect to the electronic component to be binarizing compensated therein.

The comparator circuit 604 includes a first input terminal for receiving the binarized image signal from the ADC 504, and a second input terminal for receiving the reference brightness level RB from a first register 608a of the control section 608 and an output terminal.

The comparator circuit 604 firstly compares each of the brightness levels of pixels of the binarized image signal from ADC 504 with the initial binarizing reference brightness level IR from a register 608a and outputs the first comparison signal CR to the counter circuit 606 and a switch 610. When each brightness level is higher than the initial binarizing reference brightness level IR, the comparator circuit 604 outputs a high logic signal to a counter circuit 606 and the switch 610. On the contrary, when each brightness level is equal to or lower than the initial binarizing reference brightness level IR, the comparator circuit 604 outputs a low logic signal to the counter circuit 606 and the switch 610. The output signal CR from the comparator circuit 604 to the counter circuit 606 and the switch 610 has a waveform as shown in FIG. 7B.

The counter circuit 606 includes a first AND gate 606a and a counter 606b. The AND gate 606a firstly ANDs an output signal CR of the comparator circuit 604 and the analog-to-digital converter clock ADC CLK from the ADC 504 and outputs a predetermined clock signal AND 1 to a counter 606b. The counter 606b is connected to the output terminal of the first AND gate 606b, is cleared by the vertical synchronizing signal V.sync from the sync separator 506, and counts the predetermined clock signal AND generated by the first AND gate 606a to generate a count signal CS. The count signal CS is applied to the control section 608. That is, the counter circuit 606 counts a number of the pixels having brightness levels higher than the reference brightness level based on the first comparison result of the comparator circuit 604.

The control section 608 includes first and second registers 608a and 608b, a subtracter 606c, a comparator 606d, a delay circuit 606e, a D type flipflop 606f, and a second AND gate 606g.

The first register 608a is connected to the first memory 602a, reads out the initial binarizing reference brightness level IR from a first memory 602a, and temporarily stores it therein, and feeds the initial binarizing reference brightness level IR to the comparator 604 and the subtracter 608c.

The subtracter 608b subtracts a predetermined subtracting value SV from the initial binarizing reference brightness level IR from the first register 608a to control initial binarizing reference brightness level IR. In an embodiment of the present invention, preferably, the initial binarizing reference brightness level IR is greater than the predetermined subtracting value SV.

The comparator 608c includes a first input terminal for receiving the reference sum PS of the number of pixels stored in the second memory 602b and the count signal CS from the counter circuit 606 and an output for outputting the comparison result signal. The comparator 608d secondly compares the received count signal through the second input terminal thereof with the reference sum of the number of pixels through the first input terminal and outputs the second comparison result CR2 to the delay circuit 608d. When the received count signal from the counter 606b is greater than the reference sum PS of the number of pixels, the comparator 608c outputs a low logic signal to the delay circuit 608d. On the contrary, when the received count signal from the counter 606c is equal to or smaller than the reference sum PS of the number of pixels, the comparator 608 outputs a high logic signal to the delay circuit 608d.

The delay circuit 608d is connected to the output terminal of the comparator 608c, delays the second comparison signal CR2 from the comparator 608c, and outputs the delayed signal D1 to the D type flip-flop 608e.

The D-type flip-flop 608f has a clock terminal CLX for receiving the vertical synchronizing signal V.sync from the sync separator 506, a data input terminal D for receiving the delayed signal D1 from the delay circuit 608b, and an output terminal Q for outputting the output signal Q1. The D type flip-flop 608e latches the delayed signal D1 from the delay circuit 608d in response to the vertical synchronizing signal V. sync from the ADC 504.

The result signal Q1 of the D type flip-flop 608e is initially HIGH. When the vertical synchronizing signal V.sync changes from "0" to "1" at times tl and t2, the Q1 output takes on the levels present at D.

That is, Q stays HIGH at times tl and t2 because the D1 is still HIGH. Even though the D input level changes between t2 and t5, it has no effect on the result signal Q1. When the vertical synchronizing signal V.sync changes from "0" to "1' at time t5, the delayed signal D1 input is LOW; thus the result signal Q1 of the D type flip-flop 608e changes from a high state to a low state.

The second AND gate 608f includes a first input terminal for receiving the output signal Q1 of the D type flip-flop 608e and a second input terminal for receiving the vertical synchronizing signal V.sync from the sync separator 506, and output terminal connected to the enable terminal EN of the subtracter 608b. The second AND gate 608f secondly ANDs the latched signal D1 from the D type flip-flop 608e and the vertical sync signal V.sync to generate a signal in order to control the subtracter 608b.

That is, the control section 608 secondly compares the number of the pixels counted by the counter circuit 606 with the reference sum of a number of pixels PS stored in the second memory 602b and controls the reference value based on the second comparison result. The control section 608 further includes a second register 608g for storing a predetermined subtracting value SV to be supplied to subtracter 608b.

FIG. 7 is an operating timing chart of the binarizing compensation apparatus shown in FIG. 6. As shown in FIG 7(A), an ADC CLX is a clock generated by the ADC 504 and is applied to a second input terminal of the first AND gate 606a. As shown in FIG 7(B), a CR1 is an output signal of the comparator circuit 604 and is applied to a first input terminal of the first AND gate 606a and a switch 610. As shown in FIG 7(C), an AND 1 is output signal of the first AND gate 606a and is applied to counter 606b. As shown in FIG. 7(D), a CR2 is an output signal of the comparator 608d and is applied to the delay circuit 608d.

As shown in FIG. 7(E), D1 is a delayed signal from the delay circuit 608e and is applied to the data input terminal D of the D type flip-flop 608e. As shown in FIG. 7(F), a V.sync is a vertical synchronizing signal from the sync separator 506 and is applied to the clock terminal CLX of D type flip-flop 608e and a second input terminal of the second AND gate 608f. As shown in FIG. 7(G), a Q1 is an output signal of the D type flipflop 608f and a first input terminal of the AND gate 608f. As shown in FIG. 7(H), an AND2 is an output signal of the second AND gate 608f and is applied to an enabling terminal EN of the subtracter 608c.

A first time interval T1 designates one field period of the image of the component. A second time interval T3 designates a period which performs one subtraction by means of the subtracter 608b. A third time interval T3 is a delay time by the delay circuit 608d. A time tl represents a time in which the operation of compensating for the binarized image signal from the ADC 504 finishes.

FIG. 8A shows a brightness characteristic of an image based on the initial reference brightness level IR before compensating for the original image of component of FIG. 2. An IR is the initial binarizing reference brightness level which is stored in the first memory 602a. A first area A represents first pixels having a low level, and a second area B represents second pixels having a high level. FIG. 8B shows a brightness characteristic of an image based on the compensated reference brightness level after compensating for the original image of the component of FIG. 2. A CB is an optimal reference brightness level adjusted by the present invention. A third area A2 represents first compensated pixels of the first pixels having a low level, and the fourth area B2 represents second compensated pixels of the second pixels having a high level.

FIGs. 9(A) and 9(B) show an image based on the initial reference brightness level before and after compensating for the original image of the component of FIG. 2, respectively. Referring to FIGs. 9(A)and 9(B), the image of FIG. 9(B) which is compensated according to the present invention is more similar to the image of FIG. 9(A) before compensating for the image with respect to the original image of FIG. 2.

Hereinafter, an operation of the method for compensating a binarized image signal according to an embodiment of the present invention with reference to FIG. 9 will be explained.

In step S901, an initial binarizing reference brightness level IR, a reference sum PS of a number of pixels, and a predetermined subtracting value SV are stored in the first memory 602a, the second memory 602b, and the second register 608b, respectively. In step S902, the binarized image signal of the component from the ADC 504 is input to a first input terminal of a comparator circuit 604, and the first register 608a reads out the initial binarizing reference brightness level IR from the first memory 602a (step S903) and outputs the read initial binarizing reference brightness level IR to a second input terminal of the comparator circuit 604.

The comparator circuit 604 firstly compares each of brightness levels of pixels of the binarized image signal from ADC 504 with the initial binarizing reference brightness level IR from the first register 608a (step S903). As a result of the comparison in step S903, when each brightness level is higher than the initial binarizing reference brightness level IR, the comparator circuit 604 outputs a high logic signal to a counter circuit 606 and the switch 610 (step S904). On the contrary, when each brightness level is equal to or lower than the initial reference brightness level IR, the comparator 604 outputs a low logic signal to the counter circuit 606 and the switch 610 (step S905). The output signal CR from the comparator circuit 604 to the counter circuit 606 and the switch 610 has a waveform as shown in FIG. 7B.

In step S906, the first AND gate 606a ANDs the result signal CR of the comparator circuit 604 and an ADC clock ADC CLX from the ADC 504 as shown in FIG. 7A and outputs a clock signal AND 1 into the counter 606b.

In step S907, the counter 606b receives the clock signal AND1 from the first AND gate 606a and counts the clock signal AND1 in response to the vertical synchronizing signal V.sync from the sync separator 506 and outputs a count signal CS to the second input terminal of a comparator 608c.

In step S908, the comparator 608d compares the reference sum PS of the number of pixels which is stored in a second memory 602b with the count signal CS from the counter 606b. As a result of the comparison in step S908, when the reference sum PS of the number of pixels is greater than the count signal CS, the comparator 608d outputs a high logic signal to a delay circuit 608e (step S909). On the contrary, when the reference sum PS of the number of pixels is equal to or less than the count signal CS, the comparator 608d outputs a high logic signal to a delay circuit 608e (step S910).

In step S911, the delay circuit 608e delays the comparison result signal CR2 from the comparator 608e by a predetermined time interval and feeds the delayed signal D1 to a data input terminal D of the D type flip-flop 608f. In step S912, D type flip-flop latches the delayed signal D1 from the delay circuit 608b in response to the vertical synchronizing signal V.sync from the sync separator 506 of FIG. 5 and outputs the latched signal Q1 to a first terminal of the second AND gate 608g. In step S913, the second AND gate 608 ANDs the latched signal Q1 from the D type flip-flop 608g and the vertical synchronizing signal V.sync from the sync separator 506 and outputs a signal in order to control the subtracter 608c. The control signal is applied to a clock terminal of subtracter 608c.

In step S914, the subtracter 608c subtracts the subtracting value SV from the second register 608b from the initial reference bright level IR provided by the first register 608a in response to the control signal AND2 from the second AND gate 608f. The subtracting result value IR-SV is applied to the first register 608a. In step S915, the first register 608a sets the subtracting result value IR-SV as a new binarizing reference brightness level and outputs the new binarizing reference brightness level IR-SV to the comparator circuit 604. And the routine returns to step S903 and the following steps are repeated until the optimal reference brightness level is searched. That is, the routine is repeated until the output signal of the counter 606 is more than the reference sum PS of the number of pixels.

As mentioned above, the present invention binarizes image signals from a printed circuit board by varying a binarizing reference brightness level to thereby have efficiency which is not influenced by change of a periphery environment.

The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

Claims (19)

1. An binarizing compensation apparatus, said apparatus comprising: first and second memories for storing an initial binarizing reference brightness level and a reference sum of a number of pixels with respect to an electronic component to be binarizing compensated, respectively; a comparator circuit for firstly comparing each of brightness levels of pixels of an image signal of the electronic component binarized by an analog-to-digital converter with the initial binarizing reference brightness level; a counter circuit for counting a number of the pixels having brightness levels higher than the initial binarizing reference brightness level based on the first comparison result; and a controller for secondly comparing the number of the pixels counted by the counter circuit with the reference sum of a number of pixels stored in the second memory to control the initial binarizing reference value based on the second comparison result.

2. The binarizing compensation apparatus in accordance with claim 1, wherein as the first comparison result, when each of brightness levels of pixels of a binarized image signal of the electronic component is higher than the initial binarizing reference brightness level the comparator circuit outputs a high logic signal, and when each of brightness levels of pixels of a binarized image signal of the electronic component is equal to or lower than the initial binarizing reference brightness level the comparator circuit outputs a low logic signal.

3. The binarizing compensation apparatus in accordance with claim 1, wherein the counter circuit includes a first logic gate for firstly logical operating an output signal of the comparator circuit and the analog-to-digital converter clock from the analog-todigital converter to generate a predetermined clock signal; and a counter for counting the predetermined clock signal generated by the first logic gate to generate a count signal.

4. The binarizing compensation apparatus in accordance with claim 3, wherein the first logic gate includes a first AND gate for firstly ANDing an output signal of the comparator circuit and the analog-todigital converter clock from the analog-to-digital converter to generate the predetermined clock signal.

5. The binarizing compensation apparatus in accordance with claim 1, wherein the control section includes a first register for reading out the initial binarizing reference brightness level from the first memory and for temporarily storing the initial binarizing reference brightness level; a subtracter for subtracting the predetermined subtracting value from the initial binarizing reference brightness level stored in the first register to control the initial binarizing reference brightness level; a comparator for thirdly comparing the reference sum of the number of pixels stored in the second memory with the counted number of pixels from the counter circuit to output a third comparison result signal; a delay circuit for delaying the third comparison result signal from the comparator; a D type flip-flop for latching the delayed signal from the delay circuit in response to the vertical synchronizing signal from the analog-to-digital converter; and a second logic gate for secondly logical operating the latched signal from the D type flip-flop and the vertical sync signal to generate a signal for controlling the subtracter.

6. The binarizing compensation apparatus in accordance with claim 5, wherein the initial binarizing reference brightness level stored in the first register is greater than the predetermined subtracting value.

7. The binarizing compensation apparatus in accordance with claim 5, wherein as the third comparison result of the comparator, when the reference sum of the number of pixels is greater than the counted number of pixels the comparator outputs a high logic signal, and when the reference sum of the number of pixels is equal to or smaller than the counted number of pixels the comparator outputs a high logic signal.

8. The binarizing compensation apparatus in accordance with claim 5, wherein the D type flip-flop includes a clock terminal for receiving the vertical synchronizing signal from a sync separator of the image processing system, a data input terminal for receiving the delayed signal from the delay circuit, and an output terminal for outputting the output signal.

9. The binarizing compensation apparatus in accordance with claim 5, wherein the second logic gate includes a second AND gate for secondly ANDing the latched signal from the D type flip-flop and the vertical sync signal to generate a signal for controlling the subtracter.

10. The binarizing compensation apparatus in accordance with claim 5, further comprising a second register for storing the predetermined subtracting value.

11. An binarizing compensation apparatus, said apparatus comprising: first and second memories for storing an initial binarizing reference brightness level and a reference sum of a number of pixels with respect to an electronic component to be binarizing compensated, respectively; a comparator circuit for firstly comparing each of brightness levels of pixels of an image signal of the electronic component binarized by an analog-to-digital converter with the initial binarizing reference brightness level; a counter circuit for counting a number of the pixels having brightness levels higher than the initial binarizing reference brightness level based on the first comparison result; a first register for reading out the initial binarizing reference brightness level from the first memory and for temporarily storing the initial binarizing reference brightness level; a subtracter for subtracting the predetermined subtracting value from the initial binarizing reference brightness level stored in the first register to control the initial binarizing reference brightness level; a comparator for thirdly comparing the reference sum of the number of pixels stored in the second memory with the counted number of pixels from the counter circuit to output a third comparison result signal; a delay circuit for delaying the third comparison result signal from the comparator; a D type flip-flop for latching the delayed signal from the delay circuit in response to the vertical synchronizing signal from the analog-to-digital converter; and a first logic gate for first logical operating the latched signal from the D type flip-flop and the vertical sync signal to generate a signal for controlling the subtracter.

12. The binarizing compensation apparatus in accordance with claim 11, wherein the first logic gate includes a first AND gate for firstly ANDing the latched signal from the D type flip-flop and the vertical sync signal to generate a signal for controlling the subtracter.

13. The binarizing compensation apparatus in accordance with claim 11, wherein the counter circuit includes a second logic gate for secondly logical operating an output signal of the comparator circuit and the analog-to-digital converter clock from the analog-todigital converter to generate a predetermined clock signal; and a counter for counting the predetermined clock signal generated by the second logic gate to generate a count signal.

14. The binarizing compensation apparatus in accordance with claim 13, wherein the second logic gate includes a second AND gate for secondly ANDing an output signal of the comparator circuit and the analogto-digital converter clock from the analog-to-digital converter to generate the predetermined clock signal.

15. A binarizing compensation method, said method comprising the steps of: (a) storing an initial binarizing reference brightness level and a reference sum of a number of pixels with respect to an electronic component to be binarizing compensated; (b) receiving a binarized image signal of the electronic component, and firstly comparing each of brightness levels of pixels of the binarized image signal with the initial binarizing reference brightness level; (c) counting a number of the pixels having brightness levels higher than the initial binarizing reference brightness level based on the first comparison result of step (b); (d) secondly comparing the reference sum of a number of pixels stored in step (a) with the number of pixels counted in step (c); and (e) controlling the initial binarizing reference brightness level based on the second comparison of step (d).

16. The binarizing compensation method in accordance with claim 15, wherein as the first comparison result of step (b), when each of the brightness levels of pixels of the binarized image signal is higher than the initial binarizing reference brightness level outputting a high logic signal, and when the each of brightness levels of pixels of the binarized image signal is equal to or lower than the initial binarizing reference brightness level outputting a low logic signal.

17. The binarizing compensation method in accordance with claim 15, wherein as the second comparison result of step (b), when the stored reference sum of a number of pixels is greater than the counted number of pixels outputting a high logic signal, and when the stored reference sum of a number of pixels is equal to or less than the counted number of pixels outputting a low logic signal.

18. The binarizing compensation method in accordance with claim 15, wherein step (e) includes (e-l) delaying the comparison result signal of step (d) by a predetermined time interval to output a delayed signal; (e-2) latching the delayed signal in response to a vertical synchronizing signal to output a latching signal; (e-3) logically operating the latched signal and the vertical synchronizing signal to thereby generate a signal for controlling the initial binarizing reference brightness level; and (e-4) controlling a subtracting operating of a predetermined subtracting value from the initial binarizing reference brightness level according a logic state of the control signal for the initial binarizing reference brightness level.

19. The binarizing compensation method in accordance with claim 18, wherein step (e-4) includes stopping the subtracting operation, and when the control signal is at logical high level when the control signal is at logical low level, and subtracting the predetermined subtracting value from the initial binarizing reference brightness level; and setting the subtracting value as a new binarizing reference brightness level, and returning to a step of comparing each of brightness levels of pixels of the binarized image signal with the initial binarizing reference brightness level.